UNITED STATES DISTRICT COURT
`WESTERN DISTRICT OF TEXAS
`AUSTIN DIVISION
`
`AQUILA INNOVATIONS, INC., a
`Delaware corporation,
`
`Plaintiffs,
`
`v.
`ADVANCED MICRO DEVICES, INC., a
`Delaware corporation,
`
`Defendant.
`
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`)
`)
`)
`)
`)
`)
`)
`)
`)
`)
`
`No. 1:18-cv-00554-LY
`
`DECLARATION OF DR. DOUGLAS HOLBERG
`U.S. PATENT NO. 6,239,614
`
`AMD EX1015
`U.S. Patent No. 6,239,614
`
`0001
`
`

`

`TABLE OF CONTENTS
`
`I.
`
`II.
`
`III.
`
`IV.
`
`V.
`
`VI.
`
`INTRODUCTION .............................................................................................................. 3
`
`MATERIALS CONSIDERED ........................................................................................... 3
`
`EDUCATION AND EXPERIENCE .................................................................................. 4
`
`RELEVANT LEGAL PRINCIPLES AND GUIDELINES ............................................... 6
`
`A.
`
`B.
`
`Claim Construction ................................................................................................. 6
`
`The Level of Ordinary Skill in the Art.................................................................... 8
`
`BACKGROUND OF THE ‘614 PATENT ......................................................................... 9
`
`CLAIM CONSTRUCTION .............................................................................................. 11
`
`A.
`
`B.
`
`C.
`
`D.
`
`E.
`
`F.
`
`G.
`
`“unit cells” ............................................................................................................ 11
`
`“a unit cell array comprised of first and second unit cells laid in array form” ..... 16
`
`“unit cell array” ..................................................................................................... 19
`
`“a power switch” ................................................................................................... 19
`
`“a power switch disposed around said unit cell array and comprised of a plurality
`of third MOS transistors” ...................................................................................... 22
`
`“a plurality of input / output circuits disposed around said unit cell array” ......... 25
`
`“parts of said power switch disposed within said unit cell array” ........................ 27
`
`VII. OTHER COMMENTS...................................................................................................... 29
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`Declaration of Dr. Douglas Holberg – ‘614 Patent – Case No. 1:18-cv-00554-LY
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`Page 2 of 29
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`I.
`
`INTRODUCTION
`
`1.
`
`I have been asked by Defendant Advanced Micro Devices, Inc. (“AMD”) to give
`
`expert opinions and testimony regarding the claim construction of certain terms for U.S. Patent
`
`6,239,614 (“the ‘614 patent”). Unless otherwise noted, the statements made herein are based on
`
`my personal knowledge, and if called to testify, I could and would testify competently and
`
`truthfully with regards to this matter.
`
`2.
`
`For my work in connection with this case, I am being compensated at my standard
`
`consulting rate of $400 per hour. My compensation does not depend on my testimony rendered
`
`or on the outcome of this case.
`
`3.
`
`My opinions regarding claim construction are based on my education, experience
`
`and training, my review of the materials considered (below), and my understanding of the
`
`parties’ proposed constructions as of the date of this declaration. If the parties alter those
`
`constructions after this declaration is submitted, I may, if appropriate and permitted, submit a
`
`supplemental declaration addressing any new constructions.
`
`II.
`
`MATERIALS CONSIDERED
`
`4.
`
`In connection with this declaration, I have read the ‘614 patent and the related file
`
`histories, and any other documents cited in this declaration. I have reviewed the proposed
`
`constructions and evidence disclosed in the parties’ Joint Claim Construction Statement in
`
`connection with these claim construction proceedings. I have also reviewed the following
`
`extrinsic evidence as part of my analysis:
`
`
`
`
`
`
`
`
`Weste, Neil H. E. et al., Principles of CMOS VLSI Design (2d ed. 1993);
`Laplante, P.A., Comprehensive Dictionary of Electrical Engineering (CRC Press
`1999);
`Graf, R.F., Modern Dictionary of Electronics (7th ed. 1999);
`Merriam-Webster’s Collegiate Dictionary (10th ed. 2001);
`Webster's Third New International Dictionary (2002).
`
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`0003
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`III.
`
`EDUCATION AND EXPERIENCE
`
`5.
`
`My qualifications are stated more fully in my curriculum vitae. See Ex. A,
`
`Curriculum Vitae of Dr. Douglas Holberg. As reflected in my curriculum vitae (and as explained
`
`in more detail below), I have experience with the technology described in the ‘614 Patent,
`
`including resistors, capacitors, inductors, transistors, transformers, oscillators, operational
`
`amplifiers, comparators, CMOS integrated-circuit technology, analog/digital mixed-signal
`
`circuits, floor-planning and layout of CMOS integrated circuits, standard cells, custom cells, gate
`
`arrays, I/O cells, embedded flash, and tools used to design, construct, and verify integrated
`
`circuits (CAD tools). The following paragraphs provide a brief summary of my qualifications.
`
`6.
`
`I have over 40 years of experience in the electronics field. During that time, I
`
`have worked for several different electronics companies including: Mostek, Texas Micro
`
`Engineering (acquired by Crystal Semiconductor), Crystal Semiconductor, Cirrus Logic, Cygnal
`
`Integrated Products, and Silicon Laboratories. I joined Silicon Laboratories when they acquired
`
`Cygnal, which I co-founded in 1999. I am a named inventor on 39 U.S. granted patents. I have
`
`held a variety of engineering positions throughout my career, including circuit designer, design
`
`manager, Director of Engineering, Chief Technical Officer, V.P. of Engineering, and V.P. of
`
`Technology. In addition to my engineering experience, I also have served as an adjunct faculty
`
`member at the University of Texas, where I taught CMOS analog and mixed-signal design for
`
`six years, and I have taught a number of short courses in Germany and Ireland.
`
`7.
`
`I earned the BSEE degree from Texas A&M University, the MSE and Ph.D.
`
`degrees from The University of Texas at Austin. A complete listing of my qualifications
`
`including a list of my patents is found in Ex. A.
`
`8.
`
`Upon graduation from Texas A&M, I went to work for Mostek Corporation
`
`designing integrated circuits for telecommunications applications. I designed an integrated
`
`DTMF tone generator which was my first patented invention. I also designed telephone ringer
`
`Declaration of Dr. Douglas Holberg – ‘614 Patent – Case No. 1:18-cv-00554-LY
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`circuits and two-to-four-wire converters for central-office applications. After leaving Mostek, I
`
`joined a startup company, Texas Micro Engineering, as its second employee where I designed,
`
`among other things, a dual-channel (atrium-ventricle) pacemaker sense amplifier/filter using
`
`discrete-time switched capacitor technology, co-designed a gate-array that was used to
`
`implement an insulin-pump controller, and a metronome. While enrolled in the Masters/Ph.D.
`
`program at The University of Texas at Austin, I worked on the application of bipolar technology
`
`to DRAM sense-amplifier architectures and circuit-simulation algorithms. I also designed and
`
`laid out the mask set (The Holberg Mask Set) used by the fabrication class/lab for many years.
`
`Upon graduating with a Ph.D., I went to work for Crystal Semiconductor/Cirrus Logic where I
`
`designed high frequency synthesizers for hard-disk read-channel applications. I managed a group
`
`designing CCD interface circuits for digital camera applications as well as television encoder
`
`chips and CMOS imagers. Upon leaving Cirrus, I started a company called Cygnal developing
`
`mixed-signal microcontrollers. I was a founder/CTO/VP Engineering, as well as an individual
`
`contributor. While at Cygnal, I designed A/D converters, Vbe temp sensors, I/O cells/pads
`
`(both design and layout) as well as many additional miscellaneous circuits. Cygnal was
`
`purchased by Silicon Labs where I remained employed as a manager of the microcontroller
`
`group, followed by the position, VP of Technology.
`
`9.
`
`In 2008 I began a consulting career in the area of patents and intellectual property.
`
`I have supported my clients in patent prosecution, licensing, and litigation in a variety of
`
`technologies, including analog/digital mixed signal circuits, RF circuits, oscillators, PLLs, A/D,
`
`D/A converters, switch-mode power supplies, motor drivers, and a variety of inventions from the
`
`circuit-level to system level. Based on my experience, both professional and educational, I
`
`believe I am more than qualified to give the opinions expressed herein.
`
`Declaration of Dr. Douglas Holberg – ‘614 Patent – Case No. 1:18-cv-00554-LY
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`10.
`
`I am the coauthor of the book “CMOS Analog Circuit Design” which was
`
`published in first edition in 1987. It is now in third edition and published in English and Chinese.
`
`It is a widely-used text throughout the world.
`
`IV.
`
`RELEVANT LEGAL PRINCIPLES AND GUIDELINES
`
`11.
`
`I am not an attorney and will not offer opinions on the law. I have been informed
`
`by counsel for AMD, however, of several principles concerning claim construction that I have
`
`used in arriving at my stated conclusions in this report.
`
`A.
`
`12.
`
`Claim Construction
`
`I understand that “claim construction” is the process of determining a patent
`
`claim’s meaning. I also understand that a claim construction analysis begins with the plain
`
`meaning of the claim term, which is the ordinary and customary meaning given to the term by
`
`those of ordinary skill in the art at the time of the invention.
`
`13.
`
`I have been informed and understand that there is a presumption that claim terms
`
`carry their accustomed meaning among persons of ordinary skill in the art. I have also been
`
`informed that the ordinary and customary meaning of a claim term may be determined by
`
`reviewing a variety of sources, including the claims themselves, the specification (or “written
`
`description”) of a patent, its prosecution history, and dictionaries and treatises.
`
`14.
`
`I have been informed and understand that the language of a patent claim must be
`
`interpreted in light of the patent’s claims, specification, and prosecution history, as well as other
`
`evidence extrinsic to the patent. More specifically, I understand that claim terms should be given
`
`their plain and ordinary meaning as understood by a person of ordinary skill in the art as of the
`
`effective filing date of the patent application (i.e., the day the application that led to the patent
`
`was filed), unless the claims, specification, or prosecution history indicate that a special meaning
`
`was intended.
`
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`15. More specifically, I understand that, for claim construction, one must focus on the
`
`claim terms in the context of the claim as a whole, interpreting the claim language as it ordinarily
`
`would be understood by a person skilled in the art at the time of the invention. I understand that
`
`the context of the surrounding words of the claim also must be considered in determining the
`
`ordinary and customary meaning of those terms.
`
`16.
`
`After the claim language, I understand that the most important sources to consider
`
`are the patent specification, including any publications incorporated by reference in the
`
`specification, and the prosecution history. I understand that, collectively, these sources (the claim
`
`language, specification, and prosecution history) are called “intrinsic evidence.”
`
`17. With respect to technical references and other information (called “extrinsic
`
`evidence”) that would have been available at the time when the patent’s application was filed, I
`
`understand that the law considers extrinsic evidence to be less reliable than intrinsic evidence,
`
`and that extrinsic evidence should not be used to change the ordinary meaning of the claim
`
`language.
`
`18.
`
`It is my understanding that a patentee may also act as his own lexicographer and
`
`provide definitions in the specification or prosecution history. For example, an inventor may
`
`clearly set forth a definition of the claim term in either the specification or prosecution history
`
`that is different from the term’s ordinary meaning. I understand that actions taken by the patent
`
`owner can affect the constructions of the claim terms. For instance, there may also be a clear
`
`disavowal of claim coverage in the specification or prosecution history.
`
`19.
`
`I understand that, if a patentee makes a clear and unambiguous disavowal of claim
`
`scope during prosecution, such a disclaimer informs the claim construction analysis by
`
`narrowing the ordinary and customary meaning of the claim consistent with the scope of the
`
`surrender. I further understand that such a disavowal of claim scope must be clear and
`
`unambiguous.
`
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`20.
`
`Unless otherwise noted, I have applied the plain meaning of the claim language
`
`for each of the claims discussed.
`
`21. My opinions of infringement are based on the information available to me as of
`
`the date of this expert report. In addition, however, I respectfully reserve the right to supplement
`
`this expert report as may be necessary or appropriate based on the discovery of additional
`
`information relevant to the opinions set forth herein, such as test results produced by
`
`Respondents.
`
`B.
`
`The Level of Ordinary Skill in the Art
`
`22. When interpreting a patent, I understand that it is important to view the disclosure
`
`and claims of that patent from the level of ordinary skill in the relevant art at the time of the
`
`invention. I understand that the ‘614 Patent was filed on April 1, 1999, claiming priority to a
`
`Japanese application which was filed January 14, 1999 (hereinafter, the “Filing Date”).
`
`23. My opinion of the level of ordinary skill in the art of the ‘614 patent is based on
`
`my personal experience working and lecturing in the fields of CMOS integrated-circuit
`
`technology, and analog/digital mixed-signal circuits, my knowledge of colleagues and others
`
`working in those fields as of and for several years prior to the applicable time frame applicable to
`
`each of those patents, my study of those patents and their file histories, and my knowledge of:
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`The level of education and experience of persons actively working in the above
`fields at the time the subject matter at issue was developed;
`
`The types of problems encountered in the art at the time the subject matter was
`developed;
`
`The rapidity with which innovations are made in those fields;
`
`Prior art patents and publications;
`
`The activities of others working in those fields;
`
`Prior art solutions to the problems addressed by the relevant art; and
`
`The sophistication of the technology at issue in this case.
`
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`24.
`
`I have also been informed that these factors are not exhaustive and are merely a
`
`useful guide to determining the level of ordinary skill in the art.
`
`25.
`
`Taking the above factors into account, and based upon my education and
`
`experience, I am familiar with the level of relevant knowledge about the technology at issue that
`
`one of ordinary skill in the art would have possessed.
`
`26.
`
`Based on the disclosure of the ‘614 patent, a person of ordinary skill in the art
`
`(“POSITA”) would have a B.S. degree in Electrical Engineering or an equivalent field as well as
`
`at least 3-5 years of academic or industry experience in semiconductor integrated circuit design,
`
`or comparable industry experience. A person with less education but more relevant practical
`
`experience may also meet this standard.
`
`27.
`
`Based on this description, I possessed at least ordinary skill in the art around the
`
`time of the Filing Date of the ‘614 patent. By that date, I had a Ph.D in Electrical Engineering
`
`and more than fifteen years of industry experience in semiconductor integrated circuit design,
`
`including designing a gate array platform for medical and consumer products and in managerial
`
`roles for telecommunications and imaging applications. See Ex. A (Curriculum Vitae). By 1999,
`
`I was also teaching graduate-level courses in CMOS Analog Circuit Design at University of
`
`Texas in Austin.
`
`28.
`
`For purposes of this declaration, I have taken the perspective of a person of
`
`ordinary skill as of the Filing Date.
`
`V.
`
`BACKGROUND OF THE ‘614 PATENT
`
`29.
`
`The ‘614 patent is directed to a semiconductor integrated circuit device including
`
`multi-threshold voltage MOS (MTCMOS) transistors, capable of operating at a low power
`
`supply voltage when in active mode and reducing power consumption resulting from a leakage
`
`current during standby mode. ‘614 patent at 1:8-12. The background section of the ‘614 patent
`
`explains that reducing power consumption in highly integrated semiconductor circuits “has
`
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`recently been recognized as an important problem.” Id. at 1:14-17. While “a reduction in the
`
`power supply voltage is a method most effective for low power consumption, . . . the reduction
`
`in the threshold voltage leads to an increase in leakage current of the MOS transistor during
`
`standby.” Id. at 1:15-26. Further, during active mode, “the reduction in the power supply voltage
`
`will cause a reduction in the operating speed of a MOS transistor.” Id. at 1:21-23. The ‘614
`
`patent explains that MTCMOS designs were a known solution to such problems related to
`
`reduced power supply. Id. at 1:26-32.
`
`30. MTCMOS circuits which use a standard cell have a couple of drawbacks. For
`
`example, “the period required to manufacture the MTCMOS becomes long” and in some cases
`
`where current is not sufficiently high during active mode, “a high-speed logical operation cannot
`
`be implemented.” Id. at 1:55-67. The ‘614 patent suggests implementation of a “layout of a
`
`semiconductor integrated circuit device by a gate array system, thereby shortening a manufacturing
`
`period thereof as compared with the conventional standard cell system.” Id. at 4-7.
`
`31.
`
`The purported invention of the ‘614 Patent is a semiconductor integrated circuit
`
`that uses a MTCMOS configuration, which combines both high-threshold MOS transistors and
`
`low-threshold MOS transistors. Id. at 1:26-2:13 (“….It is another object of the present invention
`
`to provide a semiconductor integrated circuit device capable of restraining variations in the
`
`values of voltages applied to a virtual power supply line and a virtual ground line and reducing a
`
`delay time when switching is done between logic circuits provided within an MTCMOS.”). The
`
`layout proposed by the ‘614 patent provides the MTCMOS circuit as a gate array (i.e., an array
`
`of unit cells), and also provides a power switch (comprised of high-threshold MOS transistors)
`
`located around the gate array (i.e., of unit cells). Id.
`
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`VI.
`
`CLAIM CONSTRUCTION
`
`32.
`
`I have considered each of the disputed claim terms and provide my opinions
`
`regarding claim construction below:
`
`A.
`
`“unit cells”
`
`Claim Term
`
`AMD’s Construction
`
`Plaintiff’s Construction
`
`“unit cells”
`(claim 1)
`
`semiconductor integrated circuits
`implemented by a gate array
`system, cannot be a conventional
`standard cell
`
`logic elements of which a unit cell array
`is comprised
`
`33.
`
`Claim 1 recites “a plurality of first unit cells each including a plurality of first
`
`MOS transistors” and “a plurality of second unit cells each including a plurality of second MOS
`
`transistors.” The claim language describes unit cells as including a plurality of first or second
`
`MOS transistor, with varying threshold voltages.
`
`34.
`
`The term “unit cells” is not a commonly used term in the art of semiconductor
`
`integrated circuit design. However, MOS transistors are the building block of all CMOS
`
`integrated circuits.
`
`35.
`
`The ‘614 patent distinguishes conventional standard cell MTCMOS from the
`
`claimed invention that uses “unit cell” MTCMOS. As I have explained in section V., the ‘614
`
`patent is directed to MTCMOS circuits which operate at a low power supply voltage when taken
`
`active and reduced power consumption due to leakage current during Standby. ‘614 patent, 1:8-
`
`12 (describing the field of the invention). The Background section of the specification explains
`
`that conventional MTCMOS circuits implemented a standard cell system “in which layout design
`
`is performed in units of a latch circuit such as a flip-flop circuit comprised of an inverter circuit,
`
`a master circuit and a slave circuit, and a logic circuit.” Id. at 1:52-55. The Background further
`
`notes that since the standard cell system is implemented by each circuit unit (e.g., a standard cell
`
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`is employed for each of the inverter circuit, master circuit, slave circuit, and logic circuit), “the
`
`period required to manufacture the MTCMOS becomes long.” Id. at 1:54-58. In the described
`
`“present invention,” the MTCMOS circuit is instead implemented “by a gate array system,
`
`thereby shortening a manufacturing period thereof as compared with the conventional standard
`
`cell system.” Id. at 2:3-7. The patent explains that “for achieving the” objective of having a
`
`MTCMOS gate array system, “unit cells each including PMOS transistors and NMOS
`
`transistors” are used in an array format instead of an arrangement of standard cells. Id. at 2:14-17
`
`(emphasis added). Accordingly, in my opinion, a POSITA reading the specification would
`
`understand that “unit cells” as recited in claim 1 are semiconductor integrated circuit elements
`
`implemented in a gate array system, and that they cannot be a conventional standard cell.
`
`36.
`
`A standard cell, in the context of digital circuits, is a circuit (both schematic and
`
`layout) that implements a logical function containing MOS transistors of varying dimensions
`
`(widths and lengths) and necessary metal interconnects to achieve a particular logical function.
`
`Thus, a standard cell is fully defined from the silicon substrate through the top-most metal layer
`
`prior to its inclusion into a larger logical macro-function in an integrated circuit design.
`
`Designing a PCB (printed circuit board) using standard MSI/LSI circuits (e.g., 74 Series TTL
`
`chips) is analogous to designing a circuit using a standard-cell methodology.
`
`37.
`
`A gate array is an array of MOS transistor gates (and their associated drains and
`
`sources) which have no pre-assigned logical function. Generally, all transistor gates of a single
`
`conductivity type (PMOS or NMOS) in a gate array are identical in size (gate width and length).
`
`Thus, a POSITA would know that all PMOS transistor gates would have the same dimensions,
`
`and all of the NMOS transistor gates would have the same dimensions. In order for them to have
`
`roughly equivalent drive capability, NMOS transistor gates would be about half the width of the
`
`PMOS transistor gates (due to the difference in the mobility of holes and electrons). A gate array
`
`has no logical function until the last step of the physical design process, where gates, drains, and
`
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`sources of PMOS and NMOS transistors in the array are connected to achieve a desired larger
`
`logical macro-function. These connections are made using metal, contacts, and vias. Designing a
`
`PCB using only discrete transistors is analogous to gate-array design methodology.
`
`38.
`
`Extrinsic evidence describing the knowledge of a POSITA supports the
`
`distinction between the conventional standard cell and a gate array. For example, Principles of
`
`CMOS VLSI Design (2d ed. 1993) explains that gate array structures allow for an efficient way to
`
`manufacture customized integrated circuits. Gate array structures “contain a continuous array of
`
`n- and p- transistors.” Customization at a low cost is possible “by using design-specific
`
`metalization and contacts,” and “processing time is kept to a minimum because only the top
`
`metalization steps need be run.” Weste, Neil H. E. et al., Principles of CMOS VLSI Design (2d
`
`ed. 1993) at 407-408. In contrast, standard cells are “[p]redefined circuit elements that may be
`
`selected and arranged to create a custom or semicustom integrated circuit.” Graf, R.F., Modern
`
`Dictionary of Electronics (7th ed. 1999) at 729. Moreover, unlike gate arrays, “[s]tandard cells
`
`are usually designed to be of constant height and variable width with interconnection points
`
`located along the bottom and possibly the top of the cell.” Laplante, P.A., Comprehensive
`
`Dictionary of Electrical Engineering (CRC Press 1999) at 606.
`
`39.
`
`Therefore, the ‘614 patent explains that the claimed invention is implemented by
`
`a gate array system in order to reduce manufacturing time and, as a POSITA would understand,
`
`that gate arrays and standard cells are two distinct ways of designing and fabricating
`
`semiconductor circuits.
`
`40.
`
`It is my opinion that Plaintiff’s construction of unit cells, “logic elements of
`
`which a unit cell array is comprised” fails to provide clarity to the term, is inaccurate, and fails to
`
`account for the specification’s distinction between unit cells and standard cells. Plaintiff’s
`
`proposed construction does not clarify what unit cells refers to, as it is unclear what is meant by
`
`“logic elements.” The term is not used in the specification or the claims. In general, logic
`
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`elements can mean a logic gate, such as AND, OR, XOR, NOT, NAND gates and other logic
`
`blocks. The specification does describe “logic circuits” and refers to them in Fig. 3 as numeral
`
`20, which identifies an example NAND gate and a NOR gate. ‘614 patent at 3:29-31. These logic
`
`circuits 20 in Fig. 3 are described as distinct from a latch circuit 19. Id. at 3:23-35. However, the
`
`specification explicitly indicates that both these logic circuits and latch circuits comprise
`
`transistors within unit cells:
`
`A latch circuit 19 directly connected between a power supply line 11 and a ground
`line 12 comprises the MOS transistors 23 each having the high threshold
`voltage, lying within each unit cell 3. . . . On the other hand, a set or
`arrangement of various logic circuits 20 electrically connected between a virtual
`power supply line 13 and a virtual ground line 14 is comprised of the MOS
`transistors 24 each having the low threshold voltage, lying within each unit
`cell 2.
`
`Id. at 3:23-33 (emphasis added). Here the inventor describes “logic circuits” comprising “MOS
`
`transistors . . . within each unit cell 2.” Thus, a POSITA reading this portion of the specification
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`would distinguish between a logic function and a “unit cell.” Semiconductors implemented by a
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`gate array system are also distinct from a logic function, because they do not have a logical
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`function until later when the final wiring is added to the system. Prior to wiring being added,
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`gate arrays are merely a group of floating, unconnected transistors, without logical function (e.g.,
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`unable to perform the functions of a logic gate, such as the AND, OR, XOR, etc., gates I describe
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`above). Gate arrays are thus advantageous, because they can shorten a manufacturing period.
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`This is possible because the gate array can be initially manufactured up to just prior to wire
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`processing and held at that stage indefinitely. When a new logic function is desired, interconnect
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`can be defined and implemented on the staged arrays. Thus the time between providing a logic
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`definition and a manufactured logic function is just the time required for wire processing—which
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`is relatively short.
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`41.
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`The specification also describes the fact that a preferred embodiment has a unit
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`cell that, when wired, lacks a logic function:
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`Declaration of Dr. Douglas Holberg – ‘614 Patent – Case No. 1:18-cv-00554-LY
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`Page 14 of 29
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`0014
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`A unit cell 51 is one which is not used for a circuit configuration of
`MTCMOS upon wire processing of MTCMOS. The unit cell 51 comprises two
`PMOS transistors 53 each comprised of an N well 59, P-type diffused layers 56,
`57 and 58, and gate electrodes 54 and 55 all of which are formed on a substrate
`52, and two NMOS transistors 63 each comprised of a Pwell 69, N-type diffused
`layers 66, 67 and 68, and-gate electrodes 64 and 65 all of which are formed on the
`substrate 52.
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`‘614 Patent at 4:43-51 (emphasis added). Thus, like a gate array system, the “unit cell” described
`
`in the specification is a physical layout of a group of PMOS and NMOS transistors which have
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`no inherent logical function, until they undergo “wire processing.” Indeed, the specification
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`further describes connecting the PMOS and NMOS transistors of the unit cell 51 to form
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`capacitors. Id. at 4:39-41, 4:51-55, Fig. 5. If a “unit cell” can be used to form capacitors, it
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`cannot be understood to be a “logic function.” A POSITA would know that logic functions are
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`not capacitors.
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`42.
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`Construing the unit cells to be “logic elements” or “logic circuits” ignores the
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`“present invention” described in the specification to achieve an MT-CMOS implemented by a
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`gate array system. The Plaintiff’s construction also ignores the repeated distinctions in the
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`specification made between unit cells and fully defined logic functions, which are implemented
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`by standard cell “logic circuits.” Id. at 3:23-35, 4:30-37. The gate array system, in contrast,
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`allows for manufacture of larger logic functions beyond just the basic logic gates, such as the
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`latch circuit 19. Since the specification explicitly describes the latch circuit as part of a unit cell,
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`Plaintiff’s construction that unit cells are generic “logic elements” ignores the teachings in the
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`‘614 patent.
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`43.
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`Further, the extrinsic evidence cited by Plaintiff, a paper titled “Performance
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`Simulation and Analysis of a CMOS/Nano Hybrid Nanoprocessor System,” also does not
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`support what Plaintiff argues the term means in the context of the ‘614 patent. I note that the
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`paper was published in 2009, well after the filing date of the ‘614 patent, and relates to “Hybrid
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`micro-nano electronics systems” that combines CMOS technology with nano-electronics for
`
`Declaration of Dr. Douglas Holberg – ‘614 Patent – Case No. 1:18-cv-00554-LY
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`Page 15 of 29
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`“ultra-dense” integrated circuits. Cabe, A. and Das, S., Performance Simulation and Analysis of
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`a CMOS/Nano Hybrid Nanoprocessor System, Nanotechnology, vol. 20, no. 16, 22 (Apr. 2009)
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`at 2. Although the paper states that “Each hypercell consists of a small number of unit cells,
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`where a single unit cell corresponds to the smallest logic element, typically a buffer or inverter,”
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`hypercells are not relevant MTCMOS circuits or low power semiconductor circuits. The paper’s
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`use of the term “unit cell” in hypercells is unrelated to the application described in the ‘614
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`patent, e.g., semiconductor integrated circuits, particularly for MTCMOS circuits. “Unit cell” is
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`not a term of art; otherwise, it would be ubiquitous in the literature, and it is not. The appearance
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`of the term in a paper published in 2009 describing different technology than what is described in
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`the ‘614 patent fails to support or illustrate what a POSITA would have known at the time of the
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`filing of the application that became the ‘614 patent.
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`44.
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`Accordingly, a POSITA would have understood that the term “unit cells”
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`describes the basic cell used in a semiconductor integrated circuit gate array system that cannot
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`be conventional standard cells.
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`B.
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`“a unit cell array comprised of first and second unit cells laid in array form”
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`Claim Term
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`AMD’s Construction
`
`Plaintiff’s Construction
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`a plurality of said first and second
`unit cells laid in a regular
`arrangement or pattern
`
`An arrangement of first and second unit
`cells, not ne