`
`
`(19) Japan Patent Office (JP)
`
`(12) Japanese Unexamined Patent
`Application Publication (A)
`
`
`
`
`(11) Japanese Unexamined Patent
`Application Publication Number
`H10-125878
`(43) Publication date May 5, 1998
`
`
`(51) Int. Cl.6
`
` H01L 27/118
` 21/8238
` 27/092
`
`
`Identification codes
`
`Technical indications
` FI
` H01L 21/82 M
` 27/08 321 J
`
`Request for examination: Not yet requested: Number of claims: 31 Floppy disk (Total of 24 pages)
`
`(21) Application number
`(22) Date of application
`
`
`H8-297099
`November 21, 1996
`
`
`(71) Applicant
`
`(72) Inventor
`
`
`
`
`
`(74) Agent
`
`NIPPON TELEGRAPH AND TELEPHONE CORPORATION
`19-2-3 NISHI-SHINJUKU, SHINJUKU-KU, TOKYO
`URANO, MASAMI
`℅ NIPPON TELEGRAPH AND TELEPHONE
`CORPORATION
`19-2-3 NISHI-SHINJUKU, SHINJUKU-KU, TOKYO
`Patent attorney NAGAO, TSUNEAKI
`
`
`
`(54) [TITLE OF THE INVENTION]
`Gate Array
`(57) [ABSTRACT]
`[PROBLEM]
`To provide a gate array that includes MT-CMOS
`circuits, to achieve low voltage, high-speed operation.
`[MEANS FOR RESOLUTION]
`A first basic cell 31 is used wherein two low threshold
`value p-channel MOS transistors Q1 and Q2, which are
`provided in the horizontal direction, and two low threshold
`value n-channel MOS transistors Q3 and Q4, which are
`provided in the horizontal direction, are arranged in the
`vertical direction, wherein high threshold value p-channel
`MOS transistors Q5 and Q6 are arranged adjacently above
`the MOS transistors Q1 and Q2, and high threshold value
`n-channel MOS transistors Q7 and Q8 are arranged
`adjacently below the MOS transistors Q3 and Q4.
`
`
`
`
`
`
`AMD EX1008
`U.S. Patent No. 6,239,614
`
`0001
`
`

`

`[PATENT CLAIMS]
`[CLAIM 1]
`A gate array wherein a low threshold value transistor
`group is formed through arranging, in the vertical direction,
`a plurality of
`low
`threshold value p-channel MOS
`transistors that are provided in the horizontal direction and
`a plurality of
`low
`threshold value n-channel MOS
`transistors that are provided in the horizontal direction,
`wherein:
`a plurality of high threshold value p-channel MOS
`transistors, provided in the horizontal direction, is arranged
`adjacently above the low threshold value transistor group,
`and a plurality of high threshold value n-channel MOS
`transistors, provided in the horizontal direction, is arranged
`adjacent below the low threshold value transistor group, to
`structure a first basic cell, and this first basic cell is used as
`a structural element.
`[CLAIM 2]
`A gate array as set forth in Claim 2, wherein:
`an aforementioned high threshold value n-channel MOS
`transistor is omitted.
`[CLAIM 3]
`A gate array as set forth in Claim 1, wherein:
`an aforementioned high threshold value p-channel MOS
`transistor is omitted.
`[CLAIM 4]
`A gate array as set forth in Claim 1 through Claim 3,
`wherein:
`the channel width of an aforementioned high threshold
`value p-channel MOS transistor [and/or] an aforementioned
`high threshold value n-channel MOS transistor is less than
`that of an MOS transistor of the low threshold value
`transistor group.
`[CLAIM 5]
`A gate array wherein a low threshold value transistor
`group is formed through arranging, in the vertical direction,
`a plurality of
`low
`threshold value p-channel MOS
`transistors that are provided in the horizontal direction and
`a plurality of
`low
`threshold value n-channel MOS
`transistors that are provided in the horizontal direction,
`wherein:
`a high threshold value p-channel MOS transistor and a
`low threshold value p-channel MOS transistor, provided in
`the horizontal direction, are arranged adjacently above the
`low threshold value transistor group in a common diffusion
`region, and a high threshold value n-channel MOS
`transistor and a low threshold value n-channel MOS
`transistor, provided in the horizontal direction, are arranged
`adjacently below the low threshold value transistor group,
`to structure a second basic cell, and this second basic cell is
`used as a structural element.
`[CLAIM 6]
`A gate array as set forth in Claim 5, wherein:
`a high threshold value n-channel MOS transistor and a
`low threshold value n-channel MOS transistor provided in
`the horizontal direction in the common diffusion region are
`omitted.
`[CLAIM 7]
`A gate array as set forth in Claim 5, wherein:
`a high threshold value p-channel MOS transistor and a
`low threshold value p-channel MOS transistor provided in
`
`Japanese Unexamined Patent Application Publication H10-125878
`(2)
`
`
`the horizontal direction in the common diffusion region are
`omitted.
`[CLAIM 8]
`A gate array as set forth in Claims 5 through 7, wherein:
`a channel width of a high threshold value n-channel
`MOS transistor and a low threshold value n-channel MOS
`transistor, provided in the horizontal direction in the
`common diffusion region, and a channel width of a high
`threshold value p-channel MOS transistor and a low
`threshold value p-channel MOS transistor, provided in the
`horizontal direction in the common diffusion region, are
`less than that of an MOS transistor of the low threshold
`value transistor group.
`[CLAIM 9]
`A gate array, comprising: a first basic cell as set forth in
`Claim 1 through 4 and a second basic cell as set forth in
`Claim 5 through 8, wherein the first basic cells and the
`second basic cells are arranged as an array so that the
`second basic cells are arranged with periodicity.
`[CLAIM 10]
`A gate array wherein a low threshold value transistor
`group is formed through arranging, in the vertical direction,
`a plurality of
`low
`threshold value p-channel MOS
`transistors that are provided in the horizontal direction and
`a plurality of
`low
`threshold value n-channel MOS
`transistors that are provided in the horizontal direction,
`wherein a plurality of low threshold value p-channel MOS
`transistors, provided in the horizontal direction, is arranged
`adjacently above the low threshold value transistor group,
`and a plurality of low threshold value n-channel MOS
`transistors, provided in the horizontal direction, is arranged
`adjacently below the low threshold value transistor group,
`to structure a fourth basic cell; and
`the fourth basic cell and first basic cell as set forth in
`Claim 1 through 4, wherein the first basic cells and the
`fourth basic cells are arranged as an array so that the fourth
`basic cells are arranged with periodicity therein.
`[CLAIM 11]
`A gate array wherein:
`a plurality of high threshold value p-channel MOS
`transistors provided in the horizontal direction and a
`plurality of high
`threshold value n-channel MOS
`transistors, provided
`in
`the horizontal direction, are
`arranged in the vertical direction to structure a third basic
`cell;
`the aforementioned third basic cell is arranged at one or
`both of ends in the direction in which the first and second
`basic cells set forth in Claim 9 are arranged; or
`the third basic cell is arranged at one or both ends in the
`direction in which the first and fourth basic cells set forth in
`Claim 10 are arranged, described, or at one or both ends in
`the direction perpendicular to the arrangement direction.
`[CLAIM 12]
`A gate array as set forth in Claim 11, wherein:
`a low threshold value input/output buffer cell, structured
`from a low threshold value MOS transistor, is arranged in a
`peripheral region.
`[CLAIM 13]
`A gate array as set forth in Claim 11, wherein:
`a low threshold value input/output buffer cell, structured
`from an MOS transistor with a low threshold value, and a
`high threshold value input/output buffer cell, structured
`
`
`
`
`0002
`
`

`

`from an MOS transistor with a high threshold value, are
`disposed in a peripheral region.
`[CLAIM 14]
`A gate array as set forth in Claim 11, wherein:
`a high/low threshold value mixed input/output buffer
`cell, structured from a low threshold value MOS transistor
`and a high threshold value MOS transistor, is arranged in a
`peripheral region.
`[CLAIM 15]
`A gate array as set forth in Claim 1, 4, 5, 8, or 9 through
`14, wherein:
`a high voltage level side actual power supply line, a low
`voltage level side actual power supply line, a high voltage
`level side virtual power supply line, and a low voltage level
`side virtual power supply line are provided;
`a high voltage level side power supply controlling
`circuit, comprising a high threshold value p-channel MOS
`transistor of a first or second basic cell, is structured
`between the high voltage level side actual power supply
`line and the high voltage level side virtual power supply
`line;
`a low voltage level side power supply controlling circuit
`comprising a high
`threshold value n-channel MOS
`transistor of a first or second basic cell is structured
`between the low voltage level side actual power supply line
`and the low voltage level side virtual power supply line.
`[CLAIM 16]
`A gate array as set forth in Claim 15, wherein:
`the high voltage level side power supply controlling
`circuit is structured through connecting the source of the
`high threshold value p-channel MOS transistor to the high
`voltage level side actual power supply line, connecting the
`drain thereof to the high voltage level side virtual power
`supply line, and connecting the gate thereof to a first
`control terminal; and
`the low voltage level side power supply controlling
`circuit is structured through connecting the source of the
`high threshold value n-channel MOS transistor to the low
`voltage level side actual power supply line, connecting the
`drain thereof to the low voltage level side virtual power
`supply line, and connecting the gate thereof to a second
`control terminal.
`[CLAIM 17]
`A gate array as set forth in Claim 2, 4, 6, 8, or 9 through
`14, wherein:
`a high voltage level side actual power supply line, a low
`voltage level side actual power supply line, and a high
`voltage level side virtual power supply line are provided;
`and
`a high voltage level side power supply controlling
`circuit, comprising a high threshold value p-channel MOS
`transistor of a first or second basic cell, is structured
`between the high voltage level side actual power supply
`line and the high voltage level side virtual power supply
`line.
`[CLAIM 18]
`A gate array as set forth in Claim 17, wherein:
`the high voltage level side power supply controlling
`circuit is structured through connecting the source of the
`high threshold value p-channel MOS transistor to the high
`voltage level side actual power supply line, connecting the
`drain thereof to the high voltage level side virtual power
`
`Japanese Unexamined Patent Application Publication H10-125878
`(3)
`
`
`supply line, and connecting the gate thereof to a first
`control terminal.
`[CLAIM 19]
`A gate array as set forth in Claim 3, 4, 7, 8, or 9 through
`14, wherein:
`a high voltage level side actual power supply line, a low
`voltage level side actual power supply line, and a low
`voltage level side virtual power supply line are provided;
`and
`a low voltage level side power supply controlling circuit
`comprising a high
`threshold value n-channel MOS
`transistor of a first or second basic cell is structured
`between the low voltage level side actual power supply line
`and the low voltage level side virtual power supply line.
`[CLAIM 20]
`A gate array as set forth in Claim 19, wherein:
`the low voltage level side power supply controlling
`circuit is structured through connecting the source of the
`high threshold value n-channel MOS transistor to the low
`voltage level side actual power supply line, connecting the
`drain thereof to the low voltage level side virtual power
`supply line, and connecting the gate thereof to a control
`terminal.
`[CLAIM 21]
`A gate array as set forth in Claim 1 through 14, wherein:
`a high voltage level side actual power supply line and a
`low voltage level side actual power supply line are
`provided, and also a high voltage level side virtual power
`supply line and/or a low voltage level side virtual power
`supply line is provided, and a low threshold value logic
`gate is structured in the low threshold value transistor
`group;
`a high voltage level side power supply terminal of the
`low threshold value logic gate is connected to a high
`voltage level side virtual power supply line, and a low
`voltage level side power supply terminal is connected to the
`low voltage level side virtual power supply line, or a high
`voltage level side power supply terminal is connected to a
`high voltage level side actual power supply line and a low
`voltage level side power supply terminal is connected to a
`low voltage level side virtual power supply line, or a high
`voltage level side power supply terminal is connected to a
`high voltage level side virtual power supply line and a low
`voltage level power supply line is connected to a low
`voltage level actual power supply line.
`[CLAIM 22]
`A gate array as set forth in Claim 1, 4, 5, 8, or 9 through
`14, wherein:
`a high voltage level side actual power supply line, a low
`voltage level side actual power supply line, a high voltage
`level side virtual power supply line, and a low voltage level
`side virtual power supply line are provided;
`and a high threshold value logic gate is structured from
`the first or second basic cell high threshold value p-channel
`MOS transistor and high threshold value n-channel MOS
`transistor; and
`high voltage level side power supply terminal of the high
`threshold value logic gate is connected to the high voltage
`level side virtual power supply line, and the low voltage
`level side power supply terminal thereof is connected to the
`low voltage level side virtual power supply line.
`[CLAIM 23]
`
`
`
`
`0003
`
`

`

`A gate array as set forth in Claim 1, 4, 5, 8, or 9 through
`14, wherein:
`a high voltage level side actual power supply line and a
`low voltage level side actual power supply line are
`provided;
`and a high threshold value logic gate is structured from
`the first or second basic cell high threshold value p-channel
`MOS transistor and high threshold value n-channel MOS
`transistor; and
`high voltage level side power supply terminal of the high
`threshold value logic gate is connected to the high voltage
`level side actual power supply line, and the low voltage
`level side power supply terminal thereof is connected to the
`low voltage level side actual power supply line.
`[CLAIM 24]
`A gate array as set forth in Claim 11 through 14,
`wherein:
`a high voltage level side actual power supply line and a
`low voltage level side actual power supply line are
`provided;
`and a high threshold value logic gate is structured from
`the third basic cell high threshold value p-channel MOS
`transistor and high
`threshold value n-channel MOS
`transistor; and
`high voltage level side power supply terminal of the high
`threshold value logic gate is connected to the high voltage
`level side actual power supply line, and the low voltage
`level side power supply terminal thereof is connected to the
`low voltage level side actual power supply line.
`[CLAIM 25]
`A gate array wherein a high voltage level side power
`supply controlling circuit as set forth in Claim 15 through
`18 or a low voltage level side power supply controlling
`circuit as set forth in Claim 15, 16, 19, or 20 is connected to
`an output terminal of a high threshold value logic gate as
`set forth in Claim 23.
`[CLAIM 26]
`A gate array wherein a high voltage level side power
`supply controlling circuit as set forth in Claim 15 through
`18 or a low voltage level side power supply controlling
`circuit as set forth in Claim 15, 16, 19, or 20 is connected to
`an output terminal of a high threshold value logic gate as
`set forth in Claim 24.
`[CLAIM 27]
`A gate array wherein:
`a high voltage level side actual power supply line, a low
`voltage level side actual power supply line, a high voltage
`level side virtual power supply line, and/or a low voltage
`level side virtual power supply line are provided;
`a low threshold value input buffer or output buffer is
`structured from a low threshold value MOS transistor in a
`low threshold value input/output buffer cell as set forth in
`Claim 12;
`a high voltage level side power supply terminal of the
`low threshold value input buffer or output buffer is
`connected to a high voltage level side virtual power supply
`line, and a low voltage level side power supply terminal is
`connected to the low voltage level side virtual power
`supply line, or a high voltage level side power supply
`terminal is connected to a high voltage level side actual
`power supply line and a low voltage level side power
`supply terminal is connected to a low voltage level side
`
`Japanese Unexamined Patent Application Publication H10-125878
`(4)
`
`
`virtual power supply line, or a high voltage level side
`power supply terminal is connected to a high voltage level
`side virtual power supply line and a low voltage level
`power supply line is connected to a low voltage level
`actual power supply line.
`[CLAIM 28]
`A gate array wherein:
`a high voltage level side actual power supply line, a low
`voltage level side actual power supply line, a high voltage
`level side virtual power supply line, and/or a low voltage
`level side virtual power supply line are provided;
`a low threshold value input buffer or output buffer is
`structured from a low threshold value MOS transistor in a
`low threshold value input/output buffer cell as set forth in
`Claim 13;
`a high voltage level side power supply terminal of the
`low threshold value input buffer or output buffer is
`connected to a high voltage level side virtual power supply
`line, and a low voltage level side power supply terminal is
`connected to the low voltage level side virtual power
`supply line, or a high voltage level side power supply
`terminal is connected to a high voltage level side actual
`power supply line and a low voltage level side power
`supply terminal is connected to a low voltage level side
`virtual power supply line, or a high voltage level side
`power supply terminal is connected to a high voltage level
`side virtual power supply line and a low voltage level
`power supply line is connected to a low voltage level
`actual power supply line;
`a high threshold value input buffer or output buffer is
`structured from a high threshold value MOS transistor in a
`high threshold value input/output buffer cell set forth in
`Claim 13; and
`a high voltage level side power supply terminal of the
`high threshold value input buffer or output buffer is
`connected to the high voltage level side actual power
`supply line and a low voltage level side power supply
`terminal is connected to the low voltage level side actual
`power supply line.
`[CLAIM 29]
`A gate array wherein:
`a low threshold value input buffer or output buffer and a
`high threshold value input buffer or output buffer is
`structured by
`the high/low
`threshold value mixed
`input/output buffer cell set forth in Claim 14;
`a high voltage level side power supply terminal of the
`low threshold value input buffer or output buffer is
`connected to a high voltage level side virtual power supply
`line, and a low voltage level side power supply terminal is
`connected to the low voltage level side virtual power
`supply line, or a high voltage level side power supply
`terminal is connected to a high voltage level side actual
`power supply line and a low voltage level side power
`supply terminal is connected to a low voltage level side
`virtual power supply line, or a high voltage level side
`power supply terminal is connected to a high voltage level
`side virtual power supply line and a low voltage level
`power supply line is connected to a low voltage level
`actual power supply line; and
`a high voltage level side power supply terminal of the
`high threshold value input buffer or output buffer is
`connected to the high voltage level side actual power
`
`
`
`
`0004
`
`

`

`supply line and a low voltage level side power supply
`terminal is connected to the low voltage level side actual
`power supply line.
`[CLAIM 30]
`A gate array as set forth in Claim 15, 16, 25, or 26,
`wherein:
`a signal that is applied from the outside of an IC chip, as
`a control signal, is relayed through a high threshold value
`input buffer as set forth in Claim 28 or 29.
`[CLAIM 31]
`A gate array wherein, in Claim 30, the signal that is
`applied from outside of the IC chip as a control signal is a
`control signal of a high voltage level side power supply
`controlling circuit [and/or] a low voltage level side power
`supply controlling circuit of the gate array set forth in
`Claim 15, 16, 25, or 26.
`[DETAILED EXPLANATION OF THE INVENTION]
`[0001]
`[FIELD OF TECHNOLOGY OF THE PRESENT INVENTION]
`The present invention relates to a gate array, wherein an
`array of cells, called "basic cells," structured from several
`transistors or several tens of transistors, are arranged on a
`chip as an array, and the transistors within the basic cells
`are connected
`through
`interconnections
`to enable
`achievement of desired logic functions.
`[0002]
`[PRIOR ART]
`FIG. 35 (a) is a diagram depicting an example of a basic
`cell in a conventional gate array, and (b) is a circuit
`diagram
`thereof. M1 and M2 are p-channel MOS
`transistors, and M3 and M4 are n-channel MOS transistors.
`Moreover, 1 is a p-type diffusion region, 2 is an n-type
`diffusion region, 3 is polysilicon that functions as a gate, or
`the like, and 4 is an n well. Logic gates are structured using
`the transistors M1 through M4. FIG. 36 (a) is a diagram
`depicting a two-input NAND gate, structured using the
`basic cells shown in FIG. 35, and (b) is a circuit diagram
`thereof. The interconnections are performed through a
`single-layer metal interconnection 5. 6 is a contact hole,
`VDD is an actual power supply line, GND is an actual
`ground line, A1 and A2 are input ports, and Y is an output
`port. Normally the p-channel MOS transistors M1 and M2
`have mutually identical gate widths and threshold values,
`and, likewise, the n-channel MOS transistors M3 and M4
`have mutually identical gate widths and threshold values.
`[0003]
`FIG. 37 (a) is a diagram depicting an example of a basic
`cell in another conventional gate array, and (b) is a circuit
`diagram thereof, a basic cell for the gate cell depicted in
`FIG. 1 of Japanese Patent Application H4-72854, by the
`same applicant as in the present application. Here p-
`channel MOS transistors M9 and M10 are provided on the
`same side as p-channel MOS transistors M1 and M2 of the
`gate cell depicted in FIG. 35, and n-channel MOS
`transistors M5 through M8 are provided on the same side as
`n-channel MOS transistors M3 and M4. In this basic cell, a
`logic gate is structured from the transistors M1 through M4,
`and memory cells are structured from the transistors M9,
`M10, and M3 through M8.
`[0004]
`FIG. 38 depicts an example of a two-input NAND gate
`structured using the basic cell of FIG. 37, but the transistors
`
`Japanese Unexamined Patent Application Publication H10-125878
`(5)
`
`
`M5 through M10 are not used. Thus the circuit diagram is
`identical to that shown in FIG. 36 (b), described above.
`[0005]
`FIG. 39 (a) is a diagram depicting a two-port memory
`cell structured using the basic cell of FIG. 37, and (b) is a
`circuit diagram
`thereof. 7
`is a
`two-layer metal
`interconnection, 8 is a through hole, BL1 and BL2 are bit
`lines, BL1N and BL2N are inverted bit lines of these bit
`lines BL1 and BL2, and WL1 and WL2 are word lines. In
`this example, the sources and drains of transistors M1 and
`M2 are tied to the power supply, and not used in structuring
`a circuit. In this conventional example, the gate widths of
`the transistors in the basic cell can be set to various sizes in
`order to structure the circuit optimally, but the threshold
`value is set to identical values for the p-channel and n-
`channel MOS transistors.
`[0006]
`In this way, in the gate array, logic circuits are structured
`using cells known as basic cells, so that identical wafers
`that have been completed up through the processes for
`manufacturing the transistors can be used in a variety of
`ICs, enabling ICs with desired logic to be achieved through
`customizing
`the
`interconnection processes
`for
`the
`individual ICs.
`[0007]
`With normal cell-based ICs, after logical design is
`completed,
`time
`is required for
`the front-end and
`interconnection processes, but with gate arrays, the front-
`and processing can move forward regardless of the type of
`IC product. Consequently, this has a distinct benefit in that
`if the transistor manufacturing process has been completed
`by the time that the logic design has been completed, then
`the time required for IC processing is only for the back-end
`processes, making it possible to shorten the development
`lead time when compared to ICs such as cell-based ICs.
`[0008]
`Note that in recent years there has been a reduction in
`power used in ICs, in response to the need to make various
`types of electronic devices mobile, and, at this time, that
`which is most effective is reducing the power supply
`voltage. However, when the voltage of the power supplied
`to ICs that use transistors that are designed for the
`conventional power supply voltage is reduced, there are
`problems in that this greatly increases delay times, and
`processing variability has a large effect.
`[0009]
`In order to prevent a reduction in operating speed and to
`reduce the effect of processing variability despite a
`reduction in the power supply voltage, one method is to
`reduce the threshold voltages of the transistors. However,
`typically when the threshold voltage of transistors is
`reduced, the leakage current wherein the transistor is OFF
`will be larger, which is a problem in that, in applications
`such as mobile devices, and the like, in particular, this
`reduces the battery life.
`[0010]
`One technology by which to solve this problem is shown
`in FIG. 40, as an example of an MT-CMOS (Multi-
`Threshold CMOS) circuit, shown in The Institute of
`Electronics, Information and Communication Engineers,
`1994 Nationwide Conference Proceedings, Volume Five,
`Page 5-195. In this FIG. 40, M11 and M12 are low
`
`
`
`
`0005
`
`

`

`threshold value p-channel MOS transistors, M13 and M14
`are low threshold value n-channel MOS transistors, M15 is
`a high threshold value p-channel MOS transistor, and M16
`is a high threshold value n-channel MOS transistor. The
`logic circuit 9 (the two-input NAND gate in the example in
`the figure) is structured from the low threshold value
`transistors M11 through M14.
`[0011]
`The power supply of the logic circuit 9 is connected to a
`virtual power supply line VDDV, and the ground is
`connected to a virtual ground line GNDV. The actual
`power supply line VDD and the virtual power supply line
`VDDV, respectively, are connected to the source and drain
`of the high threshold value p-channel MOS transistor M15,
`and a sleep control signal SL is connected to the gate.
`Moreover, the actual ground line GND and the virtual
`ground line GNDV, respectively, are connected to the
`source and drain of the high threshold value n-channel
`MOS transistor M16, and an inverted signal SLN of the
`sleep control signal SL are connected to the gate.
`[0012]
`During operation, the sleep control signal SL is at a low
`level. Through this, the high threshold value MOS
`transistors M15 and M16 are turned ON, and the virtual
`power supply line VDDV and virtual ground line GNDV
`respectively, go to essentially the same electropotential as
`the actual power supply line VDD and the actual ground
`line GND. In this case, the logic circuit 9 is structured from
`the low threshold value voltage transistors M11 through
`M14, and thus is able to operate at high speeds despite the
`low voltage.
`[0013]
`Moreover, during sleep (when in standby), the sleep
`control signal is put to a high level, causing the high
`threshold value transistors M15 and M16 to turn OFF.
`Through this, the leakage path between the actual power
`supply line VDD and the actual ground line GNDV is cut
`off by the high threshold value transistors M15 and M16
`that are in the OFF state, making it possible to reduce the
`leakage current. Note that the circuit in FIG. 40 may be
`structured without the high threshold value n-channel MOS
`transistor M16, or, as shown in FIG. 41 (b), may be
`structured without the high threshold value p-channel MOS
`transistor M15.
`[0014]
`As described above, the MT-CMOS as a circuit structure
`wherein it is possible to achieve simultaneously high-speed
`logic operation, through the low threshold value MOS
`transistors, and a reduction in leakage current, through the
`high threshold value transistors, despite the power supply
`voltage being at a low voltage range.
`[0015]
`Moreover, the method described in the document cited
`above, as a technique for layout using actual standard cells,
`is shown in FIG. 42. Power supply cells 10, which each
`includes a high threshold value p-channel MOS transistor
`M15 and an n-channel MOS transistor M16, are arranged
`on both the left and right ends of a row of cells, between
`which logic circuits cells 11 and 12, which are structured
`from low threshold value transistors, are arranged, where
`the sources and drains of the high threshold value pMOS
`transistors M15, in the power supply cells 10, are
`
`Japanese Unexamined Patent Application Publication H10-125878
`(6)
`
`
`connected, respectively, to the actual power supply line
`VDD and the virtual power supply line VDDV, and the
`source and drain of the high threshold value n-channel
`MOS transistors M16 are connected, respectively, to the
`actual ground line GND and the virtual ground line GNDV.
`The MOS transistors in the logic cells 11 and 12 are
`supplied power through the virtual power supply line
`VDDV and the virtual ground line GNDV.
`[0016]
`Note that when the IC is structured from such MT-
`CMOS circuits, a problem occurs wherein data that is
`stored in an FF (flip-flop) becomes corrupted during sleep.
`One method for solving this problem is a circuit known as a
`"balloon DFF," shown in The Institute of Electronic
`Information
`and Communication Engineers,
`1995
`Electronics Society Conference Proceedings, Volume 2,
`Page 2-220. FIG. 43 shows the structure of this circuit.
`[0017]
`13 through 16 are inverters structured from low threshold
`value transistors, where the power supply terminals and
`ground terminals thereof are connected, respectively, to the
`aforementioned virtual power supply line VDDV and
`virtual ground line GNDV. 17 and 18 are inverters
`structured from high threshold value transistors, where the
`power supply terminals and ground terminals thereof are
`connected respectively to the actual power supply line
`VDD and the actual ground line GND, to enable circuit
`operation even during sleep. 19-24 are CMOS transfer
`gates structured from low threshold value transistors, 25 is
`a CMOS transfer gate structured from a high threshold
`value transistors, CK is a clock signal, CKN is an inverted
`signal of the clock signal CK, D is an input terminal for
`DFF, Q is an output terminal for DFF, b1 and b2 are
`control signals, and b1n and b2n are inverted signals of the
`control signals b1 and b2. b1, b2, b1n, and b2a must retain
`the values thereof, even during sleep.
`[0018]
`During normal operation, when the signals b1 and b2 are
`both at the low level, the transfer gates 24 and 25 will both
`be OFF, the transfer gate 23 will be ON, and operation will
`be as a normal DFF circuit. When entering into sleep,
`control is carried out as follows:
`[0019]
`(1) First, the clock CK is tied to the low level. The
`transfer gates 19 and 22 are ON and the transfer gates 20
`and 21 are OFF, so the input signal D is cut off by the
`transfer gate 21, and thus the data that has been latched up
`to this point is latched by the latch circuit structured from
`the inverters 15 and 16 and the transfer gates 22 and 23.
`[0020]
`(2) Next, the signal b1 is put to the high level. The
`transfer gate 25 turns ON, so this latched data appears at
`the inverters 17 and 18.
`[0021]
`(3) Next, when the signal b2 is put to the high level and
`b1 is put to the low level, the data described above is
`latched in the latch circuit structured from the inverters 17
`and 18 and the transfer gate 24. Simultaneously with this,
`the transfer gate 25 turns OFF, preventing corrup