IEEE JOURNAL 01' SOLID-STATE CIRCUITS. VOL. 30. NO. 8. AUGUST 1995
`
`847
`
`1-V Power Supply High-Speed Digital Circuit
`Technology with Multithreshold-Voltage CMOS
`
`Shin' ichiro Mutoh, Member, IEEE, Takakuni Douseki, Member, IEEE, Yasuyuki Matsuya, Member, IEEE,
`Takahiro Aoki, Member, IEEE, Satosh.i Shigematsu, Member, IEEE, and Junzo Yamada, Member, IEEE
`
`Abstracl-1-V power supply high-speed low-power digital
`circuit technology with O.S-11m multitbreshold-voltage CMOS
`(MTCMOS) is proposed. This technology features both low(cid:173)
`threshold voltage and blgb-threshold voltage MOSFET's in a
`single lSI. The low-threshold voltage MOSFET's enhance speed
`penonnance at a low supply voltage of 1 V or less, wblle the
`higb-tbreshold voltage MOSFET's suppress the stand-by leakage
`current during the sleep period. This technology has brought
`about logic gate characteristics of a 1.7-ns propagation delay
`time and 0.3-,..WIMHz/gate power dissipation with a standard
`load. In add.ition, an MTCMOS standard cell library has been
`developed so that conventional CAD tools can be used to lay out
`low-voltage LSI's. To demonstrate MTCMOS's effectiveness, a
`PLL LSI based on standard cells was designed as a carrying
`vehicle. 18-MHz operation at 1 V was achieved using a o.s.,..m
`CMOS process.
`
`1. INTRODUCTION
`
`A low-power design is essential to achieve miniaturiza(cid:173)
`
`tion and long battery life in battery-operated portable
`equipment. Recently, there has been rapid progress in per(cid:173)
`sonal communications service (PCS) based on battery drives,
`including digital cellular phones, personal digital assistants,
`notebook, and palm-top computers. Future PCS will be more
`dedicated to multimedia systems, and thus the LSI's, the
`key component of the equipment, are desired not only for
`low-power consumption but also for higher signal or data
`processing capability [1], [2). In order to promote this develop(cid:173)
`ment, the demand for LSI designs achieving both low-power
`and high-speed performance should become stronger.
`Lowering the supply voltage is the most effective way to
`achieve low-power performance because power dissipation in
`digital CMOS circuits is approximately proportional to the
`square of the supply voltage. From the point of view of
`applications to battery-powered mobile equipment, the supply
`voltage should be set at I V [1). 1-V operation enables direct
`battery drive by a single Ni-Cd or Ni-H battery cell even taking
`the cell's discharge characteristic into account. This provides
`the smallest size and lightest weight equipment and eliminates
`the need for a power wasting de-to-de voltage converter.
`
`Manuscript received April 25, 1994; revised December 21, 1994.
`S. Mutoh. T. Douseki, Y. Matsuya, S. ShigemalSu, and J. Yamada are with
`High-Speed Integrated Circuits Laboratory, NTT LSI Laboratories, Kanagawa
`243·01, Japan.
`T. Aoki is with Project Team-4, NTT LSI Laboratories. Kanagawa 243-01,
`Japan.
`IEEE Log Number 9412024.
`
`However, it is generally rather difficult to reduce the supply
`voltage to I V. The drastic degradation in speed is the largest
`problem. Although several studies of high-speed 1-V oper-ating
`DRAM's have been reported [3], [4], they seem difficult to
`apply to general logic circuits because they assume st.and-by
`node voltages throughout the entire circuit are predictable in
`memory LSI's, and utilization of the conventional layout CAD
`tool is thought to be difficult. Therefore, the development of
`novel circuit technology that achieves high-speed operation
`at a low voltage of 1 V with only a single battery drive
`and can be easily applied to random logic circuitS is the key
`to developing the LSI designs for mobile equipment in the
`multimedia era.
`This paper proposes just such a new 1-V high-speed circuit
`technology that is applicable to all digital CMOS circuitS
`[5]. We call it multithreshold-voltage CMOS (MTCMOS). ItS
`unique feature is that it uses both high- and low-threshold
`voltage MOSFET's in a single chip. In the next section, key
`issues in low-voltage operation are discussed. The MTCMOS
`technology and its main characteristics are described in Section
`III. In Section IV, layout schemes based on a standard cell and
`chip configurations are discussed. Finally, the performance of
`a PLL LSI designed and fabricated using a 0.5-Jim CMOS
`process as a carrying verucle for MTCMOS technology is
`. shown in Section V.
`
`II. DESIGN [SSUES FOR LOW VOLTAGE CMOS CIRCUITS
`
`A. Low-Voltage Operation
`Power dissipation in digital CMOS circuits is approximately
`expressed as
`
`(I)
`
`where C L is the load capacitance, V dd is tbe supply voltage,
`and fop is the operating frequency. According to this formula,
`lowering vdd is the most effective way to reduce power
`dissipation because it is proportional to the square of vdd·
`Fig. I shows the relation between power consumption and
`supply voltage. lt is apparent that lowering Vdd contributes
`significantly to power reduction. Reducing supply voltage from
`the 3.3 V, widely used at present, to I V realizes about l/10
`the power dissipation. Certainly, scaling down CL or fop in
`( l) also contributes to low-power operation. Decreasing capac-
`
`0018--9200/95$04.00 © 1995 IEEE
`
`AMD EX1005
`U.S. Patent No. 6,239,614
`
`0001
`
`

`

`848
`
`!EF.E JOURNAL OF SOLID-STATE CIRCUITS. VOL 30. NO. 8. AUGUST 1995
`
`1.0
`
`.£.
`c
`
`P : Cl Vdd2 fop
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`0.0
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`
`4.0
`
`Fig. I. Relation between power consumption and supply voltage.
`
`itance CL, however, would be difficult without scaling down
`the device and wiring, and higher throughput performance
`usually requires an increase in frequency fop. Although there
`have been attempts to lower fop by introducing parallel
`processing, this approach generally increases hardware over(cid:173)
`head and requires extensive reworking at an architecture or
`algorithm design level [2).
`
`B. Key Issue for Low-Voltage Operation
`Although lowering Vdd to I V is effective in lowering power
`dissipation, as previously described, it is generally difficult
`because the speed perfom1ance is dramatically reduced at
`lower voltages. ln CMOS digital circuits, the gate delay time
`(tpd) is approximately given by
`
`CLVdd
`/.pd (X -~-- :::::
`DS
`
`CLVdd
`2
`A V.td - 1/i,,)
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`tOES
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`Fig. 2. Gate delay time and subthreshold leakage current dependence on
`threshold voltage.
`
`a MOSFET I.,.b at Vas = 0 is expressed as
`
`)
`-Vth
`l sub oc exp Sfln 10
`(
`
`(3)
`
`where Vi~t is the threshold voltage of a MOSFET. and S is
`subthreshold swing. Leakage current characteristics at a Vdd
`of I V are also shown in Fig. 2. These values are calculated
`assuming S is 85 mY/decade. As Vih is reduced by 0.1 V, I .wb
`becomes about ten times larger. This becomes Lhe source of
`the large stand-by current. With respect io portable equipment.
`in particular. the stand-by period is generally much longer
`than tbe operating period. Therefore. an increased stand-by
`current wastes battery power seriously. That is why it has
`been difficult to satisfy rhe requirements for both high-speed
`and low stand-by power at a low supply voltage of I V.
`
`where CL is the load capacitance, los is the drain current
`in the saturation region, Vdd is the supply voltage, Vi1, is
`the MOSFET's threshold voltage, and A is a constant. ln the
`above expression. lowering the supply voltage decreases 1 os
`proportional to the square of the voltage difference vdd- Vih.
`which results in a drastic increase in gate delay time as Vdd
`approaches Va, .
`Until now, supply voltage has generally been lowered by
`scaling down the device feature size to ensure the reliability of
`thin gate oxides [6], [7]. Speed performance is maintained even
`at low voltage due to the improvement in transconductance
`flm. brought about by shrinking feature size to a half or
`deep submicron size. Considering the increasing demand for
`extremely low-power operation. however, much lower voltage
`should be applied to devices in the same generation. In this
`case, a decrease in delay time at lower voltage must be
`achieved without relying on device feature size scaling.
`One way to overcome the speed degradation problem is to
`reduce the Va, of a MOSFET, as seen clearly in (2). Fig. 2
`shows the circuit characteristics dependence on 'llih· As Vdd
`gets lower from 2 to 1 V. gate delay time tpd becomes
`more sensitive to 'Vih. Therefore, reducing 'Vit. is effective
`to achieve high-speed operation at a Vdd of I V. As V0,
`is reduced , however, another significant problem emerges-a
`rapid increase in stand-by current due to changes in the
`subthreshold leakage current. Subthreshold leakage current of
`
`III. MTCMOS CIRCUIT T ECHNOLOGY
`
`A. Basic Circuit Scheme
`The new MTCMOS circuit technology is proposed to satisfy
`both requirements of lowering the threshold voltage of a
`MOSFET and reducing stand-by current, both of which are
`necessary to obtain high-speed low-power perforrnance at a
`vdd of I v.
`This technology has two main features. One is that N(cid:173)
`channel and P-channcl MOSFET's with two different thresh(cid:173)
`old voltages are employed in a single chip. The olher one
`is rwo operational modes, "active" and "sleep," for efficient
`power management.
`Fig. 3 shows the basic MTCMOS circuit scheme with the
`NAND gates. The logic gate is composed of MOSFET's with
`a low threshold voltage of about 0.2-0.3 V.lts power terminals
`are not connected directly to the power supply lines VDD and
`GND. but rather to the .. virtual" power supply lines VDDV
`and GNDV. The real and virtual power lines arc linked by
`MOSFET' s Q I and Q2. These have a high threshold voltage of
`about 0.5-0.6 V and serve as sleep control transistors. Signals
`SL and S L, which arc connected to the gates of Q I and Q2,
`respectively, are used for active/sleep mode control. Circuit
`operation in each mode at a supply voltage of I V is described
`below.
`
`0002
`
`

`

`MUTOH <1 ul.: 1-V POWER SUPPLY HIGH-SPEED DIGITAL CIRCUIT TECHNOLOGY
`
`849
`
`Low-VIhTr
`
`1~
`D
`
`Low-VIh gate
`
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`
`1~
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`
`Higi>-VIh gale
`
`VDD
`
`SL-i
`
`-L. CV1 T
`
`-L CV2
`T
`
`Fig. 3. MTCMOS circuil scheme.
`
`In the active mode, when SL is set low, Ql and Q2 are
`turned on and their on-resistance is so small that VDDV and
`GNDV function as real power Lines. Therefore, the NAND
`gate operates normally and at a high speed because the Vth of
`0.3 V is low enough relative to the supply voltage of L V.
`In the sleep mode, when SL is set high, Q I and Q2 are
`turned off so that the virtual lines VDDV and GNDV are
`assumed to be floating. The relatively large leakage current
`determined by the subthreshold characteristics of low-l/;1,
`MOSFET's, is almost completely suppressed by Ql and Q2
`since they have a high Vth and thus a much lower leakage
`current Therefore, power consumption during the stand-by
`period can be dramatically reduced by the sleep controL
`It should be pointed out that two other factors affect the
`speed performance of an MTCMOS circuit One is the size
`of the sleep control transistors Ql and Q2, and the other is
`the capacitances Cv 1 and Cv2 of the virtual power lines.
`Ql and Q2 supply current to the virtual lines. The larger
`their gate widths are designed, the smaller the on-resistance
`becomes. Cv 1 and Cv2 also act as temporary supply sources
`to internal logic gates. Thus, the voltage rise in GNDV and
`drop in VDDV caused by the switching of the internal logic
`gate are suppressed by setting them large enough to maintain
`high-speed performance.
`To confirm the effects, simulations were carried out. Fig. 4
`shows the gate delay time tpd and effective supply voltage
`V,1 1 dependence on the normalized gate width of sleep control
`transistors W H /WL along with the simple single MTCMOS
`circuit model used for simulations, where Vel 1 is defined as
`the minimum value of spontaneous voltage difference between
`VDDV and GNDV (between node a and b in this simulation).
`It is clear that Larger Cv , virtual line capacitance, and W H ,
`sleep control transistor width, maintain the effective supply
`
`voltage v., 1 for the internal logic gates and enhance the
`
`speed performance. For instance, a W H fW ~ of 5 and C v /Co
`of 5 keep the decrease in Veff within 10% of Vdd and the
`degradation in gate delay time within 15% compared to a
`pure low-ll;h CMOS. The area penalty for the wider gate
`transistors is relatively small because they are shared by all
`the logic gates on a chip. As for Cv, the above condition is
`generally met in an actual LSI because Cv includes the source
`capacitances of all the logic gates connected to virtual power
`lines and wiring capacitances. Therefore, nothing extra need
`be added.
`
`(a)
`
`(b)
`
`Fig. 4. Gate delay time and effective supply voltage dependence on the
`normalir.ed gate width of the sleep control transistor. (a) Simulation results.
`(b) Simulation circuit model.
`
`5.0
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`4.0
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`
`~ "'3.0
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`~ 2.0
`>-
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`NAND gate
`F.0 .• 3
`Al :1mm
`
`1.5
`1.0
`Supply Voltage (V)
`
`2.0
`
`(a)
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`
`Coov.CMOS
`(fu'l H-Vth)
`
`NAND gate
`F.0 . •3
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`1.6
`¥ 1.4
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`t 0.4
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`1.0
`1.5
`Supply Voltage M
`
`2.0
`
`{b)
`Fig. 5. MTCMOS performances. (a) Gate delay time. (b) Normalized power
`delay product dependence on supply voltage.
`
`B. Electrical Performance
`The measured MTCMOS logic gate delay time is shown
`in Fig. 5(a) as a function of supply voltage. Data for the
`conventional full high- v;h and full low-V1h CMOS logic gates
`are also plotted for comparison. It is obvious that the voltage
`dependence of an MTCMOS gate delay is much smaller than
`that of a conventional CMOS gate with high-ll;h and that the
`MTCMOS gate operates almost as fast as the full low-V11,
`gate. At a 1-V power supply, the MTCMOS gate delay time
`is reduced by 70% as compared with the conventional CMOS
`gate with high-Vih· The dependence of normalized power(cid:173)
`delay product (NPDP) on supply voltage is shown in Fig. 5(b),
`
`0003
`
`

`

`850
`
`IEEE JOURNAL OF SOLID-STATE CIRCUITS. VOL. 30. NO. 8. AUGUST 1995
`
`TABLE I
`CIMRAC'l'ERISTICS OF MTCMOS CIRCUIT Tr;cHNOLOGY
`
`Power supply voltage
`I.OV
`1.7 nslgate
`Propagation delay time
`Power di&.~ipation
`0.3 f1WIMH•Jga.to
`(2-input NAND with F.0.-3. line - I mm)
`
`VDD
`
`(a)
`
`\b)
`
`Fig. 6. MTCMOS latch circuit. (a) The proposed circuit. (b) Tite problem
`of the leakage current path.
`
`where power consumption is normalized by frequency. At low
`voltages. especially below 1.5 V, the NPDP of the MTCMOS
`is much less than that of the conventional high· Vu, gates.
`reflecting the improved speed performance at lower voltage.
`The smalles1 NPDP is achieved around I V in the MTCMOS
`gates. This shows that power reduction effect proportional to
`the square of supply voltage overcomes speed degradation in
`low-voltage operation. In addilion, it was confirmed that the
`stand-by current was reduced three or four orders of magnitude
`due to the sleep control.
`From these results, it is clear that MTCMOS circuit technol(cid:173)
`ogy achieves both high-speed and low-power operations at a
`low supply voltage of I V or less. The measured characteristics
`related to this circuit technology are summarized in Table 1. At
`I V, NAND gate delay time is typically 1.7 ns per gate, and
`power consumption is 0.3JtW!MHz per gate with a standard
`output load of three fanouts and 1 mm of wiring. MTCMOS
`gate operates about three times faster than conventional 0.5·
`J-'m CMOS gate. Power dissipation of 0.3/LW/MHz is 1/10 of
`the power needed for 3-V operation.
`
`C. Design of Flip-Flop Circuit
`
`Special attention must be paid to the MTCMOS design of
`latch or flip-Hop circuits that have memory functions. This
`is because memorized data in latch or flip-flop circujts must
`be retained even in the sleep mode when virtual power lines
`arc floating to cut leakage current completely. The proposed
`MTCMOS latch circuit is shown in Fig. 6(a), which is used
`for Hip-flop circuits. The features are described below.
`I) A convendonal inverter 02 and a newly added one 03
`are composed of high-Vu, MOSFET's. They are connected
`directly to the true power supply lines VDD and OND. The
`latch path consists of G2 and 03, which are always provided
`with power. Therefore. data can be retained even in the sleep
`
`L.alm.
`F.0. • 3
`AL:1mm
`
`Conv.CMOS
`(1\Jll L.Yih)
`
`1.2
`1.0
`Supply Voltage M
`
`1.4
`
`1.6
`
`Fig. 7.
`
`.Latch circuit delay lime dependence on supply \'Ohage.
`
`mode, when the clock signal CLK is fixed by using the
`sleep control signal SL. G3 is designed to be smaller to
`suppress both the increases in the gate delay time and the
`area.
`2) As for the forward path, the inverter 0 I and the CMOS(cid:173)
`type transmission gate TO are composed of low -Vth MOS(cid:173)
`FET's. This makes high-speed operation possible at 1-V power
`supply. This circujt also includes local sleep control transistors
`QLl and QL2 with high-V1h. The reason for including them
`can be understood with Fig. 6(b), where a node N I is assumed
`to maintain a ''low" state in the sleep mode. If 0 I were
`connected directly to the virtual power Line VDDV, as shown
`in this figure, VDD and VDDV would be short through M I
`and M3, so that stand-by current would be increased in the
`sleep mode. Therefore. QL I and QL2 are indispensable for
`completely cutting the leakage current path. Fig. 7 shows the
`simulation results for the delay time of the MTCMOS latch
`circuit. They confirm that the delay time is reduced by 50%
`at I V compared with that of the conventional circuit with
`high-V, 1,. Furthermore. the stand-by current in the sleep mode
`was also confirmed to be almost as low as that of the high-Va,
`circuit.
`
`IV. CHIP LAYOUT SCIIEME
`In order to make this low-voltage technology practical.
`conventional CAD tools must be applicable to lay out an
`MTCMOS LSI easily without any special consideration of
`the particular circuit scheme. To meet this requirement, the
`MTCMOS standard cell library was developed.
`Fig. 8 shows the MTCMOS layout scheme based on a
`standard cell. The main feature i$ rhat rhe extra components of
`the MTCMOS circuit are buried in the cells. More specifically.
`the virtual power supply lines (VDDV and GNDV) and the
`sleep control signal line (SL) are buried in each cell, while the
`sleep control transistors Q I and Q2 with high-\lth are buried in
`the power supply cell that provides the area needed to connect
`the true and virtual power supply lines to each other in the x
`and y directions. Power supply cells nre placed on both sides
`of the logic cell based core. The true power supply lines VDD
`and OND. which are also placed in each cell, fix the voltage
`of either the substrate or the well and supply current to flip(cid:173)
`Hop circuits. TI1is layout scheme allows the extra MTCMOS
`components to be connected automatically throughout the chip
`by abutting cells with n minimum increase in chip area.
`
`0004
`
`

`

`MUTOH .r ..Z.: 1-V POWEll SUPI'I..Y HlOH·SPEED DIGITAL CIRCUIT ta:HNOUlGY
`
`S.SI
`
`...,,.w
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`10 20 30 .0 so eo
`S.O.R.~J
`
`1.0
`0
`
`1
`
`j
`
`Fig. 8. Chip layout scheme based on a standard cell.
`
`(a)
`
`Fig. 9. Gate delay lime and effective wpply YOitage depellMnce on
`Switch-On-Rate (SOR). (a) Simulation circ:uil model. (b) Gate delay lime
`and effective supply voltage versus SOR.
`
`Because Ql and Q2 can be placed just under the power
`supply lines in the power supply cell, their insertion would
`incur no area penalty. Furthermore, the virrual power lines
`VDDV and GNDV in each row are connected together so that
`one ceil can be supplied current through aJI the sleep control
`transistors within the chip, which contributes to suppress speed
`degradation.
`ln this experiment, W H, the poly-gate width of sleep control
`transistors Ql and Q2 in a power supply cell, was design
`to be ten times larger than that in the logic ceUs (WL). Ql
`and Q2 are shared by all the logic gates connected to the
`virruaJ power lines in this scheme. Therefore. the simultaneous
`switch-on rate (SOR). which indicates how many logic gates
`are switched on at almost the same time, seems to affect speed
`performance, especially in MTCMOS circuits. The amount of
`current supplied through Q I and Q2 depends on the switching
`probability of the internal logic gates. Thus, a high SOR
`enhances the voltage drops at Q I and Q2, which consequently
`reduces the effective supply voltage between VDDV and
`GNDV. Fig. 9 shows the simulation results for the SOR along
`
`(a)
`
`(b)
`
`lnJiuences of virtual power supply Unes. (a) Simulation circuit
`Fig. 10.
`model. (b) Gate delay time versus SOR.
`
`TABLE U
`0EVIC6 'l'EaiN<lLooY
`
`Gate length
`Gate oxide thichness
`N-c:hannei:Vtb
`P-cbannel : Vlh
`
`High-VIhTr
`O.SS}Uil
`IIOA
`0.55 v
`.().65 v
`
`Low-Vtt.Tr
`0.6S }U1l
`I lOA
`0.2SV
`.0.35 v
`
`with the circuit model. Here, the SOR is defined as m/n.
`where m and n indicate the number of operating logic blocks
`and the total number of blocks, respectively, assuming a 2-
`mm block width. As the SOR increases, the voltage on VDDV
`drops because Q I has to supply more current to VDDV at one
`tjme. For similar reasons, the voltage also rises on GNDV.
`These voltage changes cause the effective supply voltage Veff
`between VDDV and GNDV to decrease, extending gate delay
`time. Generally, however, the SOR is expected to be at mos1
`
`20 or 30%. In this region, the reduction of v.,,, is less th.an
`
`15% of the supply voltage, and the speed performance of 1.7
`ns/gate is still quite high.
`One way to further decrease the dependence of speed
`performance on the SOR is to use a sleep control lrllDSistor
`with a wider gate. This is. however. a trade-off between speed
`and stand-by current because total stand-by current in a chip
`is approximately given by 2KWHiu. Here, K is the number
`of rows in the block shown in Fig. 8, while W H is the gate
`width of the sleep control transistor, and In is its leakage
`current when the gate's width and length are equal. Another
`effective way to decrease this dependence is to remove one
`set of the two sleep control transistors and virtuaJ power lines.
`The expected improvements in speed are shown in Fig. 10
`along with simulation circujts. By removing of GNDV (b-1)
`and VDDV (b-2). gate delay time can be reduced by 15-25%
`compared with the basic scheme. The removal of VDDV is
`clearly more effective in increasing speed. The reason for this
`is that the threshold voltage of the P-channel MOSFET (Ql)
`was designed to be higher than that of the N-channel one
`(Q2) in this study (see Table II).
`
`V. TEsT CHIP RESULTS
`
`A. Process and Device Technology
`To confirm the effectiveness of MTCMOS circuit technol(cid:173)
`ogy, a PLL LSI using new MTCMOS standard cells was
`
`0005
`
`

`

`852
`
`IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. JO. NO. 8. At,;OUST 1995
`
`0.5
`
`1.5
`1.0
`Supply Voltage M
`
`2.0
`
`Fig. 12. Operation frequency of the PLL chip.
`
`5.0 ..---~-~------~·
`
`~4_0 top-•z.s MH> /eor~~al •
`~ 130
`('0
`
`"- 1.0
`
`1.0
`
`4.0
`3.0
`2.0
`Supply Voltago M
`
`5.0
`
`Fig. 13. Power dissipation of the PLL chip versus supply voltage.
`
`Fig. I I. Microphotograph of the PLL chip.
`
`TABLE nl
`AREA PENAt:rY FACTOR
`
`Combinational Circuit
`Sequential Circuit
`PLL LSI Digital Core
`
`1.1
`2.0
`I .3
`
`designed and fabricated. Convenlional 0.5-J.Lffi CMOS process
`technology for 3.3-V operation with single-polysilicon and
`double-metal layers wa<; used. MOSFET's with different V0 , 's
`in the same well were formed by optimizing the impurity
`concentration in the well and controlling the channel doses
`with two additional masks, which minimizes the increase
`in the number of process steps. The key device parameters
`and characteristics are summarized in Table ll. The gate
`length of the low-V1,. MOSFET is 0.65 ttm, which is 0.1
`ttm longer than that of the high-Vth ones. This is preferable
`to suppress variations in the threshold voltage due to short(cid:173)
`channel effects. The gate oxide thickness is J 10 A for both
`types of MOSFET' s. The low-Va, 's are 0.25 V for N-channel
`and - 0.35 V for P-channel MOSFET's.
`A microphotograph of the PLL chip is shown in Fig. 11.
`This chip consists of about 5 K gates, including the automatic
`frequency control circuit and the intermittent operation con(cid:173)
`troller [8]. The whole chip is 4 x 5 mm2 , and the digital core
`is about 2 x 2 mm2. Table m lists the area penalty factors
`in this study. An MTCMOS combinational circuit cell bas an
`area about I 0% larger than a conventional ceU does owing
`to the insertion of virtual supply lines and the sleep control
`line. A sequential circuit cell, such as an MTCMOS OFF with
`clear, needs an area about twice that of a conventional cell in
`order to store data even in the sleep period. The area increase
`for the whole digital core, however. is only 30% in spite of
`the fact that the OFF's occupy a relatively large part (about
`50%) of the total gate counts. This is because the channel
`area is almost unchanged. Moreover, because all OFF's in
`an actual LSI aren't expected to hold the date during sleep
`
`IM
`lOOk
`10k
`Operation frequency (Hz)
`
`Fig. I4. Power dissipation of tho PLL chip versus operation frequency.
`
`period, the area penalty can be further reduced by appropriately
`combining the use of a conventional DFF and the DFF with
`a special memory function.
`
`B. Chip Performance
`Fig. 12 shows the measured operation frequency as a func(cid:173)
`tion of supply voltage. At I V, the chip operates at 18 MHz
`which is sufficient for many applications.
`Fig. 13 shows the power dissipation in the djgital core as a
`function of supply voltage at an operation frequency of 12.8
`MHz. The power dissipation of the conventional 5-V operation
`PLL is also plotted for comparison. At I V, power dissipation
`is drastically reduced to below 1120 compared with that of the
`conventional LSI operated at 5 V.
`Fig. 14 shows another aspect of the power perfor(cid:173)
`mance-
`the operating current versus the operating fre{)uency
`for the worst case at a supply voltage of I .2 Y. Although the
`operating current is proportional to the frequency in the region
`over I MHz. it becomes almost constant in the low-frequency
`region. This is due to the leakage current caused by using
`low-Vih MOSFET's. In the active mode, the leakage current
`of about 30 ttA in thjs chip is negUgible because it is less
`
`0006
`
`

`

`M\JI'OH <t o.l.: 1-V POWER SUPPLY HIGH-SPEED DIGITAL CIRCUIT TECHNOLOGY
`
`8S3
`
`TABLE IV
`CHARACTERISTICS OF n!E PLL CHiP
`
`Power supply vohage
`Core size
`Cycle frequency
`Power dissipation
`SlaDd-by cunent
`Tum-on time
`GatecounlS
`
`I.OV
`2.4 mm x 2.3 mm
`18MH2
`200 11W (at 10 Mfu)
`<5GnA
`<SOOns
`5 K gates
`
`than 1/10 of the dynamic current consumption at a desired
`operating frequency of over 1 0 MHz. In the sleep mode, on
`the other hand, the current is dramatically reduced to below
`50 nA, so that low stand-by characteristics can be obtained.
`Typical PLL LSI features are summarized in Table IV. The
`tum-on time, which is the time needed to switch from sleep
`to active mode, is less than 500 ns even in the worst case.
`
`VI. CONCLUSION
`Multitbreshold-voltage CMOS (MTCMOS) circuit technol(cid:173)
`ogy has been proposed as a way to achieve a 1-V supply
`voltage high-speed and low-power LSI operation. This tech(cid:173)
`nology uses MOSFET's with two different threshold voltages
`on a single chip and introduces a sleep control scheme for effi(cid:173)
`cient power management. Low-threshold voltage MOSFET's
`improve the speed performance at a low supply voltage of
`1 V, while high-threshold MOSFET's suppress the stand(cid:173)
`by power dissipation. rn addition, a standard ceU Library
`has been developed to simplify low-voltage LSI designs. To
`demonstrate the effectiveness of this technology, a PLL LSI
`based on standard cells was designed as a carrying vehicle
`using a 0.5-~-tm CMOS process. High-speed operation of 18
`MHz at I V confinned the validity of this new technology.
`
`ACKNOWLEDGMENT
`The authors would like to thank S. Horiguchi, E. Arai, N.
`leda, and K. Imai for their suggestions and encouragement.
`
`REFERENCES
`
`[1] R. W. Brodersen. A. Chandrakasan, and S. Sheng. ''Design techniques
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`1993.
`[2] A. P. Chandtakasan, S. Sheng, and R. W. Brodersen. "Low-power
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`473-484. Apr. I 992.
`[3] M. Horiguchi. T. Sakata, and K. hoh. "Switched-source-impedance
`CMOS circuit for low standby subthreshold current giga-scale LSI's,"
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`M. Aoki. "Subthre.~hold current reduction for decoded-driver by self(cid:173)
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`Nov. 1993.
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`in Proc. IEEE Int. ASIC Corif., Sept. 1993, pp. 18(>..189.
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`1992.
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`in Proc. IEEE vrc. 1992, pp. 752.-755.
`
`Sbin'icbiro Mutoh (M'93) was born in Tokyo.
`Japan. on October 12, 1963. He received !he B.E.
`and M.E. degrees in electronic engineering from
`Cbiba University. Chiba. Japan. in 1986 and 1988,
`respectively.
`In 1988. he joined Nippon Telegraph and
`Telephone Corporation (NTT), Tokyo, Japan. Since
`1988. he has been engaged in !he research and
`development of 1-V operating logic and memory
`circuit technology. He is now with !he High(cid:173)
`Speed Integrated CircuitS Laboratory, NTT LSI
`Laboratories, Kanagawa, Japan.
`Mr. Mutob is a member of !he Institute of Electronic. lnfonnation, and
`Communication Engineers of Japan.
`
`Takakunl Douseki (M'93) was born in Fukui,
`Japan. on January I 2, 1958. He received !he B.S.
`and M.S. degrees in electrical engineering from
`Fukui University, Fu.kui, Japan, in 1980 and 1982.
`respectively.
`In 1982, he joined !he Musashino Electrical
`Communication Laboratory, Nippon Telegraph and
`Telephone Public Corporation (NTT). where he
`worked on the design of static MOS memory. He
`i.s currently a senior research engineer with NTT
`LSI Labora1ories, Kanagawa, Japan, where he is
`engaged in research on !he scaled-down BiCMOS. CMOS, and bipolar
`circuils.
`Mr. Dousetci is a member of the Institute of Electronic, Jnfonnation. and
`Communica1ion Engineen; of Japan and !he Japan Society of Applied Physics.
`
`Yasuyuld Matsuya (M'87) was born in Aomori.
`Japan, on February 14, 1956. He received the B.E.
`degree in electronic engineering from lwate Univer(cid:173)
`sity, lwate, Japan, in 1978.
`In 1978, he joined !he NTT Electrical Commu(cid:173)
`nications Laboratories in 1978. where he worked
`on !he design of higb resolution NO and D/ A
`convenefS. He is currently with !he High-Speed In·
`tegrated Circuits Laboratory. NTT LSI Laboratories.
`Kanagawa, Japan. He has been engaged in research
`on the low voltage power supply NO and 0/A
`
`conversion technology.
`Mr. Matsuya is a member of the Institute of Electronic. Information. and
`Communication Engineers of Japan.
`
`Takahiro Aokl (M'85) was born in Nagoya, Japan.
`on November 25, 1955. He received !he B.S. and
`M.S. degrees in electrical engineering from Nagoya
`University, Nagoya, Japan. in 1978 and 1980, re(cid:173)
`spectively.
`From 1980 to 1983, he wa.~ with !he Musasbino
`Electrical Communication Laboratory, Nippon Tele(cid:173)
`graph and Telephone Public Corporation (NTT),
`Tokyo, Japan. In 1983. he joined !he NTT Atsugi
`Electrical Communication Laboratory (now. NTT
`LSI Labordtories) Kanagawa. Japan. He has been
`engaged in !he research and development of !he CMOS logic LSI design,
`latch-up modeling and characterization, half-micron CMOS/BiCMOS device
`design, and I-V operated low power CMOS process/device design. His present
`res