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`UNITED STATES PATENT AND TRADEMARK OFFICE
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`ADVANCED MICRO DEVICES, INC.
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`Petitioner
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`v.
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`AQUILA INNOVATIONS INC.
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`Patent Owner
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`Case IPR2019-01525
`Patent 6,239,614 B1
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`PATENT OWNER’S RESPONSE
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`

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`TABLE OF CONTENTS
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`Page
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`
`
`I. 
`
`II. 
`
`INTRODUCTION .......................................................................................... 1 
`
`TECHNICAL BACKGROUND .................................................................... 3 
`
`III.  CLAIM CONSTRUCTION. .......................................................................... 7 
`
`A. 
`
`B. 
`
`C. 
`
`D. 
`
`E. 
`
`F. 
`
`“Unit Cell.” ......................................................................................... 10 
`
`“A Unit Cell Array Comprised Of Said First And Second Unit
`Cells Laid In Array Form.” ................................................................ 12 
`
`“A Power Switch.” ............................................................................. 13 
`
`“A Power Switch Disposed Around Said Unit Cell Array And
`Comprised Of A Plurality Of Third MOS Transistors” ..................... 14 
`
`“A Plurality Of Input/Output Circuits Disposed Around Said
`Unit Cell Array” ................................................................................. 15 
`
`“Parts Of Said Power Switch Disposed Within Said Unit Cell
`Array” ................................................................................................. 16 
`
`IV. 
`
`INTRODUCTION TO THE REFERENCES PETIONER ASSERTS
`IN GROUNDS 1 & 2. ................................................................................... 17 
`
`V.  GROUND 1: PETITIONER HAS NOT PROVEN CLAIMS 1-3 OF
`THE ’614 PATENT ARE UNPATENTABLE BECAUSE ONE OF
`ORDINARY SKILL WOULD NOT COMBINE URANO AND
`MUTOH021 .................................................................................................. 19 
`
`A. 
`
`B. 
`
`Petitioner Does Not Establish That Arranging Power Switch
`Cells To “Encircl[e] The Unit Cell” Was An Improvement Over
`Urano’s “Both Ends Vertically” Arrangement. ................................. 21 
`
`Petitioner Does Not Establish That An “Encircle” Arrangement
`Was A Known Technique That Would Improve Urano’s “Both
`Ends Vertically” Arrangement. .......................................................... 22 
`
`-i-
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`

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`TABLE OF CONTENTS
`(continued)
`
`Page
`
`
`
`C. 
`
`D. 
`
`E. 
`
`A Person Of Ordinary Skill In The Art Would Not Have
`Recognized That An “At All Ends Vertically And
`Horizontally” Arrangement Would Predictably Improve
`Urano’s “Both Ends Vertically” Arrangement. ................................. 25 
`
`Petitioner Fails To Demonstrate That Urano and Mutoh021
`Could Be Readily Or Predictably Combined. .................................... 30 
`
`Petitioner’s Proposed Combination Is Above The Level Of
`Ordinary Skill In The Art. .................................................................. 33 
`
`VI.  GROUND 2: PETITIONER HAS NOT PROVEN CLAIMS 1-3 OF
`THE ’614 PATENT ARE UNPATENTABLE BECAUSE ONE OF
`ORDINARY SKILL WOULD NOT COMBINE MUTOH AND
`MUTOH021 .................................................................................................. 35 
`
`A. 
`
`B. 
`
`C. 
`
`D. 
`
`E. 
`
`Petitioner Does Not Establish That Arranging Power Switch
`Cells “On All Sides Of The Unit Cell Array” Was An
`Improvement Over Mutoh’s “Both Sides Of” Arrangement. ............ 37 
`
`Petitioner Does Not Establish That An “At All Ends Vertically
`And Horizontally” Arrangement Was A Know Technique That
`Would Improve Mutoh’s “Both Sides Of” Arrangement. ................. 38 
`
`A Person Of Ordinary Skill In The Art Would Not Have
`Recognized That An “At All Ends Vertically And
`Horizontally” Arrangement Would Predictably Improve
`Mutoh’s “Both Sides Of” Arrangement. ............................................ 39 
`
`Petitioner Does Not Establish That Mutoh and Mutoh021 Could
`Be Readily Or Predictably Combined ................................................ 45 
`
`Petitioner’s Proposed Combination Is Above The Level Of
`Ordinary Skill In The Art. .................................................................. 47 
`
`-ii-
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`TABLE OF CONTENTS
`(continued)
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`Page
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`
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`VII.  THE PETITION FAILS TO ESTABLISH THE
`UNPATENTABILITY OF ANY CLAIM CHALLENGED IN
`GROUND 3 BECAUSE IT FAILS TO SHOW THAT CLAIMS 4-5
`ARE OBVIOUS OVER DOUSEKI IN VIEW OF RAMUS. ...................... 50 
`
`A. 
`
`Petitioner Fails To Establish A Motivation To Combine
`Douseki And Ramus. .......................................................................... 50 
`
`VIII.  INTER PARTES REVIEW IS UNCONSTITUTIONAL. ............................ 51 
`
`A. 
`
`B. 
`
`Inter Partes Review Violates The Appointments Clause. ................. 51 
`
`Inter Partes Review Violates The Takings And Due Process
`Clauses. ............................................................................................... 52 
`
`IX.  CONCLUSION ............................................................................................. 53 
`
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`-iii-
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`
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`TABLE OF AUTHORITIES
`
` Page(s)
`
`Federal Cases
`Abbott Labs. v. Sandoz, Inc.,
`566 F.3d 1282 (Fed. Cir. 2009) .......................................................................... 12
`
`ActiveVideo Networks, Inc. v. Verizon Communs., Inc.,
`694 F.3d 1312 (Fed. Cir. 2012) ...................................................................passim
`
`Arthrex, Inc. v. Smith & Nephew, Inc.,
`941 F.3d 1320 (Fed. Cir. 2019) .................................................................... 51, 52
`
`Broadcom Corp. v. Emulex Corp.,
`732 F.3d 1325 (Fed. Cir. 2013) .................................................................... 21, 37
`
`Celgene Corp. v. Peter,
`931 F. 3d 1342 (Fed. Cir. 2019) ......................................................................... 53
`
`Cias, Inc. v. All. Gaming Corp.,
`504 F.3d 1356 (Fed. Cir. 2007) .......................................................................... 16
`
`Edmond v. United States,
`520 U.S. 651 (1997) ...................................................................................... 51, 52
`
`Epistar Corp. v. ITC,
`566 F.3d 1321 (Fed. Cir. 2009) .......................................................................... 11
`
`Free Enter. Fund v. Pub. Co. Accounting Oversight Bd.,
`561 U.S. 477 (2010) ...................................................................................... 51, 52
`
`Freytag v. Commissioner,
`501 U.S. 868 (1991) ...................................................................................... 51, 52
`
`In re Fritch,
`972 F.2d 1260 (Fed. Cir. 1992) .......................................................................... 21
`
`Harmonic Inc. v. Avid Tech., Inc.,
`815 F.3d 1356 (Fed. Cir. 2016) ............................................................................ 1
`
`Hill-Rom Servs. v. Stryker Corp.,
`755 F.3d 1367 (Fed. Cir. 2014) .......................................................................... 13
`-iv-
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`Hologic v. Enzo,
`2018 Pat. App. LEXIS 5855 (P.T.A.B. April 18, 2018) ..................................... 8
`
`Innogenetics, N.V. v. Abbott Labs.,
`512 F.3d 1363 (Fed. Cir. 2008) .......................................................................... 46
`
`Insite Vision Inc. v. Sandoz, Inc.,
`783 F.3d 853 (Fed. Cir. 2015) ...................................................................... 21, 38
`
`KSR International Co. v. Teleflex Inc.,
`550 U.S. 398 (2007) ...................................................................................... 20, 37
`
`Lucia v. SEC,
`138 S. Ct. 2044 (2018) .................................................................................. 51, 52
`
`In re Magnum Oil Tools Int’l, Ltd.,
`829 F.3d 1364 (Fed. Cir. 2016) ............................................................................ 1
`
`Masias v. Sec’y of HHS,
`634 F.3d 1283 (Fed. Cir. 2011) .................................................................... 51, 52
`
`MobileMedia Ideas LLC v. Apple Inc.,
`780 F.3d 1159 (Fed. Cir. 2015) .................................................................... 33, 47
`
`Pacing Techs., LLC v. Garmin Int’l, Inc.,
`778 F.3d 1021 (Fed. Cir. 2015) .......................................................................... 11
`
`Runway Safe LLC v. Engineered Arresting Systems,
`IPR2015-01921, Paper No. 9 (P.T.A.B. February 29, 2016) ............................. 22
`
`Stryker Corp. v. Karl Storz Endoscopy America, Inc.,
`IPR2015-00764, Paper 13 (Sept. 2, 2015) .......................................................... 51
`
`TRW Automotive U.S. LLC v. Magna Electronics, Inc.,
`IPR2015-00972, Paper 9 (Sept. 16, 2015) ......................................................... 51
`
`Vivid Technologies, Inc. v. American Science,
`200 F. 3d 795 (Fed. Cir. 2000) ............................................................................. 9
`
`Regulations
`
`37 C.F.R. § 42.100 ..................................................................................................... 8
`
`-v-
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`

`
`
`Other Authorities
`IEEE Journal of Solid-State Circuits, Vol. 30, No. 8, 847-854 (1995) ............passim
`
`MPEP § 2143 ..................................................................................................... 20, 37
`
`Webster’s Third New International Dictionary (2002) ........................................... 15
`
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`-vi-
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`PATENT OWNER’S EXHIBIT LIST
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`
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`2002
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`2003
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`2004
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`Exhibit No. Description
`2001
`Email Correspondence with Board re Sur-Replies
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`Declaration of Dr. Steven A. Przybylski
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`Curriculum Vitae of Dr. Steven A. Przybylski
`
`Excerpts from Michael Vai, VLSI Design (2001)
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`Excerpts from Rabaey et al., Digital Integrated Circuits (2003)
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`Excerpts from Peter Van Zant, Microchip Fabrication (2000)
`
`Excerpts from Wai-Kai Chen, The VLSI Handbook (2007)
`
`
`2005
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`2006
`
`2007
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`
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`-vii-
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`Patent Owner Aquila Innovations Inc. (“Aquila”) submits this Patent Owner
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`Response to the Petition and Decision Granting Inter Partes Review, Paper Nos. 1
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`(“Petition”), 12.
`
`I.
`
`INTRODUCTION
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`“In an IPR, the petitioner has the burden from the onset to show with
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`particularity why the patent it challenges is unpatentable.” Harmonic Inc. v. Avid
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`Tech., Inc., 815 F.3d 1356, 1363 (Fed. Cir. 2016). “[T]hat burden never shifts to
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`the patentee.” In re Magnum Oil Tools Int’l, Ltd., 829 F.3d 1364, 1375 (Fed. Cir.
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`2016) (citation omitted).
`
`United States Patent No. 6,239,614 (the “’614 Patent”) is directed generally
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`to an improved semiconductor integrated circuit layout that utilizes MOS
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`transistors of varying threshold-voltages, described in the ’614 Patent as a
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`Multithreshold-Voltage CMOS or MTCMOS. See ’614 patent, col. 1, lines 26-27.
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`The MTCMOS consumes less power than conventional semiconductor integrated
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`circuits because it can operate at a lower voltage when active and leaks less power
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`current when it is inactive. Patent Owner has asserted the ’614 Patent against
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`Petitioner in the United States District Court for the Western District of Texas.
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`Petition at 4.
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`-1-
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`Petitioner contends that claims 1-3 of the ’614 patent are unpatentable as
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`obvious over Urano1 in view of Mutoh021,2 that claims 1-3 are unpatentable as
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`obvious over Mutoh3 in view of Mutoh021, and that claims 4-5 are obvious over
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`Douseki4 in view of Ramus.5 Petition at 6.
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`For Grounds 1 and 2, Petitioner relies on Mutoh021 to teach the “power
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`switch disposed around” limitation of claim 1. For Ground 3, Petitioner relies on
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`Ramus to teach the “first and second capacitors are constructed by connecting
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`MOS transistors placed within unit cells in array form” limitation of claim 4.
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`The Petition fails to prove, by a preponderance of the evidence, that claims
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`1-3 of the ’614 patent are unpatentable under Ground 1 and Ground 2 because
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`there is no credible evidence demonstrating why a person of ordinary skill in the
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`art would have combined Urano and Mutoh021 or Mutoh and Mutoh021. The
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`Petition also fails to prove, by a preponderance of the evidence, that claims 4-5 of
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`
`1 Japanese Patent Publication No. H10125878 to Masami Urano (“Urano”)
`2 Japanese Patent Publication No. H0818021 to Shin’ichiro Mutoh et al.
`(“Mutoh021”).
`3 Mutoh et al., “1-V Power Supply High-S peed Digital Circuit Technology with
`Multithreshold-Voltage CMOS,” IEEE Journal of Solid-State Circuits, Vol. 30,
`No. 8, 847-854 (1995) (“Mutoh”).
`4 U.S. Patent No. 5,486,774 to Douseki et al. (“Douseki”).
`5 U.S. Patent No. 5,631,492 to Ramus et al. (“Ramus”).
`
`-2-
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`

`

`
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`the ’614 patent are unpatentable under Ground 3 because there is no credible
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`evidence demonstrating why a person of ordinary skill in the art would have
`
`combined Douseki and Ramus. Instead, Petitioner misrepresents the teachings of
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`these references, relies on generic expert testimony that bears no relation to any
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`specific combination of prior art elements, and relies on hindsight bias to cobble
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`together the references.
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`Petitioner and its expert fail to carry their burden to show that the challenged
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`claims of the ’614 Patent are unpatentable. The claims of the ’614 patent should be
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`confirmed as patentable over the asserted references.
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`II. TECHNICAL BACKGROUND
`The ’614 patent teaches an integrated circuit design that arranges low-
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`threshold voltage transistors and high-threshold transistors together such that the
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`integrated circuit can be operated with a very low supply voltage without the
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`power leakage that is typically associated with low-threshold voltage transistors.
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`Przybylski Decl., Ex. 2002 ¶ 28 (citing Ex. 1001 at 1:6-12).
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`Integrated circuits are created using several layers on a semiconductor wafer.
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`Id. ¶ 29 (citing Ex. 2004 at 18). Some of the layers join together to form
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`transistors. Id. Other layers form wires that join the transistors to form circuits. Id.
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`“The layers that form the MOS transistors are in or directly on the wafer, and the
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`layers that interconnect the transistors are physically above the transistors.” Id. In
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`-3-
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`

`

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`circuit diagrams, these layers are depicted using transparency and cross hatching.
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`Id. ¶ 30.
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`For example, Figure 5 of the ’614 patent, below, depicts a portion of an
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`integrated circuit. Id.
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`
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`Ex. 1001 at Figure 5, 4:39-58. This diagram shows 5 different layers. Ex. 2002 ¶
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`31. Four of the layers form four transistors connected as two pairs in these base
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`levels. Id. One transistor is formed between source and drain regions 56 and 57 on
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`a layer known as the diffusion layer. Id. This transistor is controlled by a gate
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`electrode 54 that is located on a different layer. Id. (citing Ex. 1001 at 4:39-58).
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`-4-
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`

`

`
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`Above these two layers, is a third layer indicated by hash marks. Id. Structures 60,
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`61, 70, and 71 illustrate four wires, each of which is located this third level. Id.
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`This third level “is typically called Metal 1 or something comparable.” Id. (citing
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`Ex. 2004 Ex. 1005 at 852 Ex. 1008 at 0015, ¶¶ 0002, 0005; Ex. 1013 at ¶ 0025).
`
`Structures 62 and 72 are known as “contacts.” Id. “Contacts” are vertical
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`connections between the first two layers—the “transistor layers”—and Metal 1. Id.
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`Sometimes there is a second layer of metal—Metal 2—located above Metal 1.
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`When there are two or more levels of metal, vias (sometimes called though-hole
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`connections) connect Metal 1 to Metal 2. Id. (citing Ex. 1013 at Para. 25). The
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`lowest levels that make up the transistors are known as the front end, while the
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`metallization layers are called the back end. Id. “These names come from the
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`conceptual layout of a semiconductor manufacturing line, in which the lowest
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`layers are manufactured first, followed by the layering of the metallization layers
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`on top of them.” Id.
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`The transistor and diffusion layers can conduct signals and are occasionally
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`used to convey signals short distances. Id. ¶ 32. But “their intrinsic resistance make
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`only the metal layers useful for longer distant interconnections.” Id. (citing Ex.
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`1013 at Figure 4).
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`During fabrication, one or more masks are needed to define the regions of
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`each layer of the integrated circuit. Id. ¶ 33. Masks are expensive and time
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`-5-
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`

`

`
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`consuming to create. Id. The more layers of an integrated circuit, the more masks
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`will be needed, and the more expensive and time consuming it will be to
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`manufacture the integrated circuit. Id. (citing Ex. 200A at 1).
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`An important property of a MOS transistor is its threshold voltage. Id. ¶ 34.
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`The threshold voltage is the voltage that must be applied to turn on the gate
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`electrode of the transistor. Id. “Logic circuits made with transistors with lower
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`threshold voltages can be faster, but there is a cost of additional leakage current.”
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`Id. Leakage current is current that passes through the transistors from source to
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`drain even when the transistor is off. “This increased leakage current translates to
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`increased power consumption, even when the device is not doing useful work.” Id.
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`(citing Ex. 1001 at 1:7-33, 3:7-22).
`
`The idea behind MTCMOS (multi-threshold CMOS) is to
`fabricate the integrated circuits with two varieties of
`transistors: one set with a higher threshold voltages and
`lower leakage currents, and another set with lower
`threshold voltages. This allows for both high-speed/high-
`leakage
`circuitry
`and
`lower-speed/lower-leakage
`circuitry. In order to manage the wasted power of the
`former, power switches are included that can isolate and
`turn off chunks of low-Vt logic when they are not in use.
`
`Id. (citing Ex. 1001 at 1:14-50; Ex. 1005 at 847, 848-849).
`
`-6-
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`

`

`
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`Digital integrated circuit design is a two-phased process: the logic design
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`and the physical design. Ex. 2002 ¶ 35. Logic design progresses from a high-level
`
`or behavioral representation to a logic representation of the design. Id. (citing Ex.
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`2004 at 6-11). The physical design phase translates the logic representation into the
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`rectangles that represent regions on each of the masks that become areas of each
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`level of the physical stack. Ex. 2002 ¶ 35 (citing Ex. 2004 at 11-17).
`
`There are several unique design styles for circuit
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`design, including “full custom”, “standard cells”, and
`“gate arrays.” Ex. 2002 ¶ 36. In “standard cell” and “gate
`array” design styles,
`libraries of commonly used
`functions are designed by hand and then software
`Computer Aided Design (CAD) tools are used to
`translate the logical design into the physical design that
`will be ultimately fabricated. In these two design styles,
`the development of the libraries and their associated
`architecture and infrastructure, and the development of
`the logic design and the mapping of that logic design
`onto the library are performed by two separate groups of
`engineers with different skills and concerns, often
`working in different companies. Ex. 2004 at 11-17.
`
`Id.
`
`III. CLAIM CONSTRUCTION.
`Claims in an inter partes review proceeding “shall be construed using the
`
`same claim construction standard that would be used to construe the claim in a
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`-7-
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`

`

`
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`civil action under 35 U.S.C. 282(b), including construing the claim in accordance
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`with the ordinary and customary meaning of such claim as understood by one of
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`ordinary skill in the art and the prosecution history pertaining to the patent.” 37
`
`C.F.R. § 42.100.
`
`Petitioner asserts that six terms require construction: “unit cells”; “a unit cell
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`array comprised of said first and second unit cells laid in array form”; “a power
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`switch”; “a power switch disposed around said unit cell array and comprised of a
`
`plurality of third MOS transistors”; “a plurality of input/output circuits disposed
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`around said unit cell array”; and “parts of said power switch disposed within said
`
`unit cell array.”
`
`Petitioner, however, does not apply several of its proposed constructions
`
`under its asserted grounds, and the constructions it does apply are incorrect. “A
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`petition for an inter partes review must ‘[p]rovide a statement of the precise relief
`
`requested for each claim challenged,’ which ‘statement must identify . . . [h]ow the
`
`challenged claim is to be construed’ and ‘[h]ow the construed claim is
`
`unpatentable.’” Hologic v. Enzo, 2018 Pat. App. LEXIS 5855, *8 (P.T.A.B. April
`
`18, 2018) (citing 37 C.F.R. § 42.104(b)(3)-(4)). Under this standard, the petitioner
`
`must “advocate unpatentability under a claim construction it consider[s] to be
`
`correct.” Hologic, 2018 Pat. App. LEXIS 5855, at *9.
`
`-8-
`
`

`

`
`
`In Ground 2 and 3, Petitioner asserts that ’614 Patent is unpatentable using
`
`Patent Owner’s construction of “unit cells.” Petitioner, however, explicitly rejects
`
`Patent Owner’s construction of “unit cells” in the Petition. See Petition at 18 (“In
`
`the pending litigation, the Patent Owner has proposed a construction of ‘logic
`
`elements of which a unit cell array is comprised’ for the term ‘unit cells.’
`
`However, this construction fails to provide clarity to the term, is inaccurate, and
`
`fails to account for the specification’s distinction between unit cells and standard
`
`cells as explained by Dr. Holberg.”) (citations omitted). Further, Petitioner applies
`
`its construction of “disposed around” to Ground 1, but relies on Patent Owner’s
`
`construction, which it also asserts is “inaccurate,” for Ground 2. See Petition at 22
`
`(citing Ex. 1003, ¶¶ 96-97; Ex. 1015, ¶¶ 58-59). “Because the Petition does not
`
`map the challenged claims, as Petitioner considers them to be correctly construed,
`
`to the asserted prior art, there is not a reasonable likelihood that Petitioner would
`
`prevail with respect to any challenged claim” of Grounds 1, 2 or 3. See Hologic,
`
`2018 Pat. App. LEXIS 5855, at *9-10.
`
`Patent Owner submits that it is not necessary for the Board to construe any
`
`of the terms proposed by Petitioner. Petitioner’s failure to prove the unpatentability
`
`of the challenged claims over the asserted references does not depend upon the
`
`construction of any term. Vivid Technologies, Inc. v. American Science, 200 F. 3d
`
`795, 803 (Fed. Cir. 2000) (“only those terms need be construed that are in
`
`-9-
`
`

`

`
`
`controversy, and only to the extent necessary to resolve the controversy.”). To the
`
`extent that a construction is necessary, Patent Owner’s claim construction positions
`
`are provided below.
`
`A.
`
`“Unit Cell.”
`
`Claim 1 claims a semiconductor integrated circuit device with five parts:
`
`transistors, unit cells, a unit cell array, a power switch, and input/output circuits.
`
`See generally Ex. 1001 at 6:45-61. The device has two types of unit cells. The first
`
`type of unit cell has a plurality of MOS transistors, each having “a first threshold
`
`voltage.” The second type also has a plurality of MOS transistors, but these
`
`transistors have “a second threshold voltage.” These two types of unit cells are
`
`arranged to form a unit cell array. See Ex. 1001 at 6:53-54. The power switch and
`
`input/output circuits are arranged around the unit cell array. See id., at 6:55-60.
`
`Figure 1 depicts one embodiment of the semiconductor integrated circuit device
`
`taught by the ’614 patent.
`
`Figure 1 shows cell array 1, unit cells 2 and 3, power switch 4, and
`
`input/output circuits 5, which make up semiconductor integrated circuit device 10
`
`(“MTCMOS”). See id., at 3:11-19. The unit cells depicted in Figure 1 are
`
`comprised of PMOS and NMOS transistors. Id., at 3:11-16. PMOS and NMOS
`
`transistors allow each unit cell to perform simple logic functions. When unit cells
`
`are grouped into a unit cell array, they allow the MTCMOS to perform more
`
`-10-
`
`

`

`
`
`complex logic functions. Thus, Aquila proposes that “unit cells” simply be
`
`construed as “logic elements of which a unit cell array is comprised.”
`
`Petitioner’s request to construe “unit cell” as a “semiconductor integrated
`
`circuits implemented by a gate array system, cannot be a conventional standard
`
`cell” is a transparent and improper effort to import a limitation from the
`
`specification into the claims. Specifically, Petitioner’s construction imports one of
`
`the stated objectives of the ’614 Patent: “[I]t is therefore an object of the present
`
`invention to implement the layout of a semiconductor integrated circuit device by a
`
`gate array system, thereby shortening a manufacturing period thereof as compared
`
`with the conventional standard cell system.” Id. at 17 (citing Ex. 1001 at 2:3-7).
`
`Petitioner’s focus on one of the stated objects of the invention is misplaced in
`
`claim construction. “The characterization of a feature as ‘an object’ or ‘another
`
`object,’ or even as a ‘principal object,’ will not always rise to the level of
`
`disclaimer.” Pacing Techs., LLC v. Garmin Int’l, Inc., 778 F.3d 1021, 1025 (Fed.
`
`Cir. 2015). Furthermore, “[a] patentee’s discussion of the shortcomings of certain
`
`techniques is not a disavowal of the use of those techniques in a manner consistent
`
`with the claimed invention.” Epistar Corp. v. ITC, 566 F.3d 1321, 1335 (Fed. Cir.
`
`2009).
`
`Petitioner also cites Figure 3 to bolster its gate array construction, which the
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`’614 Patent describes as “one example of the unit cells shown in FIG. 1 according
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`to a configuration of a semiconductor integrated circuit device of the present
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`invention.” Id. at 17-18 (citing Ex. 1001 at 3:8-11). But “[w]hen the specification
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`describes a single embodiment to enable the invention, this court will not limit
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`broader claim language to that single application ‘unless the patentee has
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`demonstrated a clear intention to limit the claim scope using words or expressions
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`of manifest exclusion or restriction.’” Abbott Labs. v. Sandoz, Inc., 566 F.3d 1282,
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`1288 (Fed. Cir. 2009) (citations and internal quotations omitted). The fact that
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`Petitioner’s cited example does not constitute “words or expressions of manifest
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`exclusion or restriction” is made clear by the next passage of the ’614 Patent cited
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`by Petitioner: “Since the layout of the MTCMOS 10 can be implemented in
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`accordance with a gate array system in the present embodiment, a manufacturing
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`period can be shortened as compared with the conventional standard cell system.”
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`Petition at 18 (citing Ex. 1001 at 3:51-54). The specification thus explains that in
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`the first embodiment, “the MTCMOS 10 can be implemented in accordance with a
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`gate array system,” not that it “is implemented” or “must be implemented.”
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`Aquila’s construction of “unit cells” as “logic elements of which a unit cell
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`array is comprised” should be adopted.
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`B.
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` “A Unit Cell Array Comprised Of Said First And Second Unit
`Cells Laid In Array Form.”
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`Petitioner asserts that the term “a unit cell array comprised of said first and
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`second unit cells laid in array form” should be construed as “a plurality of said first
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`and second unit cells laid in a regular arrangement or pattern.” Petition at 19.
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`Patent Owner submits that the term should be construed as “an arrangement of unit
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`cells, not necessarily in a regular arrangement or pattern,” because there is no
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`justification for adopting a “regular arrangement or pattern” limitation.
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`Petitioner’s construction is another attempt to limit the ’614 patent to a gate
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`array implementation. In support of its proposal, Petitioner cites a selectively
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`edited non-technical dictionary definition of “array.” Id. at 19. Petitioner does not
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`state that this definition is consistent with how a person of ordinary skill in the art
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`would understand the term, or explain why resort to extrinsic evidence is
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`necessary. See Hill-Rom Servs. v. Stryker Corp., 755 F.3d 1367, 1373 (Fed. Cir.
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`2014) (“[T]o deviate from the plain and ordinary meaning of a claim term to one of
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`skill in the art, the patentee must, with some language, indicate a clear intent to do
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`so in the patent. And there is no such language here.”). There is no clear indication
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`in the intrinsic record that the patentee intended the term “laid in array form” to be
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`limited to a “regular arrangement or pattern.” Petitioner’s construction should be
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`rejected.
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`“A Power Switch.”
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`C.
`Patent Owner contends that “a power switch” does not require construction.
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`Petitioner contends the term should be construed as “a switch including a PMOS
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`and an NMOS transistor.” Petition at 20.
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`Petitioner acknowledges that “[t]he claims do not describe whether the third
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`MOS transistors include PMOS or NMOS transistors, or both.” Petition at 20.
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`Petitioner’s expert confirms that the power switch could be implemented with only
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`PMOS or only NMOS transistors and there is nothing in the claims of the ’614
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`patent requiring both. See Holberg Decl., Ex. 1003 ¶ 88 (“The claims do not
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`describe whether the third MOS transistors include PMOS or NMOS transistors, or
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`both.”).
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`Petitioner’s use of the word “switch” in its proposed construction supports
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`Patent Owner’s position that the term “a power switch” does not require
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`construction. Petitioner agrees that a switch is a switch, but seeks to attach an
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`unsupported limitation to the term.
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`D.
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`“A Power Switch Disposed Around Said Unit Cell Array And
`Comprised Of A Plurality Of Third MOS Transistors”
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`The parties disagree how the phrase “disposed around” should be construed
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`in the term “a power switch disposed around said unit cell array and comprised of a
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`plurality of third MOS transistors.” Patent Owner contends that, consistent with the
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`phrase’s plain and ordinary meaning, the phrase should be construed as “located on
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`all sides of.” Petitioner contends that “disposed around” should be construed as
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`“encircle.” Petition 21.
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`The only evidence Petitioner cites in support of its “encircle” construction
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`are “dictionary definitions of ‘disposed’ and ‘around’ [that] describe an
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`arrangement of something that encircles another thing. Id. (citing Ex. 1031, 120
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`(defining “around”). Ex. 1003 ¶ 95; Ex. 1015 ¶ 57). Petitioner does not include the
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`definitions in its Petition and instead improperly incorporates them by reference. If
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`Petitioner had included the definition of “around” Petitioner and its expert cite it
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`would be clear that the definition does not say what Petitioner says it does.
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`According to Dr. Holberg, “Webster’s Third New International Dictionary (2002)
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`defines ‘around’ as ‘on all sides of ... so as to encircle or enclose ... about.’” Ex.
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`1003 ¶ 95. To arrive at this “definition,” Dr. Holberg omits the first definition:
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`“along the outer edge or boundary of,” and uses an ellipses to merge the next two
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`definitions “on all sides of” and “so as to encircle or enclose.” See Ex. 1031 at 120.
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`AMD’s contortions reveal its inability to find support for its proposed construction.
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`Petitioner’s reliance on a misleading presentation of extrinsic evidence,
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`which it improperly incorporates by reference, is no basis to adopt its proposed
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`“encircle” limitation.
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`E.
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`“A Plurality Of Input/Output Circuits Disposed Around Said Unit
`Cell Array”
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`The parties again dispute the meaning of “disposed around.” Patent Owner
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`argues that “disposed around” means “located on all sides,” while Petitioner
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`contends that “disposed around said unit cell array” means to “encircle said unit
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`cell array.” Petition 23.
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`In support of its proposal, Petitioner cites the same “definition” it cobbled
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`together in support of its “encircle” construction or the “power switch disposed
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`around” limitation discussed above. See id. Petitioner’s reliance on a single
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`“definition” and conclusory expert testimony, which it improperly incorporates by
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`reference, is no basis to adopt its proposed “encircle” limitation.
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`F.
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`“Parts Of Said Power Switch Disposed Within Said Unit Cell
`Array”
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`The parties dispute whether the ’614 patent requires that the “parts of said
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`power switch disposed within said unit cell array” must be third MOS transistors.
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`Petition 24. Claim 1 teaches that the power switch is “comprised of a plurality of
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`third MOS transistors,” meaning that the power switch includes, but is not limited
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`to, the plurality of third MOS transistors. See Cias, Inc. v. All. Gaming Corp., 504
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`F.3d 1356, 1360 (Fed. Cir. 2007) (“The usual and generally consistent meaning of
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`‘comprised of,’ when it is used as a transition phrase, is, like ‘comprising,’ that the
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`ensuing elements or steps are not limiting.”); see also id. (“In the patent claim
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`context the term ‘comprising’