`
`
`
`
`
`
`
`
`ANANTHA CHANDRAKASAN
`
`BORIVOJE NIKOLIC
`
`DIGITAL
`INTEGRATED CIRCUITS
`
`
`
`
`PRENTICE HALL ELECTRONICS AND VLSI SERIES
`CHARLES G. SODINI, SERiES EDITOR
`
`
`
`AQUILA - Ex. 2005
`AQUILA — EX. 2005
`
`

`

`
`
`DIGITAL
`
`INTEGRATED
`
`CIRCUITS
`
`A DESIGN PERSPECTIVE
`
`SECOND EDITION
`
`JAN M. RABAEY
`ANANTHA CHANDRAKA'SAN
`BORIVOJE NIKOLIC
`
`PRENTICE HALL ELECTRONICS AND VLSI SERIES
`CHARLES G. SODINI. SERIES EDITOR
`
`I’oau‘su'm
`
`I‘l(luti:al.it )11
`
`Pearson Education. Inc.
`
`Upper Saddle River, New Jersey 0?458
`
`and Edition
`
`
`
`

`

`‘
`
`Library of Congress Cataloging-in-Publicafion Data on file.
`
`Vice Presidenth Editorial Director. ECS: Marcia J. Horton
`Publisher: Tom Robbins
`
`Editorial Assistant: Eric Von Orrenbridge
`Vice President and Director of Production and Manufacturing, ESM: David W Riccardi
`Executive Managing Editor: Vince O'Brien
`Managing Editor: David A George
`Production Editor: Daniel Sandin
`Director of Creative Services: Paul Belfouti
`Creative Director: Carole Anson
`Art and Cover Director: Jayne Come
`Art Editor: Greg Dulles
`Manufacturing Manager: Trudy Pirciorri
`Manufacturing Buyer: Lisa McDowell
`Marketing Manager: Holly Stark
`
`l12 )< 245 in.
`About the Cover: Detail of “Wet Orange." by Joan Mitchell (American. 19254992). Oil on canvas.
`(284.5X6223 cm). Carnegie Museum of Art. Pitlsburgh. PA. Gift of Kaufmann's Department Store and the
`National Endowment for the Arts. 74.1 1. Photograph by Peter Harholdt. 1995.
`
`i’l'cnl ice
`
`”all
`-
`
`© 2003, 1996 by Pearson Education. inc.
`Pearsm Education. Inc.
`Upper Saddle River. NJ D'MSS
`
`The author and publisher of this book have used their best efforts in preparing this book. These efforts include the devel—
`opment. research. and testing of the theories and programs to determine their effectiveness. The author and publisher
`shall not be liable in any event for incidental and consequential damages in connection with. or arising out of. the fur
`nishing, performance, or use of these programs.
`
`All rights reserved. No part of this book may be reproduced. in any form or by any means.
`withorrt permission in writing from the publisher.
`
`Printed in the United States of America
`
`10
`
`9
`
`8
`
`7
`
`6
`
`ISBN 0-13-090996-3
`
`PearstJn Education Ltd., London
`Pearson Education Australia Pty. Ltd. Sydney
`Pearson Education Singapore. Pie. Ltd
`Pearson Education NOl‘ll'l Asia Ltd., Hong Kong
`Pearson Education Canada Inc... Toronto
`Pearson Educacion de Mexico. SA. de CV.
`Pearson Education—Japan, Tokyo
`Pearson Education Malaysia, Pte. Ltd.
`Pearson Education I.nc.. Upper Saddle River, New Jersey
`
`
`
`
`
`

`

`
`
`
`
`éfi .
`
`lag-[:1
`_¢-_.
`‘1-
`
`{1
`
`1:3.
`
`
`
`Contents
`
`Preface
`vii
`
`
`
`Part I
`The Fabrics
`1
`
`Chapter I
`
`Introduction
`
`1.1
`1.2
`1.3
`
`1.4
`1.5
`
`A Historical Perspective
`Issues in Digital Integrated Circuit Design
`Quality Metrics of a Digital Design
`1.3.1 Cost of an Integrated Circuit
`1.3.2
`Functionality and Robustness
`1.3.3
`Performance
`
`Power and Energy Consumption
`1.3.4
`Summary
`To Probe Further
`Reference Books
`References
`
`Chapter 2 The Manufacturing Process
`2.1
`Introduction
`
`2.2 Manufacturing CMOS Integrated Circuits
`2.2.1
`The Silicon Wafer
`2.2.2
`Photolithography
`2.2.3
`Some Recurring Process Steps
`2.2.4
`Simplified CMOS Process Flow
`
`2.3
`
`2.4
`
`2.5
`
`2.6
`
`Design Rules—The Contract between Designer
`and Process Engineer
`Packaging Integrated Circuits
`2.4.1
`Package Materials
`2.4.2
`Interconnect Levels
`
`2.4.3 Thermal Considerations in Packaging
`Perspective-flTrends in Process Technology
`2.5.1
`Short-Term Developments
`2.5.2
`In the Longer Tenn
`Summary
`
`XV
`
`3
`
`4
`6
`15
`16
`13
`27
`
`30
`31
`31
`32
`33
`
`35
`36
`
`36
`37
`3?
`41
`42
`
`4'?
`51
`52
`53
`
`59
`61
`61
`63
`64
`
`

`

`xvi
`
`Contents
`
`2.7
`
`To Probe Further
`References
`Design Methodology Insert A It: LAYOUT
`A.1
`To Probe Further
`References
`Chapter3 The Devices
`
`3.1
`3.2
`
`Introduction
`The Diode
`3.2.1 A First Glance at the Diode—The Depletion Region
`3.2.2 Static Behavior
`3.2.3 Dynamic, or Transient. Behavior
`3.2.4 The Actual Diode—-Seconda.ry Effects
`3.2.5 The SPICE Diode Model
`The MOS(FET) Transistor
`3.3.1 A First Glance at the Device
`3.3.2 The MOS Transistor under Static Couditions
`3.3.3 The Actual MOS Transistor—Some Secondaty Effects
`3.3.4 SPICE Models for the MOS Transistor
`A Word on Process Variations
`Perspective—Technology Scaling
`Summary
`To Probe Further
`References
`Design Methodology Insert B Circuit Simulation
`References
`
`3.3
`
`3.4
`3.5
`3.6
`3.7
`
`Chapter 4 The Wire
`
`
`
`64
`64
`57
`7i
`71
`73
`
`74
`74
`75
`77
`80
`84
`85
`a?
`8'?
`88
`114
`11?
`120
`122
`128
`129
`130
`131
`134
`
`135
`
`i
`
`i
`i
`I
`1
`
`i
`i
`-
`
`;
`I
`
`.
`E
`a
`=
`:
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`-
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`_-
`..._..
`Eli
`
`iii
`3:2
`f“
`%
`2g
`ii
`
`"r:
`‘2:
`'9‘
`33
`0'1
`ii
`1.5"
`1;
`43
`ii
`“-
`55
`ii
`33
`9:5
`0?
`it?
`iii
`1*
`
`a
`
`f,
`
`-
`
`037
`55%
`1'3
`4*?
`5%
`‘t‘
`
`’3.
`
`4.1
`4.2
`
`4.3
`
`4.4
`
`Introduction
`A First Glance
`
`Interconnect Parameters—Capacitance, Resistance,
`and Inductance
`4.3.1 Capacitance
`4.3.2 Resistance
`4.3.3
`Inductance
`Electrical Wire Models
`4.4.1 The Idea] Wire
`4.4.2 The Lumped Model
`4.4.3 The Lumped RC Model
`4.4.4 The Distributed rc Line
`4.4.5 The Transmission Line
`
`136
`136
`
`138
`138
`144
`148
`150
`151
`151
`152
`156
`159
`
`
`
`

`

` xvili
`
`Contents
`
`
`
`
`
`
`
`
`6.4
`
`6.5
`
`6.6
`
`6.3.3 Signal Integrity Issues in Dynamic Design
`6.3.4 Cascading Dynamic Gates
`Perspectives
`6.4.1 How to Choose a Logic Style?
`6.4.2 Designing Logic for Reduced Supply Voltages
`Summary
`To Probe Further
`References
`
`290
`295
`303
`303
`303
`306
`307
`308
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Design Methodology Insert C How to Simulate Complex
`Logic Circuits
`
`C1
`C2
`C3
`
`Representing Digital Data as a Continuous Entity
`Representing Data as 3 Discrete Entity
`Using Higher-Level Data Models
`References
`
`309
`
`310
`310
`315
`3 17
`
`Design Methodology Insert D Layout Techniques for Complex Gates 319
`
`Chapter 7 Designing Sequential Logic Circuits
`7.1
`Introduction
`
`7.2
`
`7.3
`
`7.4
`
`7.5
`
`7.6
`
`7.1.1 Timing Metrics for Sequential Circuits
`7.1.2 Classification of Memory Elements
`Static Latches and Registers
`7.2.1 The Bistabiljty Principle
`7.2.2 Multiplexer-Based Latches
`7.2.3 Master~Slave Ed gedTriggered Register
`7.2.4 Low-Voltage Static Latches
`7.2.5 Static SR Fiip—Flops—Writin g Data by Pure Force
`Dynamic Latches and Registers
`7.3.1 Dynamic Transmission~Gate Edge-triggered Registers
`7.3.2 CZMOS—A Clock-Skew Lnsensitive Approach
`7.3.3 True SingIe~Phase Clocked Register (TSPCRJ
`Alternative Register Styles‘
`7.4.1
`Pulse Registers
`7.4.2 Sense-Amplifier—Based Registers
`Pipelining: An Approach to Optimize Sequential Circuits
`7.5.1 Latch- versus Register-Based Pipelines
`7.5.2 NORA~CMOS—~A Logic Style fur Pipelined Structures
`Nonbistable Sequential Circuits
`7.6.1 The Schmitt Trigger
`7.6.2 Monostable Sequential Circuits
`7.6.3 Astable Circuits
`
`I
`
`_
`
`'
`
`‘
`
`7.7
`7.8
`
`Perspective: Choosing a Clocking Strategy
`Summary
`I
`l
`
`325
`326
`
`327
`328
`330
`330
`332
`333
`339
`341
`344
`344
`346
`350
`354
`354
`356
`358
`360
`361
`364
`364
`367
`368
`
`370
`37]
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`'h:‘\
`
`
`
`
`
`

`

`
`
`r.
`
`
`
`Contents
`
`7.9
`
`To Probe Further
`
`References
`
`xix
`
`372
`
`372
`
`
`
`
`Part 3
`A System Perspective
`375
`
`Chapter 8
`
`Implementation Strategies for Digital ICS
`8.1
`Introduction
`
`8.2
`
`8.3
`8.4
`
`8.5
`
`8.6
`8.7
`8.8
`
`From Custom to Semicustorn and Structured-Array
`Design Approaches
`Custom Circuit Design
`Cell-Based Design Methodology
`8.4.]
`Standard Cell
`8.4.2 Compiled Cells
`8.4.3 Macrocells, Megacells and Intellectual Property
`8.4.4 Semicustom Design Flow
`Array-Based Implementation Approaches
`8.5.1 Prediffused (or Mask-Piogrammabie) Arrays
`8.5.2 Prewired Arrays
`Perspective—The Implementation Platform of the Future
`Summary
`To Probe Further
`References
`
`Design Methodology Insert E Characterizing Logic
`and Sequential Cells
`
`References
`
`Design Methodology Insert F Design Synthesis
`
`References
`
`Chapter 9 Coping with Interconnect
`
`9.1
`
`9.2
`
`9.3
`
`9.4
`
`Introduction
`
`Capacitive Parasitics
`9.2.1 Capacitance and Reliability—Cross Talk
`9.2.2 Capacitance and Performance in CMOS
`Resistive Parasitics
`
`9.3.1 Resistance and Reliability—Ohmic Voltage Drop
`9.3.2 Electromigration
`9.3.3 Resistance and Performance—RC Delay
`Inductive Parasitics‘
`
`9.4.1
`9.4.2
`
`Inductance and Reliability— Voltage Drop
`Inductance and Performance—Transomsion-ljne Effects
`
`9.5
`
`Advanced Interconnect Techniques
`
`377
`378
`
`382
`383
`384
`385
`390
`392
`396
`399
`399
`404
`420
`423
`423
`424
`
`427
`
`434
`
`435
`
`443
`
`445
`
`446
`
`445
`446
`449
`460
`
`460
`462
`464
`469
`
`469
`475
`
`480
`
` mi
`
`: Contents
`
`'
`
`:t
`i
`i..-
`i:
`l
`
`i3
`
`290
`295
`303
`303
`303
`306
`
`307
`308
`
`309
`
`310
`310
`315
`317'
`
`gm 319
`'
`325
`i.
`
`326
`327
`328
`330
`330
`332
`333
`339
`341
`344
`
`344
`346
`350
`354
`354
`
`356
`358
`360
`361
`364
`364
`367
`368
`
`370
`371
`
`..
`
`s
`"
`
`_
`ts
`
`es
`
`
`
`

`

`
`
`__._..
`
`9.5.1 Reduced—Swing Circuits
`9.5.2 Current-Mode Transmission Techniques
`
`9.6
`9.7
`9.8
`
`Perspective: Networks-on-a-Chip
`Summary
`To Probe Further
`
`References
`
`Chapter 10 Timing Issues in Digital Circuits
`10.1
`Introduction
`10.2
`
`Timing Classification of Digital Systems
`10.2. 1 Synchronous Interconnect
`10.2.2 Mcsochronous interconnect
`10.2.3 Plesiochronous Interconnect
`
`10.3
`
`10.4
`
`10.5
`
`10.6
`
`10.7
`
`10.8
`10.9
`
`10.2.4 Asynchronous Interconnect
`Synchronous Design—An In-depth Perspective
`10.3.1 Synchronous Timing Basics
`10.3.2 Sources of Skew and Jitter
`
`10.3.3 Clock-Distribution Techniques
`10.3.4 Latch-Based Clocking!
`Self-Timed Circuit Design“
`10.4.1 Self-Timed Logic—An Asynchronous Technique
`10.4. 2 Completion-Si gnal Generation
`10.4.3 Self-Timed Signaling
`10.4.4 Practical Examples of Self-Timed Logic
`Synchronizers and Arbiters’
`10.5.1 Synchroniaer5+-Concept and Implementation
`10.5.2 Arbiters
`
`Clock Synthesis and Synchronization Using
`a Phase-Locked Loop‘
`10.6.1 Basic Concept
`10.6.2 Building Blocks of a PLL
`Future Directions and Perspectives
`10.7.1 Distributed Clocking Using DLLS
`10.7 .2 Optical Clock Distribution
`10.7.3 Synchronous versus Asynchronous Design
`Summary
`To Probe Further
`References
`
`Design Methodology Insert G Design Verification
`References
`
`Contents
`
`480
`486
`
`487
`488
`489
`489
`
`491
`
`492
`
`492
`492
`493
`493
`494
`495
`495
`502
`508
`516
`519
`519
`522
`526
`531
`534
`534
`538
`
`539
`540
`542
`546
`546
`548
`549
`
`550
`551
`551
`
`553
`
`557
`
`contents
`
`Chapter 1'
`
`
`
`2523432.
`
`g-Ha; new
`
`\';'-.a‘i=._""'5'-'-'-m=m_ia-'-new...
`
`
`gig..'_,._:::.:'_-_'.-fl
`
`*9
`
`
`
`

`

`
`
`
`
`
`
`
`Chapter II Designing Arithmetic Building Blocks
`1 1.1
`Introduction
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`xxi
`
`559
`
`560
`560
`561
`561
`564
`571
`
`586
`586
`587
`589
`593
`594
`
`594
`595
`596
`
`596
`600
`601
`611
`617
`
`618
`619
`620
`621
`
`623
`
`624
`625
`627
`
`634
`634
`647
`65 7
`670
`672
`672
`679
`686
`689
`689
`
`Contents
`
`11.2 Datapaths in Digital Processor Architectures
`I 1.3 The Adder
`
`11.3.1 The Binary Adder: Definitions
`11.3.2 The Full Adder: Circuit Design Considerations
`11.3.3 The. Binary Adder: Logic Design Considerations
`1 1.4 The Multiplier
`11.4.1 The Multiplier: Definitions
`11.4.2 Partial-Product Generation
`1 1.4.3 Partial-Product Accumulation
`11.4.4 Final Addition
`
`11.4.5 Multiplier Summary
`1 1.5 The Shifter
`11.5.1 Barrel Shifter
`
`11.5.2 Logarithmic Shifter
`1 1.6 Other Arithmetic Operators
`1 1.7
`Power and Speed Trade-offs in Datapath Structures“
`11.7.1 Design Time Power-Reduction Techniques
`11.7.2 Run~Time Power Management
`1 1.7.3 Reducing the Power in Standby (or Sleep) Mode
`1 1.8 PerSpective: Design as a Trade-off
`11.9 Summary
`11.10 To Probe Further
`References
`
`Chapter 12 Designing Memory and Array Structures
`12.1
`Introduction
`
`12.1. 1 Memory Classification
`12.1.2 Memory Architectures and Building Blocks
`12.2 The Memory Core
`12.2.1 Read-Only Memories
`12.2.2 Nonvolatile Read—Write Memories
`
`12.2.3 Read-Write Memories (RAM)
`12.2.4 Contents-Addressable or Associative Memory (CAM)
`12.3 Memory Peripheral Circuitry‘
`12.3.1 The Address Decoders
`
`12.3.2 Sense Amplifiers
`12.3.3 Voitage References
`12.3.4 Driverszuffers
`
`12.3.5 Timing and Control
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`

`

`xxii
`
`Contents
`
`
`
`12.4 Memory Reliability and Yield‘
`12.4.1 Signal-to-Noise Ratio
`12.4.2 Memory Yield
`12.5 Power Dissipation in Memories‘
`12.5.1 Sources of Power Dissipation in Memories
`12.5.2 Partitioning of the Memory
`12.5.3 Addressing die Active Power Dissipation
`12.5.4 Data-Retention Dissipation
`12.5.5 Summary
`
`12.6 Case Studies in Memory Design
`12.6.1 The Programmable Logic Array (PLA)
`12.6.2 A4~Mbit SRAM
`
`12.6.3 A l-Gbit NAND Flash Memory
`12.? Perspective: Semiconductor Memory Trends and Evolutions
`12.8
`Summary
`12.9 To Probe Further
`References
`
`Design Methodology Insert H Validation and Test
`of Manufactured Circuits
`
`H.1
`11.2
`
`Introduction
`Test Procedure
`
`H.3 Design for Testability
`H.3.l
`Issues in Design for Testability
`H.3.2 Ad Hoc Testing
`H.3.3 Scan—Based Test
`
`H.4
`
`11.5
`
`H.3.4 Boundary-Scan Design
`H.3.5 Built-in Self-Test (BIST)
`Test-Pattern Generation
`H.4.l Fault Models
`
`H.4.2 Automatic Test-Pattern Generation (ATPG)
`H.4.3 Fault Simulation
`To Probe Further
`
`References
`
`Problem Solutions
`
`Index
`
`693
`693
`69%
`70]
`701
`702
`202
`"104
`707
`
`707
`707
`710
`
`712
`714
`716
`71'?
`'1' 1 8
`
`721
`
`1’21
`722
`
`3’23
`723
`725
`726
`
`729
`730
`3’34
`734
`
`736
`737
`'13?
`
`73?
`
`739
`
`745
`
`16641113111:3in3
`
`ofcores???
`
`
`
`
`
`

`

`
`
`395
`
`prediction mod-
`ly means for the
`
`8.4 Cell-Based Design Methodology
`
`mbedded processors),
`ebuggers fore
`
`priatesoftwaretools (such ascompilers andd rtant because the
`
`els‘ and test benches. The latter are quite impo
`
`end user to verify that the module delivers t
`
`The design of a s
`
`els of granularity. At the
`
`the functional modules
`the application-specific
`
`ded processors; and finally,
`single die, it i
`tern functionality migrating onto a
`
`modules. embe
`onsists of a blend of design styles and
`ithin a sea of standard cells.
`
`ireless Communications
`.
`l stack for a wireless
`
`Figure 8-15 shows an integrated circuit implementin
`a is occupied by the
`tern [SilvaOl]. The majority of the are
`
`01]) and its memory
`indoor conuttunication sys
`dded microprocessor (the Tensilica Xtensa pr0cessor [Xtensa
`
`evels of the pro—
`'
`'
`lementation of the higherl
`
`f the chip‘
`the functionality o
`
`system. This processor
`
`are generate
`pliers pro-
`(:1 using module com
`toool stack {Applicatio
`
`madcally generated from a
`itself is auto
`ndor. The processor core
`mplementation.
`
`d cells for its physical i
`in Verilog, and uses stander
`tionsetcanbc
`set insttUc
`
`“soft—core" approach is that the proces
`
`exercise in reuse at different lev—
`threw; at a level higher, WE: have
`e have the embed-
`'
`‘ next. w
`
`megacells.
`s not surprising to
`riding a number 0
`
`see that a typical ASIC
`fhard or soft macrocells
`
`
`
`c w
`
`vided by the process ve
`
`even after fabrication.
`higherleveldescription
`Theadvantageofusingthe
`
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`
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`tailored to the application. and that the processor itself can easily be ported to different
`technologies and fabrication processes.
`implementing the computation—intensive parts of the protocol (MACIPHY) on the
`microprocessor w0uld require very high clock speeds and would unnecessarily increase the
`power dissipation of the chip. Fortunately, these functions are fixed and typically do not
`require a flexible implementation. Hence. they are implemented as an accelerator module in
`
`standard cells. The hard-wired implementation accomplishes the task of implementing a
`
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`
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`
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` huge number of computations at a relatively low power level and clock frequency. The
`designer ofa system on a chip is continuously faced with the challenge of deciding what is
`more desirable—after-the— fabrication flexibility versus higher performance at lower power
`levels. Fortunately, tools are emerging that help the designer to explore the overall design
`space and analyze the trade-offs in an informed fashion [SilvaO] ]. Observe also that the chip
`contains a set of U0 interfaces, as well as an embedded network module, which helps to
`orchestrate the traffic between processor and the various accelerator and U0 modules.
`
`
`
`
`
`
`The generation process of a macro module depends on the hard or soft nature of the block.
`as well as the level of design entry. In the following sections, we briefly discuss some com—
`
`
`monly: used approaches.
`
`
`8.4.4
`
`Semicustom Design Flow
`
`
`
`
`So far, we have defined the components that make up the cell-based design methodology. In this
`section. we discuss how it all comes together. Figure 8-16 details the traditional sequence of
`
`
`steps to design a semicustom circuit. The steps of what we call the design flow are enumerated
`in the figure. with a brief description of each:
`
` .
`
`1. Design Capture enters the design into the ASIC design system. A variety of methods can
`.I
`l
`be used to do so, including schematics and block diagrams; hardware description lan-
`
`-
`i
`guages (HDLs) such as VHDL, Verilog. and, more recently. C—derivatives such as Sys—
`temC; behavioral description languages followed by high-level synthesis; and imported
`intellectual property modules.
`
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`2. Logic Synthesis tools translate modules described using an HDL language into a netiist.
`Netlists of reused or generated macros can then be inserted to form the complete netlist of
`the design.
`
`3. Prelayout Simulation and Verification. The design is checked for correctness. Perfor-
`mance analysis is performed based on estimated parasitics and layout parameters. If the
`design is found to be nonfunctional, extra iterations over the design capture or the logic
`synthesis are necessary.
`4. Floor Planning. Based .on estimated module sizes, the overall outlay of the chip is cre-
`ated. The global-power and clock—distribution networks also are conceived at that time.
`
`
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`Figure 8-16 The Semicustom [or ASIC) design flow.
`
`5. Placement. The precise positioning of the cells is decided.
`6. Routing. The interconnections between the cells and blocks are wired.
`
`7. Extraction. A model of the chip is generated from the actual physical layout. including
`the precise deviCe sizes. devices parasitics. and the capacitance and resistance ofthe wires.
`8. Postlayout Simulation and Verification. The functionality and performance of the chip is
`verified in the presence of the layout parasitics. If the design is found to be lacking. itera—
`tions on the floorplanning, placement. and routing might be necessary. Very often, this
`might not solve the problem. and another round of the structural design phase might be
`necessary.
`
`9. Tape Out. Once the design is found to be meeting all design goals and functions, a binary
`file is generated containing all the information needed for mask generation. This file is
`then sent out to the ASIC vendor or foundry. This important moment in the life of a chip is
`called tripe out.
`
`While the design flow just described has served us well for many years, it was found to be
`severely lacking once technology reached the 0.25pm CMOS boundary. With design technol-
`ogy proceeding into the deep submicron region, layout parasitics—especially from the intercon—
`nect—are playing an increasingly important role. The prediction models used by the logic and
`structural synthesis tools have a hard time providing accurate estimates for these parasitics. The
`chances that the generated design meets the tinting constraints at the first try are thus very small
`(Figure 8-]?a). The designer (or design team) is then forced to go through a number of costly
`iterations of synthesis followed by layout generation until an acceptable artwork that meets the
`tinting constraints is obtained (Figure 8-17b and c). Each of these iterations may take several
`
`
`
`8.4 Celt-Based Design Methodology
`
`397
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`Design Capture
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`Chapter 8 - Implementation Strategies for Digital ICS
`
`(a) Initial design
`
`(c) Final design
`
`Figure 8—17 The timing closure process. The white lines indicate nets with timing
`violations. in each iteration of the design process, timing errors are removed by
`optimizing the logic. by insertion of butters, by constraining the placement, or by
`streamlining the routing until an error-free design is obtained [AvantiOi].
`
`number of needed iterations continues to grow with the scaling of technology. This problem,
`
`called timing closure. made it obvious that new solutions and a change in design methodology
`were required.
`
`The common answer is to create a tighter integration between the logical and physical
`
`design processes. If the logic synthesis tool, for example, also performs some part of the place—
`ment—or directs the placementflmore precise estimates of the layout parameters can be
`
`obtained. Figure 8-18 shows an example of a design environment that merges RTL synthesis
`with first-order placement and routing. The resulting netlist is then fed into an optimization tool
`that performs the detailed placement and routing, while guaranteeing the timing constraints are
`
`met. While this approach has shown to be quite successful in reducing die number of design iter-
`
`
`
`
`
`
`of iterations to reach timing closure in deep submicron.
`
`R’I‘L
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`
`Integrated synthesis place-and-route reduces the number
`
`

`

`
`
`8.5 Array-Based Implementation Approaches
`
`399
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`ations, it throws quite a challenge at the design-tool developers. With the number of parasitic
`effects increasing with every round of technology scaling, the design optimization process that
`must
`take all
`this into account becomes exponentially complex as well. As a result. other
`approaches might be required as well. In the coming chapters, we will highlight “design some
`tions" that can help to alleviate some of these problems. An example is the use of regular and
`predictable structures, both at the logical and the physical level.
`
`
`
`
`
`
`8.5 Array-Based implementation Approaches
`
`While design automation can help reduce the design time. it does not address the time spent in
`the manufacturing process. All of the design methodologies discussed thus far require a com-
`plete run through the fabrication process.’]‘his can take from three weeks to several months, and
`
`it can substantially delay the introduction of a product. Additionally, with ever-increasing mask
`costs, a dedicated process run is expensive, and product economics must determine if this is a
`viable route.
`
`Consequently, a number of alternative implementation approaches have been devised that
`
`do not require a complete run through the manufacturing process, or they avoid dedicated pro-
`cessing completely. These approaches have the advantage of having a lower NRE (nonrecurring
`expense) and are, therefore, more attractive for small series. This comes at the expense of lower
`performance, lower integration density, or higher power dissipation.
`
`8.5.1
`
`Preditfused (or Mask-Programmable) Arrays
`
`in this approach, batches of wafers containing arrays of primitive cells or transistors are manu-
`factured by the vendors and stored. All the fabrication steps needed to make transistors are stan-
`dardized and executed without regard to the final application.
`
`To transform these uncommitted wafers into an actual design, only the desired intercon-
`nections have to be added, determining the overall function of the chip with only a few metalli-
`zation steps. These layers can be designed and applied to the premanufactured wafers much
`more rapidly, reducing the turnaround time to a week or less.
`
`This approach is often called the gate-array or the sea-of-gates approach, depending on
`the style of the prediffused wafer. To illustrate the concept, consider the gate-array primitive cell
`shown in Figure 8—1951. It comprises four NMOS and four PMOS transistors, polysilicon gate
`connections, and a power and ground rail. There are two possible contact points per diffusion
`area and two potential connection points for the polysilicon strips. We can turn this cell, which
`
`does not implement any logic function so far, into a real circuit by adding some extra wires on
`the metal layer and contact holes. This is illustrated in Figure S-l9b, where the cell is turned into
`a four-input NOR gate.
`The original gate-array approach2 places the cells in rows separated by wiring channels, as
`shown in Figure 8-20a. The overall look is similar to the traditional standard~cell technique. With
`the advent of extra metallization layers, the routing channels can be eliminated, and routing can
`
`2This approach is often called the channeled gate array.
`
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`Chapter 8 - Implementation Strategies for Digital ICS
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`Polysilicon
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`lMetal
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`contact
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`NMOS
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`3.5 .
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`(a) Primitive gate—array cell
`
`(b) Programmed cell. implementing
`a four~input NOR
`
`Figure 8-19 An example of the gate-array approach.
`
`uncommitted
`‘ ceils
`
` Rows of
`
`
`
`Routing
`channel
`
`(a) Channelled
`
`(b) Channelless (or sea of gates)
`
`Figure 8-20 Gate-array architectures.
`
`be performed on top of the primitive cells—occasionally leaving a cell unused. This channelless
`architecture, also called sea ofgates (Figure 8—20b). yields an increased density. and makes it pos—
`sible to achieve integration levels of millions of gates on a single die. Another advantage of the
`sea—of—gates approach is that it customizes the contact layer between metal-l and diffusion and}
`
`or polysilicon, in centrast to the standard gate—array approach where the contacts are predefined
`(see Figure 8-193). This extra flexibility leads to a further reduction in cell size.
`
`The primary challenge when designing a gate—array (or sea—of—gates) template is to deter—
`mine the composition of the primitive cell and the size of the individual transistors. A sufficient
`number of wiring tracks must be provided to minimize the number of cells wasted to intercon—
`
`nect. The cell should be chosen so that the prefabricated transistors can be utilized to a maximal
`
`extent over a wide range of designs. For example, the configuration of Figure 8-19 is well suited
`for the realization of four—input gates, but wastes devices when implementing two-input gates.
`
`
`
`

`

`8.5 Array—Based Implementation Approaches
`
`401
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`oxide-isolation between
`gates
`
`(b) Cell using the gate-isolation
`approach and supporting
`multiple transistor Sizes
`
`
`
`
`
`
`Figure 8-21 Examples of sea-of-gates primitive cells {from [Veendrick92]}.
`
`Multiple cells are needed when implementing a flip-flop. A number of alternative cell structures
`are pictured in Figure 8—2]
`in a simplified format. In one approach. each cell contains a limited
`number of transistors (four to eight). The gates are isolated by means of oxide isolation (also
`called geometry isolation). The “dog-bone" terminations on the poly gates allow for denser rout~
`
`ing. A second approach provides long rows of transistors. all sharing the same diffusion area. In
`this architecture, it is necessary to electrically turn off some devices to provide isolation between
`neighboring gates by tying NMOS and PMOS transistors to GND and V00, respectively. This
`technique is called gore isolation. This approach wastes a number of transistors to provide the
`isolation, but provides an overall higher transistor density.
`
`Figure 8-22 shows the base cell for a gate-isolated gate array (from [Smith97]). The cell is
`one routing track wide. and contains one p-channel and one fl-Chal'lllel transistor. Also shown is a
`base cell containing all possible contact positions. There is room for 21 contacts in the vertical
`direction, which means that the cell has a height of 21 tracks.
`
`It is worth observing that the cell in Figure 8~2ib provides two rows of smaller NMOS
`
`transistors that can be connected in parallel if needed. Smaller transistors come in handy when
`implementing pass—transistor logic or memory cells. Sizing the transistors in the cells is a clear
`
`challenge. Due to the interconnect—oriented nature of the array-based design methodology, the
`propagation delay is generally dominated by the interconnect capacitance. This seems to favor
`larger device sizes that cause a larger area loss when unused. On the other hand, it is possible to
`construct larger transistors by putting several smaller devices in parallel.
`
`Mapping a logic design onto an array of cells is a largely automated process, involving
`logic synthesis folloWed by placement and muting. The quality of these tools has an enormous
`impact on the final density and performance of a sea~of~gates implementation. Utilization fac-
`
`tors in sea—of—gates structures are a strong function ofthe type of application being implemented.
`Utilization factors of nearly 100% can be obtained for regular structures such as memories. For
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`The base cell is shown on the left (from [Smith97]).
`
`other applications, utilization factors can be substantially lower (< 75%), due largely to wiring
`restrictions. Figure 8-23 shows an example of a flip-flop macrocell, implemented in a gate—
`isolated, gate-array library.
`
`
`
`

`

`
`
`Similar to the scenarios unfolding in the standard—cell arena, designers of sea-of—gate
`arrays discovered that a design with a large number of gates also has large memory needs.
`Implementing these memon cells on top of the gate-array base—cells is possible. but not very
`efficient. A more efficient approach is to set aside some area for dedicated memory modules.
`The mixing of gate arrays with fixed macros is called the embedded gate-array approach. Other
`modules such as microprocessor and microcon [rollers are also ideal candidates for embedding.
`-—-———————_—__—_—
`
`403
`
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`
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`
` 8.5 Array-Based Implementation Approaches
`
`
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`
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`
`
`
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`
`Example 8.7 Sea-of-Gates
`
`An example of a sea-of—gates implementation is showa in Figure 8-24. The array has a
`maximum capacity of 300 K. gates and is implemented in a 0.6—um CMOS technology.
`The upper left part of the array implements a memory subsystem, which results in a regu—
`lar modular layout. The rest of the array implements random logic.
`
`
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`.3
`f __———————————_—'
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`Chapter 8 o Implementation Strategies for Digital lCS
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`Design Consideration—Gate Arrays versus Standard Cells
`
`In the 1980s and 19905, when the majority of the chips were less titan 50.000 gates, design cycles often
`could be measured in weeks or a few months. The two— or three—week savings in turnaround time fora gate~
`array design was then a significant portion of the total design cycle, more than enough to offset the addi‘
`tiOnal die size. Wi