`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`________________________________
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`________________________________
`
`
`ADVANCED MICRO DEVICES, INC.
`Petitioner
`
`
`v.
`
`
`AQUILA INNOVATIONS INC.,
`Patent Owner
`
`________________________________
`
`
`
`Case No. IPR2019-01525
`Patent No. 6,239,614
`________________________________
`
`
`
`DECLARATION OF DR. STEVEN A. PRZYBYLSKI
`
`
`
`
`
`
`
`AQUILA – Ex. 2002
`
`

`

`
`
`TABLE OF CONTENTS
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`
`Page
`
`INTRODUCTION ........................................................................................... 1
`
`SUMMARY OF OPINIONS ........................................................................... 2
`
`I.
`
`II.
`
`III. QUALIFICATIONS ........................................................................................ 3
`
`IV. APPLICABLE LEGAL STANDARDS .......................................................... 5
`
`A.
`
`Burden of Proof ..................................................................................... 6
`
`B. Obviousness ........................................................................................... 6
`
`V.
`
`TECHNOLOGY BACKGROUND ................................................................. 8
`
`VI. LEVEL OF ORDINARY SKILL IN THE ART ........................................... 27
`
`VII. THE ’614 PATENT ....................................................................................... 27
`
`VIII. REFERENCES .............................................................................................. 32
`
`A. Mutoh .................................................................................................. 32
`
`B. Urano ................................................................................................... 34
`
`C. Mutoh021 ............................................................................................ 43
`
`IX. OBVIOUSNESS OF CLAIMS 1-3 OVER URANO IN VIEW OF
`MUTOH021 ................................................................................................... 48
`
`A. Motivation to Combine Urano and Mutoh021 .................................... 48
`
`B.
`
`Petitioner’s Proposed Modification Is Beyond The Level Of
`Ordinary Skill In The Art. ................................................................... 58
`
`X. OBVIOUSNESS OF CLAIMS 1-3 OVER MUTOH IN VIEW OF
`MUTOH021 ................................................................................................... 62
`
`A. Motivation To Combine Mutoh And Mutoh021 ................................. 62
`
`
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`-i-
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`

`

`
`
`
`
`B.
`
`TABLE OF CONTENTS
`(continued)
`
`Petitioner’s Proposed Modification Is Beyond The Level Of
`Ordinary Skill In The Art. ................................................................... 64
`
`XI. CONCLUSION .............................................................................................. 66
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`-ii-
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`I.
`
`INTRODUCTION
`
`1.
`
`I, Steven A. Przybylski, Ph.D., have been retained by Freitas &
`
`Weinberg LLP on behalf of Aquila Innovations Inc. (“Aquila”) as an independent
`
`expert in the field of computer memory technology in this inter partes review
`
`number IPR2019-01525 of U.S. Patent No. 6,239,614 (“the ’614 patent”).
`
`2.
`
`I understand that the ’614 patent is owned by Aquila Innovations, Inc.,
`
`which I understand has sued Advanced Micro Devices, Inc. (“AMD”) for
`
`infringement of the ’614 patent and that AMD filed the IPR petition.
`
`3.
`
`I am being compensated at my standard hourly rate for my work on this
`
`matter, including providing this declaration. My compensation is not dependent on
`
`the outcome of this inter partes review (“IPR”), the infringement litigation, or any
`
`other proceeding. The compensation I receive in this case does not in any way
`
`affect the substance of my testimony in this declaration.
`
`4.
`
`I have no financial interest in the ’614 patent, Aquila, or any entity
`
`affiliated with Aquila. I do not stand to benefit or be harmed financially in any way
`
`by the outcome of this IPR or the infringement litigation.
`
`5.
`
`I understand that the Patent Trial and Appeal Board (“PTAB”) has
`
`ordered trial on each of the grounds AMD has asserted: That claims 1-3 of the ’614
`
`patent are obvious over Urano (Japanese Unexamined Patent H10-125878, Exhibit
`
`-1-
`
`

`

`
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`1008) in view of Mutoh021 (Japanese Patent H08-018021, Exhibit 1013); that
`
`claims 1-3 are obvious over Mutoh (Mutoh et al., “1-V Power Supply High-S peed
`
`Digital Circuit Technology with Multithreshold-Voltage CMOS,” IEEE Journal of
`
`Solid-State Circuits, Vol. 30, No. 8, 847-854 (1995), Exhibit 1005) in view of
`
`Mutoh021; and that claims 4 and 5 are obvious over Douseki (U.S. Patent No.
`
`5,486,774, Exhibit 1010) in view of Ramus (U.S. Patent No. 5,631,492, Exhibit
`
`1011).
`
`6.
`
` In preparing this declaration, I have considered the ’614 patent and its
`
`prosecution history, the AMD’s IPR petition, the declaration of Dr. Holberg in
`
`Support of Inter Partes Review of U.S. Patent No. 6,239,614 (Exhibit 1003)
`
`(“Holberg Decl.”), the prior art and references identified in the petition and Dr.
`
`Holberg’s declaration, my knowledge and expertise in the art, and any additional
`
`materials cited herein.
`
`II.
`
`SUMMARY OF OPINIONS
`
`7. Based on my review and analysis of the materials in this matter, as well
`
`as my experience and education, in my opinion the Petition fails to show that
`
`claims 1-3 of the ’614 patent should be found unpatentable.
`
`8. Based on my review and analysis of the materials in this matter, as well
`
`as my experience and education, in my opinion one of ordinary skill in the art
`
`-2-
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`

`

`
`
`would not have been motivated to combine the Urano and Mutoh021 references
`
`because no improvement would result from such a combination.
`
`9. Further, based on my review and analysis of the materials in this matter,
`
`as well as my experience and education, in my opinion one of ordinary skill in the
`
`art would not have been motivated to combine the Mutoh and Mutoh021
`
`references because no improvement would result from such a combination.
`
`III. QUALIFICATIONS
`
`10. My current curriculum vitae (“CV”) is provided as Exhibit 2003.
`
`11. I earned a Bachelor of Applied Science from the University of Toronto
`
`in 1980. I was enrolled in the Engineering Science program, completing a course
`
`of study combining the Electrical Engineer and Computer Science options.
`
`12. I earned a Masters of Science in Electrical Engineering degree and a
`
`Ph.D. in Electrical Engineering in 1982 and 1988 respectively, both from Stanford
`
`University.
`
`13. I also earned a Masters of Business Administration from the Haas
`
`School of Business at the University of California at Berkeley in 2000.
`
`14. I have extensive experience with memory semiconductor integrated
`
`circuits and the memory systems constructed of them. At Stanford, my dissertation
`
`was on the optimization of single- and multi-level cache hierarchies to maximize
`
`-3-
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`

`

`
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`system-level performance. Also at Stanford, I was a member of the core team that
`
`architected, designed, built and tested the seminal MIPS processor. I was
`
`responsible for the design of the instruction decode and control units as well as
`
`architecting the virtual memory support. I assembled and debugged the entire
`
`microprocessor design and oversaw its fabrication and testing. In 1984 and 1985, I
`
`took a leave of absence from Stanford to become a member of the founding team
`
`of MIPS Computer Systems, a startup in California that designed, built, and sold
`
`processors and computer systems. In 1989, after finishing my doctorate and brief
`
`post-doctorate at Stanford, I returned to MIPS Computer Systems. Throughout my
`
`two periods of employment at MIPS Computer Systems, I had a number of titles
`
`and worked on a variety of projects. Noteworthy were stints as processor architect,
`
`systems architect, hardware-software team liaison, and Chief Scientist of the High-
`
`End Systems group. During the second period, I also served as a Consulting
`
`Assistant Professor in the Department of Electrical Engineering at Stanford. I
`
`designed and taught an advanced graduate level course on cache and memory
`
`system design.
`
`15. In 1991, I left MIPS to become an independent consultant. In that
`
`capacity I have provided technical, strategic, marketing, and intellectual property
`
`services to a large number of clients both domestically and internationally.
`
`Between 1994 and approximately 2000, I was a leading independent analyst
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`-4-
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`

`

`
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`following, writing, and teaching about both the technical and business aspects of
`
`the DRAM industry. Overall, I have written three books and over 25 articles in the
`
`areas of memory, processors, and computer systems. In particular, I wrote and
`
`revised an 850-page book entitled “New DRAM Technologies: A Comprehensive
`
`Analysis of the New Architectures.” I have presented many lectures, classes and
`
`seminars on semiconductor memories and their memory systems, processors and
`
`computer systems. I have presented full and half-day seminars on discrete and
`
`embedded DRAMs to over 2,500 engineers, marketers, managers, and financial
`
`analysts.
`
`16. I am a member of both the Institute of Electrical and Electronics
`
`Engineers (IEEE) and the Association of Computing Machinery (ACM). In
`
`addition, in 1997 I became a registered patent agent. I am listed as the inventor on
`
`11 domestic patents and their foreign counterparts. The subject matters include
`
`memory devices, memory subsystems, networks, error detection and correction
`
`codes, processors and cache memories.
`
`IV. APPLICABLE LEGAL STANDARDS
`
`17. I will not offer opinions on principles of law because I am not an
`
`attorney. Nonetheless, I understand the following principles of patentability, and I
`
`have used these principles as a framework in arriving at my opinions stated in this
`
`declaration.
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`-5-
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`

`

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`
`
`A. Burden of Proof
`
`18. I understand that the claims in an issued patent are not presumed to be
`
`valid during an IPR, and that the petitioner has the burden to show that a patent
`
`claim is not patentable by the preponderance of the evidence.
`
`B. Obviousness
`
`19. I understand that for a patented invention to be obvious under section
`
`103 of the patent law, the challenger must identify prior art references that alone or
`
`in combination would have rendered the claimed invention obvious to one of
`
`ordinary skill in the art at the time of the invention.
`
`20. I understand that for a claim to be found obvious, every claim limitation
`
`must be found present in the combination of the prior art references.
`
`21. I understand that the factors that should be assessed in the obviousness
`
`analysis include at least: (1) the scope and content of the prior art; (2) the
`
`differences between the prior art and the claim at issue; (3) the level of ordinary
`
`skill in the art; and (4) objective evidence as indicia of nonobviousness.
`
`22. I further understand that the obviousness inquiry must guard against the
`
`use of hindsight and resist the temptation to read into the prior art the teachings of
`
`the invention in the patent at issue. Isolated elements from the prior art should not
`
`be picked and chosen and then combined using the invention as a blueprint if such
`
`-6-
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`

`

`
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`a combination would not have been obvious at the time of the invention. In other
`
`words, it is impermissible to use the patent as a template (or reason) for combining
`
`prior art references because that would be applying hindsight. The ordinary skilled
`
`artisan would have to have a reason to combine the references to create the claimed
`
`invention independent of the patent.
`
`23. It is my understanding that a reason must be shown that would have
`
`prompted a person of ordinary skill in the art to combine known elements in the
`
`fashion claimed by the patents at issue. Combinations on obviousness grounds
`
`cannot be sustained by mere conclusory statements; instead, there must be some
`
`articulated reasoning with some rational underpinning to support the legal
`
`conclusion of obviousness.
`
`24. I understand that prior art references as a whole need to be considered,
`
`including aspects that teach away from a claimed invention or that may rebut
`
`showing of obviousness.
`
`25. I understand that if a combination of two or more prior art references
`
`are used to render a claimed invention obvious, there must be a reasonable
`
`expectation of success in making or practicing the claimed invention based on their
`
`combination. I also understand that the combination cannot modify a prior art
`
`reference such that it would render a reference unsatisfactory for its intended
`
`purpose or change the principle of operation of a reference.
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`-7-
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`

`

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`
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`26. I understand that in making a determination on obviousness, one must
`
`also consider secondary considerations or objective evidence, if present, that may
`
`indicate nonobviousness. I understand that these secondary considerations help
`
`illuminate the subjective determination involved in the hypothesis used to draw the
`
`legal conclusion of obviousness based upon the first three obviousness inquiries.
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`27. I have not considered objective evidence of nonobviousness in this
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`case.
`
`V. TECHNOLOGY BACKGROUND
`
`28. The ’614 patent involves the design of digital integrated circuits using
`
`low-threshold voltage transistors so that they can be operated with a very low
`
`supply voltage without suffering from the substantial power consumption resulting
`
`from leakage current through those low threshold voltage transistors. Ex. 1001 at
`
`1:6-12.
`
`29. Integrated circuits are created using several layers on a semiconductor
`
`wafer. Ex. 2004 at 18. The wafers are cut up into individual die that are
`
`subsequently packaged. Some of the layers cooperatively form transistors and
`
`others form the wires that interconnect the transistors to form circuits. The layers
`
`that form the MOS transistors are in or directly on the wafer, and the layers that
`
`interconnect the transistors are physically above the transistors.
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`-8-
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`

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`30. These layers are depicted together on layout diagrams through the use
`
`of transparency and cross hatching. Ex. 1001 at Figure 5. For example, a small
`
`portion on an integrated circuit is shown in Figure 5 of the ’614 patent.
`
`
`
`Ex. 1001 at Figure 5, 4:39-58; See also Ex. 2005 at 400; Ex. 2007 at 46-2.
`
`31. This diagram shows 5 different layers, four of which form, in this
`
`example, four transistors connected as two pairs in these base levels. One transistor
`
`is formed between source and drain regions 56 and 57 on one level called diffusion
`
`and controlled by a gate electrode 54 on another layer. Ex. 1001 at 4:39-58. In this
`
`example, the hash marks indicate a level of metal physically above the transistor
`
`-9-
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`

`

`
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`levels. Items 60, 61, 70, and 71 illustrate 4 wires all on one level, which is typically
`
`called Metal 1 or something comparable. See Ex. 2004 at 15; Ex. 1005 at 852; Ex.
`
`1008 at 0015, ¶ 0002, 0005; Ex. 1013 ¶ 0025. “Contacts”, such as items 62 and 72
`
`are vertical connections between the transistor layers and the first metal layer.
`
`When there are two or more levels of metal, vias (sometimes called though-hole
`
`connections) connect to Metal 1 at a lower level to Metal 2 at a higher level. Ex.
`
`1013 ¶ 25; Ex. 2007 at 46-3. The lowest levels that make up the transistors are call
`
`the front-end of the process; the metallization layers are called the back end. These
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`names come from the conceptual layout of a semiconductor manufacturing line, in
`
`which the lowest layers are manufactured first, followed by the layering of the
`
`metallization layers on top of them.
`
`32. Though the gate and diffusion layers conduct signals and are
`
`occasionally used to convey signals short distances, the intrinsic resistance of these
`
`layers means that only the metal layers are useful for longer distant
`
`interconnections. Ex. 1013 at Figure 4.
`
`33. In the fabrication of the integrated circuits, one or more masks are
`
`needed to define the regions of each layer. These masks are very expensive to
`
`create. Mask creation can take weeks, which adds to the weeks of processing time
`
`to result in a lead time from design completion to packaged device that is often
`
`measured in months. These temporal and monetary costs are greater for integrated
`
`-10-
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`

`

`
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`circuits created with more layers compared with simpler ones with fewer layers.
`
`Ex. 2004 at 1; Ex. 2005 at 399; Ex. 2007 at 46-1.
`
`34. An important property of a MOS transistor is its threshold voltage. In a
`
`nutshell, it is indicative of the voltage that must be applied to the gate electrode of
`
`the transistor. Logic circuits made with transistors with lower threshold voltages
`
`can be faster, but there is a cost of additional leakage current (current passing
`
`through the transistors from source to drain) even when the transistor is off and
`
`that leakage current is supposed to be zero. This increased leakage current
`
`translates to increased power consumption, even when the device is not doing
`
`useful work. Ex. 1001 at 1:7-33, 3:7-22. The idea behind MTCMOS (multi-
`
`threshold CMOS) is to fabricate the integrated circuits with two varieties of
`
`transistors: one set with a higher threshold voltages and lower leakage currents,
`
`and another set with lower threshold voltages. This allows for both high speed (and
`
`high leakage) circuitry and lower speed/low leakage circuitry. In order to manage
`
`the wasted power of the former, power switches are included that can isolate and
`
`turn off chunks of low-Vt logic when they are not in use. Ex. 1001 at 1:14-50; Ex.
`
`1005 at 847, 848-849.
`
`-11-
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`

`

`
`
`
`
`
`Ex. 1001 at Figure 3.
`
`35. The design of digital integrated circuit have two different phases or
`
`aspects: the logic design, and the physical design. Logic design progresses from a
`
`high-level or behavioral representation to a logic representation of the design. Ex.
`
`2004 at 6-11. The physical design phase is all about translating that logic
`
`representation into the rectangles that represent regions on each of the masks that
`
`become areas of each level of the physical stack. Ex. 2004 at 11-17; Ex. 2005 at
`
`400; Ex. 2007 at 46-3 – 46-5.
`
`36. There are several unique design styles for circuit design, “full custom”,
`
`“standard cell”, and “gate array” are among them. They offer different tradeoffs for
`
`how much and what effort is applied to the physical design aspect of IC design and
`
`what the resulting performance and cost of the resulting IC is going to be. In full
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`-12-
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`

`

`
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`custom design, generally speaking, every transistor and wire is laid out (i.e. had its
`
`rectangles on each relevant layer) by hand. In “standard cell” and “gate array”
`
`design styles, libraries of commonly used functions are designed by hand and then
`
`software Computer Aided Design (CAD) tools are used to translate the logical
`
`design into the physical design that will be ultimately fabricated. In these two
`
`design styles, the development of the libraries and their associated architecture and
`
`infrastructure, and the development of the logic design and the mapping of that
`
`logic design onto the library are performed by two separate groups of engineers
`
`with different skills and concerns, often working in different companies. Ex. 2004
`
`at 11-17; Ex. 2005 at 400-401; Ex. 2006 at 543-547; Ex. 2007 at 46-1, 46-3.
`
`37. The library of cells and the architecture of how they are to be assembled
`
`together into larger structure are designed by the engineers at a semiconductor
`
`manufacturer for use by all of their customers. Ex. 2004 at 11. These library cells
`
`are intended to be used in many different integrated circuits, thus their generic
`
`characteristics. These are the Lego blocks that creative logic designers can build
`
`into any number of integrated circuits. The logic designers, typically employed by
`
`a systems company, design in a high level language that describe a specific logic
`
`block or IC. Ex. 2004 at 9-11. CAD tools translate those high level representations
`
`of that logic into collections of interconnected library cells. Subsequent stages of
`
`the translation process arrange the physical representation of those library cells
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`-13-
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`

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`
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`according to the rules specified by the library design team, and then interconnect
`
`them, laying out the wires that turn a collection of library cells into a complete and
`
`useful circuit. Ex. 2004 at 12-15. For both these design styles, once the library is
`
`complete and made available to the customers of the semiconductor manufacturer,
`
`all significant aspects of the architecture of the physical design are frozen and not
`
`changeable by the logic design team. This is because these aspects of the design,
`
`including power distribution, are engineered to ensure proper operation across a
`
`wide range of process and environmental conditions. The down-stream logic
`
`design team simply does not have full access to the myriad parameters that go in
`
`those decisions. Ex. 2006 at 547; Ex. 2007 at 46-4, 46-5.
`
`38. In a standard cell design style, all the cells in the library are the same
`
`height. Their physical design is constrained so that they share power and
`
`sometimes clocks through abutment. Ex. 2004 at 11-15. The rows of standard cell
`
`design are separated by wiring channels (also called routing channels)1. These
`
`
`1 That the figures of Urano and Mutoh021 do not show the wiring channels does
`
`not mean they are not there. There is a design style without wiring channels, called
`
`“Sea Of Gates”, but Urano and Mutoh021 do not disclose Sea Of Gates
`
`implementations. That style of IC design is beyond the scope of this matter. Ex.
`
`1034 at 409; Ex. 2005 at 400; Ex. 2007 at 46-1.
`
`-14-
`
`

`

`
`
`allow any input or output of any cell to be connected to any input or output of any
`
`other cell in the same row of cells or the adjacent row. Ex. 2004 at 15. These
`
`wiring channels typically use two levels of metal, one used for left-to-right traces,
`
`and the other for top-to-bottom traces. Ex. 2004 at Figure 1.11.
`
`Ex. 1005 at Figure 8.
`
`
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`-15-
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`

`

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`
`
`Ex. 2004 at Figure 1.11.
`
`39. The selection of which cells go where is made by the place and route
`
`software (sometimes said to include floorplanning) that is run by the logic design
`
`team. But since each cell is unique in all layers of the fabrication process, from a
`
`fabrication perspective, a standard cell design is similar to a full-custom design:
`
`any significant change in the design will impact all the layers. Ex. 2005 at 397.
`
`40. Gate arrays are different in a couple of important ways. In a gate array,
`
`the library cells fall into a small number of groups (sometime just one group),
`
`wherein all the cells in the group are identical in front end (i.e. the lowest)
`
`fabrication layers. This facilitates a single base-level design that can be customized
`
`with metallization only for form any number of different ICs. Ex. 1008 ¶ 0007; Ex.
`
`2005 at 399; Ex. 2006 at 547.
`
`-16-
`
`

`

`
`
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`41. This relationship between the uncustomized base unit cell and the set of
`
`library cells that derive from the same base cell is explained well in Urano. Ex.
`
`1008 ¶ 0001-0006, In Urano, basic cell 31 has only pairs of transistors and
`
`comprises only front-end layers: wells, diffusion and polysilicon. Ex. 1008 ¶ 0002.
`
`Each basic cell 31 can be customized to form a switched power NAND gate 33
`
`(denoted 31(33)), an unswitched power NAND gate using high Vt transistors
`
`31(38), a switched power NAND gate using high Vt transistors 31(38') a power
`
`switch 31(34), or a combination of power switch and a switched power NAND
`
`gate 31(37). Ex 1008 at Figure 2, 3, 13, 14, 4, 6. Many other customizations of
`
`each basic cells of Urano and the other references disclosing gate arrays are
`
`possible. Each of these library cells 31(33), 31(38), 31(38'), 31(34), and 31(37) can
`
`be made by customizing a type 31 basic cell without any impact to the lower
`
`layers. See also Ex. 2004 at 19; Ex. 2005 at 399.
`
`-17-
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`

`

`
`
`
`[a]:
`
`31 [33}
`
`‘/
`
`I .17 Customizatmn nfa gate—cell.
`
`Fig I
`
`If! Example 053 gal: cell In a gate array.
`
`Fig.
`
`
`
`Ex. 2004 at 19.
`
`-18-
`
`Ex. 1008 at Figures 2 and 3, page 0016.
`
`
`
`Mflal Inlcmunnccuons added
`
`a..l—E-—'-
`
`Puma
`[1‘lr-_.‘|.‘1..:\."_
`.
`
`_
`
`I—
`
`

`

`
`
`
`42. The first phase of the design of a gate array then includes not only the
`
`design of the uncustomized base cells and how they would be customized to form
`
`useful sub-circuits, but also the design of the cell array (including the number and
`
`composition of the rows of base cells and the wiring channels) and of the power
`
`distribution. Ex. 2004 at 19; Ex. 2005 at 400-401; Ex. 1008 at 0006.
`
`43. The principal advantages, therefore, of gate arrays stem from the ability
`
`to inventory wafers of die completed up to and including the fabrication of the
`
`transistors. In other words, fabrication is completed up to the boundary between
`
`the front end and the back end. Devices inventoried at this stage can become any
`
`design from any customer that is designed to the same base IC. What remains is
`
`the back-end metallization, which facilitates customization and interconnection of
`
`the base cells and the interconnection of all the cells into a functioning circuit. Ex.
`
`1001 at 2:3-13; Ex. 2004 at 20. Ex. 2005 at 399; Ex. 2006 at 547; Ex. 2007 at 46-1,
`
`46-4.
`
`44. This advantage is only possible if the second phase of the gate array
`
`design process--the mapping of a logic design onto the cell array--does not modify
`
`in any way any of the front-end layers. In other words, the placement and size and
`
`threshold voltage of all the transistors in the IC cannot be determined by the logic
`
`design process.
`
`-19-
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`
`
`45. This inventorying of partially completed gate arrays has two principal
`
`impacts: in the design and debug phase of a project, this means that once the logic
`
`design has been completed, first silicon is generally available substantially sooner
`
`than if all of the steps are unique to the design in question. This yields a significant
`
`improvement in time-to-market over full custom or standard cell designs. In
`
`addition, since the masks needed in the fabrication process as very expensive, the
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`total development cost of a design is significantly reduced. The second principal
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`impact occurs once a design is in production, that the lead time from an order to
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`shipment of an integrated circuit is reduced, the supply chain becomes much more
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`responsive to changes in demand in the final end-user product. Ex. 1001 at 3:46-
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`50; Ex. 2005 at 399; Ex. 2007 at 46-1.
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`46. Both of these advantages are increased with a MTCMOS process
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`because these processes have additional front end steps required to fabricated
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`transistors of two different threshold voltages. Ex. 1005 at 850, 852.
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`47. As noted above, the metal layers are critical because they are used to
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`convey both power (VDD and GND) and to interconnect logic elements into a
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`larger functional circuit. As seen in the ’614, Urano, Mutoh021, Mutoh and a host
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`of other references, in gate array and standard cell designs, one level of metal is
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`used to convey power and/or switched power along the rows of logic cells. Two
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`levels of metal are common in these types of designs because two levels of metal
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`-20-
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`are needed to implement the interconnections in the wiring channels (see Supra ¶
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`38). A second level of metal is also needed at the ends of the rows to feed both
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`power and ground into the rows. A second level of metal is also often useful to
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`complete the local interconnect within the logic cells. Additional levels of metal
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`are possible but they add cost and fabrication time. Since none of the principal
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`references cited by the Petitioner in the presented challenges, any further
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`discussion of more than two levels of metal is beyond the scope of this matter. Ex.
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`1005 at 852; Ex. 1008 ¶ 0005; Ex.1013 ¶ 0025.
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`48. For example, in Urano’s figures, Metal 1 is shown as a solid black line.
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`Metal 2 is shown as a dashed line. Hollow squares show the vertical connections
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`between Metal 1 and either diffusion or gate material; Solid circles show the
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`vertical connections between Metal 1 and Metal 2. Urano uses Metal 1 for local
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`interconnect in the customization of the unit cells and for the horizontal
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`communication of switched and unswitched power (VDD and VDDV) and ground
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`(GND and GNDV) down the rows of the unit cell array. Ex. 1008 at Figure 12 on
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`0019. Metal 1 is also used to connect adjacent or near-adjacent unit cells. Ex. 1008
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`at Figure 23. Urano uses Metal 2 for the some local, intra unit cell customization
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`connected that cannot be accomplished in Metal 1. EX. 1008 at Figure 13 on 0019.
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`-21-
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`Ex. 1008 at Figure 13 on page 0019.
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`49. Urano is silent on the use of metal in the wiring channel (except for the
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`embodiment of a memory made out of gate array cells (Ex. 1008 at Figure 39), but
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`a POSITA would understand that the metallization usage depicted is consistent
`
`with the use of Metal 1 for left-to-right signal traces along the wiring channels and
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`Metal 2 being used for connected those top-to-bottom traces vertically into the
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`customized unit cells. Ex. 1008 at Figure 14 and 23. Urano is also silent about the
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`use of Metal 1 and Metal 2 to convey power, ground and signals from the pad ring
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`to the ends of the unit cell array, feeding unswitched power into the rows of unit
`
`-22-
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`
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`cells. There is no suggestion however that switched power is shared among the
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`rows or globally generated. Each row or each portion of each row or each unit cell
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`generates its own switched power. Ex. 1008 at Figure 5, 30.
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`50. Mutoh021 discloses a similar use of the two levels of metallization
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`disclosed. The un-customized, basic cells are shown Figure 2 and 3. Ex. 1013 at
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`Figures 2 and 3. They consist of two pair and one pair of transistors respectively.
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`The Type 2 basic cells of Figure 2 can be customized using Metal 1 to form a two-
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`input NAND gate or a 2-input NOR gate. Ex. 1013 at Figure 4. In this Figure, the
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`Metal 1 traces are similarly shown with solid black lines. The vertical connections
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`between Metal 1 and the source or gate material of the transistors is shown with
`
`solid circles. Metal 2 traces are shown with dashed lines and the vertical
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`connections between Metal 1 and Metal 2 are shown by open squares. Ex. 1013 at
`
`Figure 4. Here the connection points to the customized basic cells are provided at
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`the top and bottom edges of the rows of cells in Metal 1. Though not shown, a
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`POSITA would infer then that the wiring channels use Metal 2 for left-right. The
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`embodiment Figures 1, 4, and 5 shows that VDD is routed top-to-bottom in Metal
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`2, connecting all the cells 3D with the unswitched supply VDD.
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`-23-
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`
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`Ex. 1013 at Figure 4.
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`51. Mutoh discloses the internal structure for a standard cell array. Ex. 1005
`
`at Figure 8. Unlike the figures of Urano and Mutoh021, this figure shows the
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`wiring channels between the rows of circuitry. It also shows clearly that common
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`unswitched and the switched power supply and ground nodes are connected north-
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`south between all of the rows. Mutoh discloses that the power supply switching
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`cells are placed on both ends of the rows of logic cells. Ex. 1005 at 850. Mutoh
`
`does not discuss how Metal 1 and Metal 2 are used within the rows of standard
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`cells or in the wiring channels, but it is very clear that a two-level metal process
`
`was used. Ex. 1005 at 852.
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`-24-
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`
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`Ex. 1005 at Figure 8.
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`52. In sum, Urano, Mutoh021 and Mutoh all disclose integrated circuits
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`(gate arrays or standard cells) using processes with two levels of metallization.
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`They are all characterized by rows of logic cells, separated by wiring channels. The
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`need for both levels of metallization in the wiring channels constrains the
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`distribution of power to the basic cells. The principal technique available to the
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`base design designers, as illustrated in all three of these references, was to
`
`distribute power to the basic cells solely down the length of the rows to all the
`
`logic cells in the row.
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`53. Over the decades, the speed and capabilities of integrated circuits have
`
`increased many orders of magnitude while power consumption remained the same
`
`or declined. Ex. 2004 at 2. This tremendous improvement has principally come