DOCKET NO.: 0107131-00648US3
`Filed on behalf of Intel Corporation
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`IPR2019-01200
`Petitioner’s Reply
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________________________________________
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________________________________________
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`Intel Corporation
`Petitioner
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`v.
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`VLSI Technology LLC
`Patent Owner
`
`Case IPR2019-01200
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`PETITIONER’S REPLY
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`U.S. PATENT NO. 7,247,552
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`TABLE OF CONTENTS
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`IPR2019-01200
`Petitioner’s Reply
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`2. 
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`3. 
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`4. 
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`I. 
`II. 
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`B. 
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`C. 
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`Introduction ...................................................................................................... 1 
`Argument ......................................................................................................... 3 
`A. 
`The Petition Demonstrated That Oda Alone, and Oda in Combination
`With Owada, Teach An Interconnect Layer Not Being Electrically
`Connected To The First Bond Pad and Used For Wiring Or
`Interconnect Other Than Directly To The First Bond Pad.................... 3 
`1. 
`Oda Teaches an Interconnect Layer That is Not Being
`Electrically Connected To The First Bond Pad and Used For
`Wiring Or Interconnect Other Than Directly To The First Bond
`Pad. .............................................................................................. 3 
`Owada Teaches an Interconnect Layer That is Not Being
`Electrically Connected To The First Bond Pad and Used For
`Wiring Or Interconnect Other Than Directly To The First Bond
`Pad. .............................................................................................. 8 
`The Petition Demonstrated that Oda, Cwynar, and Owada All Teach
`an Interconnect Layer “Underlying The Bond Pad” That Is “Used For
`Wiring Or Interconnect” And Has “Dummy Metal Lines.” ............... 18 
`1. 
`Oda Teaches Dummy Patterns Including Lines. ...................... 18 
`2. 
`Oda Teaches Interconnect Layer That Is “Used For Wiring Or
`Interconnect Other Than Directly To The First Bond Pad” And
`Has “Dummy Metal Lines.” ..................................................... 22 
`It Would Have Been Obvious To Combine Oda With Cwynar.
` ................................................................................................... 22 
`Oda and Owada Show An Interconnect Layer “Used For
`Wiring Or Interconnect Other Than Directly To The First Bond
`Pad” And Has “Dummy Metal Lines.” ..................................... 23 
`The Petition Demonstrated that Oda and Owada Both Teach
`Integrated Circuits with a “Force Region.” ......................................... 23 
`III.  Conclusion ..................................................................................................... 30 
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`i
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`INTRODUCTION
`The Petition provides a straightforward case for obviousness of challenged
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`Petitioner’s Reply
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`I.
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`claim 11 of the ’552 patent in view of Oda, Cwynar, Reddy, Owada, and Vuong.
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`The Patent Owner’s Response (“POR”) presents an assortment of arguments in
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`response, none of which have merit. The arguments raised in the POR (1) ignore
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`the explicit teachings of the prior art, (2) narrowly interpret certain claim terms,
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`and/or (3) are contradicted by the intrinsic evidence and PO’s own expert, Dr.
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`Neikirk.
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`First, Patent Owner (“PO”) argues that Oda allegedly fails to teach an
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`interconnect layer “used for wiring or other interconnect other than directly to the
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`first bond pad.” PO, however, ignores the simple fact that Oda teaches two
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`alternative uses for the lower copper layer 200—one as an active circuit
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`interconnect that interconnects semiconductor elements below it, and another as a
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`dummy pattern. There is nothing inconsistent about these alternative uses of the
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`lower copper layer 200, and Oda’s disclosure of the first alternative plainly teaches
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`an interconnect layer “used for wiring or other interconnect other than directly to
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`the first bond pad.” In discussing the first alternative, Oda further teaches that
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`layer 200 can be used as an active circuit interconnect precisely because it is
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`insulated from the upper copper layers and bond pad above. Accordingly, Oda
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`1
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`teaches an interconnect layer “used for wiring or other interconnect other than
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`Petitioner’s Reply
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`directly to the first bond pad.” Owada likewise teaches this limitation as further
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`detailed below.
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`Second, PO contends that a person of ordinary skill in the art (“POSA”)
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`would not have understood that the dummy metal “patterns” in Oda could include
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`metal “lines,” or that a POSA would have been motivated to combine Oda with
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`Owada and Cwynar for this limitation (which both indisputably do disclose active
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`and dummy metal lines). But PO’s expert Dr. Neikirk admitted both that “lines”
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`are one of the most common forms of patterns in circuit interconnects, and further
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`that Oda discloses dummy metal lines. Ex. 1229 [Neikirk Dep.], 39:22-40:5;
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`84:22-85:2. PO further argues that the alleged “Manhattan rules,” which
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`supposedly require metal lines to run in only one direction, would have prohibited
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`replacing a two-dimensional dummy pattern with metal lines (running in only one
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`direction). However, Dr. Neikirk conceded that the Manhattan rules are not
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`applicable in the context of the ’552 patent, because the metal lines (including
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`dummy lines) disclosed in the ’552 patent run in two, orthogonal directions on the
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`same layer.
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`Lastly, PO seeks to interpret the phrase “die attach”—which appears only in
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`the construction of “force region”—as limited to the step of adding an adhesive on
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`2
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`the opposite side of the die from where electrical wire bond connections to the
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`bond pad are being made. This “construction of a construction” is an attempt to
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`effectively exclude a die attach that uses a wire bonding process from the scope of
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`the claims of the ’552 patent. However, PO’s argument is contradicted by:
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` the ’552 patent specification (which (1) specifically contemplated a
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`“wire bonding pad” and (2) explained that the need to add dummy
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`metal lines was to mitigate stresses experienced in the interconnect
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`layers under a bond pad when carrying out electrical connections to
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`the bond pad);
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` the admissions of PO’s own expert (that forces would be exerted
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`under the bond pad during the process of electrical attachment in both
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`flip chip and wire bonding processes); and
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` the extrinsic evidence (which described the entire wire bonding
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`process that includes both electrical and adhesive attachment as a die
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`attachment method).
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`II. ARGUMENT
`A. The Petition Demonstrated That Oda Alone, and Oda in
`Combination With Owada, Teach An Interconnect Layer Not
`Being Electrically Connected To The First Bond Pad and Used
`For Wiring Or Interconnect Other Than Directly To The First
`Bond Pad.
`1. Oda Teaches an Interconnect Layer That is Not Being
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`Electrically Connected To The First Bond Pad and Used
`For Wiring Or Interconnect Other Than Directly To The
`First Bond Pad.
`Claim 11 of the ’552 patent requires developing a layout including an
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`“interconnect layer[] underlying a first bond pad” that is “not being electrically
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`connected to the first bond pad and used for wiring or interconnect other than
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`directly to the first bond pad.” Ex. 1201, Claim 11. As explained in the Petition,
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`Oda teaches that layer 200 can be used as active circuit interconnects rather than
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`as a dummy metal pattern:
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`Petition, 47-49; Ex. 1202 [Bravman Declaration], ¶¶ 106-109; Ex. 1203 [Oda], Fig.
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`2A, [0061] (“In addition, the…lower copper layer 200…may…be used as a pattern
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`1
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`for circuit interconnects.”)1. Further, it is because the layer 210 is insulated from
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`the upper layers and bond pad 130 that the layer 210 is not electrically connected
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`to the bond pad above it, and thus can be used for circuit interconnects for the
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`substrate below. Petition, 47-49; Ex. 1202, ¶¶ 106-109; Ex. 1203, Fig. 2A, [0011],
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`[0049], [0054], [0061], [0062].
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`PO argues that Oda does not teach that layer 210 is “used for wiring or other
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`interconnect,” but rather that it must be a “dummy layer,” and that the passages
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`relied upon by Petitioner suggesting otherwise “conflict” and are “inconsistent.”
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`POR, 9-12. But PO’s position is based on a misreading of Oda, which clearly
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`describes alternative uses for layer 210, including as a dummy pattern, as well as a
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`pattern for circuit interconnects. See Merck & Co. v. Biocraft Laboratories, 874
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`F.2d 804 (Fed. Cir. 1989), cert. denied, 493 U.S. 975 (1989) (a reference may be
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`relied upon for all that it would have reasonably suggested to one having ordinary
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`skill the art, including nonpreferred embodiments); see also Upsher-Smith Labs. v.
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`Pamlab, LLC, 412 F.3d 1319, 1323, (Fed. Cir. 2005) (reference disclosing optional
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`inclusion of a particular component teaches compositions that both do and do not
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`contain that component).
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`1 All emphases are added unless otherwise indicated.
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`5
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`More specifically, Oda’s description of Figure 2A (and related Figures 2B
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`and 2C) reveals that two alternative uses for lower layer 210 are taught, and they
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`are not inconsistent with each other. That description starts at paragraph [0054],
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`where Oda explains that the bottom layer 10 of Figure 2A is the “semiconductor
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`substrate” where the “semiconductor elements” (transistors, resistors, etc.) are
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`located. Ex. 1203, [0054]. There are also “circuit interconnects for
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`interconnecting these semiconductor elements” located on the substrate, and these
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`“circuit interconnects” are also “formed from conductive layers such as copper
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`layers that are formed on the same layer as either upper copper layer 100 and lower
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`copper layer 200.” Id. Thus, paragraph [0054] explains that layer 200 (including
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`layer 210) may contain “circuit interconnects” that connect semiconductor
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`elements on the substrate. Id.
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`Paragraphs [0055]-[0060] of Oda then explain that upper copper layer 100
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`and lower copper layer 200 may also contain “dummy patterns,” as further detailed
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`in Figures 2B and 2C. In Paragraph [0061], Oda then explains that the dummy
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`patterns of the lower layers can themselves also be used for the circuit
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`interconnects: “[i]n addition, the dummy pattern of lower copper layer 200 is
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`electrically insulated from upper copper layer 100, and this dummy pattern may
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`therefore be used as a pattern for circuit interconnects.” This paragraph, coming
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`6
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`after the paragraphs above, thus describes an optional alternative for the metal
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`Petitioner’s Reply
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`patterns below the bond pad—they may be dummies and/or circuit interconnects.
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`PO further argues that even if Oda’s lower layer 210 contains active circuit
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`interconnects, Petitioner has purportedly failed to show it is “not being electrically
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`connected to the first bond pad.” POR, 13-24. PO argues that it is not sufficient to
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`demonstrate that layer 210 is electrically insulated from the upper layer 100
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`connected to the bond pad because the layer 210 may purportedly be both insulated
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`and electrically connected at the same time. Id.
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`PO is wrong. The passage from paragraph [0061] quoted above does not
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`just state that layer 200 (including layer 210) “is electrically insulated” from the
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`layers and bond pad above it, but instead notes that it is because of this electrical
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`insulation that layer 200 “may therefore be used as a pattern for circuit
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`interconnects.” In other words, it is because layer 210 is insulated from and not
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`electrically connected to the upper layers and bond pad above that it may
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`independently function to electrically connect to circuit elements on the substrate
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`below. Ex. 1203, [0061]; Petition, 47-49; Ex. 1202, ¶¶ 106-109; cf. Ex. 1201,
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`1:58-61 (describing prior art structures in which the “via arrangement requires that
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`majority portions of the underlying metal layers and the bond pad are all
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`electrically connected together and thus are not functionally independent of each
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`other”); see also Ex. 1230 [Modern Dictionary of Electronics], 379 (“Insulated: …
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`Separated from other conducting surfaces by a nonconductive material offering a
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`high, permanent resistance to the passage of current and disruptive discharge.”).
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`Even PO’s own expert agrees that lower layer 200 can be used for routing
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`active circuitry. See Ex. 1229 [Neikirk Dep.], 62:6-12 (“Q If you’re going to route
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`between two transistors on the substrate, it’s more likely that you’re going to use
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`the lower layers for that, correct? A Yes. …”). Oda makes this explicit by
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`expressly teaching that layer 210 can be used for dummy patterns and for circuit
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`interconnects that electrically connect to the substrate but not to the bond pad. Ex.
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`1203, Fig. 2A, [0054]-[0061]; Petition, 47-49; Ex. 1202, ¶¶ 106-109.
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`2. Owada Teaches an Interconnect Layer That is Not Being
`Electrically Connected To The First Bond Pad and Used
`For Wiring Or Interconnect Other Than Directly To The
`First Bond Pad.
`PO also argues that Owada does not teach an interconnect layer “not being
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`electrically connected to the first bond pad and used for wiring or interconnect
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`other than directly to the first bond pad.” POR, 25-36. Here, PO appears to
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`require an even narrower and erroneous view of the term “not being electrically
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`connected” by arguing that even signal lines and power lines are electrically
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`connected to each other. As explained in the Petition, Owada teaches the inclusion
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`of active interconnect metal lines used to send “signals” that are below a bond pad
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`that is itself being used to supply “power.” Ex. 1206, 5:16-18, 7:9-15, 7:24-28;
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`Petition, 74-75; Ex. 1202, ¶¶ 170-172. The electrical potentials being carried by
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`the signal lines and the power bond pad (and the lines below it that transmit the
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`power to the substrate) must be independent of one another because, otherwise, the
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`signal lines cannot carry any information.2 That is all that the Petition needed to
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`show to demonstrate no electrical connection. Petition, 74-75; Ex. 1202, ¶¶ 170-
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`172; see also Ex. 1201, 6:3-4 (“In yet another form each of the functional lines is
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`one of a signal line or a power line.”).
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`PO does not deny that Owada shows signal lines underneath a power bond
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`pad that are electrically connected to a different bond pad (a signal bond pad). But
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`PO nonetheless argues, without any explanation, that in Owada, the “signal
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`wiring” may still be electrically connected to a separate power signal. POR, 35-36
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`2 Signal lines carry “signal” information in the form of an electric potential which
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`is different from the electric potential coming from a power supply – but if signal
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`and power are electrically connected in all instances, then there is no electrical
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`difference between them and the signal lines can no longer carry any information.
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`See Ex. 2025 [Bravman Dep], 165:1-22 (explaining differences between signal
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`lines and power lines).
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`(“[S]ignal wiring of the ECL gate (in blue) is electrically connected to each of the
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`power sources VCC, VBB, VCS, VEE, and VTT. (in red).”) (quoting Ex. 2024
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`[Neikirk Dec.], ¶¶ 50-52); see also id., 32-36. Their contentions appear to be based
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`on the argument that a signal line indirectly coupled to a power line via a resistor is
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`still electrically connected. This argument is erroneous for at least two reasons.
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`First, PO’s restrictive view of “not being electrically connected” is not
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`supported by the intrinsic evidence. Specifically, column 1 of the ’552 patent
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`explains that in the prior art, it was common to include structures under bond pads
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`that were “connected together and to the bonding pad by large arrays of vias,” and
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`that “[t]his via arrangement” requires that these structures “are all electrically
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`connected together and thus are not functionally independent of each other.” Ex.
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`1201, 1:54-61. The ’552 patent thus makes clear that components in a circuit are
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`electrically connected if they are directly connected by metal between them such
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`that they are not functionally independent. With this common-sense understanding
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`of “electrically connected,” as bolstered by the ’552 patent itself, it is clear that the
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`signal lines carrying information and the bond pad supplying power in Owada are
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`not electrically connected because, as explained above, the signal line is
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`independently functioning to carry signal rather than power.
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`10
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`Indeed, Owada explains with respect to Figure 1 (reproduced below) that
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`“solder bumps 2 consists of solder bumps 2 for supplying power sources (VEE, VTT,
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`VCC, etc.) to the internal circuits of the ECL gate array and solder bumps 2 for
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`signals, such as, for inputting of and outputting of signals.” Ex. 1206, 4:50-54. If
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`signal and power lines are indeed all “electrically connected” to one another, there
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`is no reason why separate solder bumps would be required.
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`Neither PO nor Dr. Neikirk explains why a POSA would have understood that
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`signal could be “electrically connected” to power in all instances in a circuit, and
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`such a stretched view of the term is directly contrary to its use in the ’552 patent
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`and normal parlance.
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`PO contends that Petitioner’s expert, Dr. Bravman, equivocated on whether
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`a power line can be electrically connected to a signal line. POR 32-33 (quoting Ex.
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`11
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`2025 [Bravman Dep], 165:1-22). He did not—Dr. Bravman simply explained the
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`well-known concept that signal lines and power lines are different, are functionally
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`independent, and have different physical characteristics.
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`Second, PO argues that Owada’s specific type of ECL gate array disclosed
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`may allow for signal and power supplies to be electrically connected in all
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`instances. POR, 34-36; Ex. 2024 [Neikirk Dec.], ¶¶ 50-52. But Dr. Neikirk
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`acknowledged at his deposition that signal lines and power sources are not
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`electrically connected when separated by transistors acting as switches that are
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`turned off (Ex. 1229 [Neikirk Dep.], 47:6-19), and Owada’s signal wiring is
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`separated from power by transistors acting as switches. Specifically, the signal
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`wiring relied on by Petitioner are metal lines 7a-7d:
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`Ex. 1206, Fig. 3; id., 5:22-27. This “signal wiring” exists on a “third layer” above
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`the substrate, and the wires are electrically connected on one end to a signal
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`carrying bond pad, and on the other end as input to, or output from, an ECL
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`transistor structure on the substrate below. Id. As detailed in the color-coded
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`Figure 5 of Owada supplied by Dr. Neikirk, the signals at the ECL structure on the
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`substrate used as inputs or outputs are each separated from power by a transistor
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`acting as a switch:
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`Ex. 1206, Fig. 5; Ex. 2024 [Neikirk Dec.], ¶ 50. As can be seen from this figure,
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`taking the right-most VCC and middle VBB power sources as examples, the signal
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`wiring labeled in blue and the power sources labeled in red are separated by
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`transistors acting as switches.
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`14
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`When those switches are off, the signal wirings are not electrically connected to
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`the respective power sources. Thus, when those switches are turned off, Owada
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`teaches signal lines under bond pads that are not electrically connected to the
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`power-carrying bond pads above them. Ex. 1206, Fig. 5, 5:16-18, 7:9-15, 7:24-28;
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`Petition, 74-75; Ex. 1202, ¶¶ 170-172.3
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`PO further argues that a POSA would not have had a reasonable expectation
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`of success in combining Owada and Oda. POR, 27-31. PO’s argument boils down
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`3 PO and Dr. Neikirk further argue that the “resistors” shown in Owada Figure 5
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`are evidence that the signal and power lines are electrically connected. POR, 34-
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`36; Ex. 2024 [Neikirk Dec.], ¶¶ 50-52. But as explained above, there are
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`transistors between each of the inputs and output of the ECL gate array and the rest
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`of the ECL structure, that, when off, cut any electrical connection between those
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`inputs and the power source. Further, Dr. Neikirk admitted that there are power
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`sources such as VBB that are not connected to the ECL gate array via a resistor, but
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`instead by a transistor. Ex. 1229 [Neikirk Dep.], 72:7-22; see also id., 65:18-66:2
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`(acknowledging that claim 1 only requires a “single” metal line not electrically
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`connected to the first bond pad).
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`15
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`to Owada is “simply too old and too far afield.” POR, 28. But PO does not
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`dispute that Oda and Owada are actually in the same field of endeavor, both
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`articulate a need to address the problem of keeping surfaces of interconnect layers
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`planar during manufacture, and both offer a similar solution which is to add
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`dummy features to maintain a consistent metal density. See Petition, 75-82, 85-88;
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`Ex. 1202, ¶¶ 176-182, 188-193, 200-208. As PO’s expert admitted, prior art
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`dummy lines had been used in various different types of integrated circuits created
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`using different types of processes (including damascene and subtractive process).
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`Ex. 1229 [Neikirk Dep.], 77:5-78:13. Adding dummy materials works similarly
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`across these different processes to assist in keeping metal densities uniform (aiding
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`in planarity), and to add strength to layers. Petition, 85-88; Ex. 1202, ¶¶ 200-208.
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`A POSA would thus have been motivated to combine the teachings of Oda and
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`Owada. Id.4
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`4 Dr. Neikirk acknowledged that the claims of the ’552 patent are not limited to any
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`certain manufacturing process used to create the intermetal layers of the integrated
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`circuit (Ex. 1229 [Neikirk Dep.], 128:13-20), nor are they limited to the type of
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`metal that can be included in the metal layers (id., 77:5-78:13). See POR, 28-31.
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`PO also argues that Oda does not purportedly address the problem of
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`“planarity” like Owada does. POR, 28-31. While it is true that Oda does not use
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`the term “planarity,” Oda does address the problem of planarity, and PO admits as
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`much by conceding that Oda uses the “related” term “dishing” (i.e., shaped like a
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`concave or convex non-planar “dish”). POR, 31; Ex. 1203, [0057]. Specifically,
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`Oda teaches that metals in the metal interconnect layers should be kept “uniform”
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`with a ratio not greater than 95% “to prevent dishing during the CMP (Chemical
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`Mechanical Polishing) processing of the copper layer.” Ex. 1203, [0057]. A
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`POSA would have understood that Oda is thus solving the well-known planarity
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`problem by keeping metal layers uniform and within prescribed percentage levels.
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`See Petition, 75-82, 85-88; Ex. 1202, ¶¶ 176-182, 188-193, 200-208. Indeed, Dr.
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`Neikirk admitted that the need to stay within metal density requirements to assist
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`with polishing in the CMP process was both disclosed in Oda and “a well-known
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`thing.” Ex. 1229 [Neikirk Dep.], 133:20-134:3.5 Thus, because they are
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`5 Further, as explained in the Petition, a POSA would have understood that dummy
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`lines that aid in planarity also provide extra shock resistance, and would have thus
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`looked to references such as Owada and Cwynar for that reason as well. Petition,
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`59, 77-78.
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`addressing and solving the same problem, a POSA would be motivated to combine
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`Oda and Owada.
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`B.
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`The Petition Demonstrated that Oda, Cwynar, and Owada All
`Teach an Interconnect Layer “Underlying The Bond Pad” That Is
`“Used For Wiring Or Interconnect” And Has “Dummy Metal
`Lines.”
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`1. Oda Teaches Dummy Patterns Including Lines.
`PO argues that “Oda teaches using two specific dummy patterns” “[r]ather
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`than teaching the use of dummy metal lines.” POR, 37. But Oda does not limit
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`itself to what its dummy patterns should look like (Ex. 1203, [0107]), and Dr.
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`Neikirk admitted that lines are a form of pattern (Ex. 1229 [Neikirk Dep.], 83:8-
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`12), and in fact are “one of the most common form of patterns in interconnect
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`circuits.” Id., 84:22-85:2. Indeed, Dr. Neikirk admitted that Oda does disclose
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`dummy metal lines:
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`Q. Would adding structural support using dummy lines
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`alleviate problems that might be associated with pressures on
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`bond pads during the wire-bonding process?
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`A. I think, in fact, that’s precisely what Oda discusses. Yes, it
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`would.
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`Id., 39:22-40:5.
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`PO further argues that a POSA would not use lines as a “pattern” in Oda
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`because lines purportedly only provide structural reinforcement in one dimension
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`when all oriented in the same direction, versus the two-dimensional dummy
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`patterns disclosed in Oda (POR, 39-42), and that the “well-known Manhattan
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`rules” dictate that “lines in a particular interconnect level[] can only run in one
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`direction.” Id., 40 (citing Ex. 2024 [Neikirk Dec.], ¶¶ 56-59). But the ’552 patent
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`itself demonstrates that the Manhattan rules need not be followed. For example, in
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`Figure 2 of the ’552 patent, line 70 is running in a different direction than the other
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`lines, such as lines 58, 66, and 68.
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`Dr. Neikirk further admitted that Figure 3 (the only figure in the ’552 patent
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`Petitioner’s Reply
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`showing dummy lines) shows “dummy lines extending both horizontally and
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`vertically,” i.e., providing support in two dimensions. Ex. 1229 [Neikirk Dep.],
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`85:16-86:2.
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`Indeed, Dr. Neikirk further admitted that Figure 3 does not follow the “Manhattan
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`rules.” Id., 89:4-90:6. Thus, PO’s arguments that Oda and Owada would not have
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`been combined because the combination would not have followed the “Manhattan
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`rules,” or that dummy lines only provide support in one dimension, are
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`inapplicable and irreconcilable with the express disclosure of the ’552 patent.6 See
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`Petitioner’s Reply
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`also Ex. 1229 [Neikirk Dep.], 110:11-111:13 (suggesting dummy metal lines can
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`provide sufficient structural support).
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`POR further argues that Oda teaches using a “uniform” pattern, and a POSA
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`would not have used dummy lines as the patterns to achieve such uniformity. POR
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`40-41. But, again, this argument is directly contradicted by the ’552 patent, which
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`explains that dummy metal should be added in such a way that “[u]niform
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`distribution of metal is also accomplished by forming the metal at a smallest metal
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`sizing and spacing permitted by design and processing constraints.” Ex. 1201,
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`5:49-52. This uniform distribution of dummy lines can be seen in Figure 3 of the
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`6 Dr. Neikirk’s declaration describes an “ideal line” that purportedly only provides
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`support in one dimension. Ex. 2024 [Neikirk Dec.], ¶ 56. However, he admitted at
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`his deposition that the lines disclosed in the ’552 patent are not “ideal lines,” and a
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`line is simply “something that is longer than it is wide and thick.” Ex. 1229
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`[Neikirk Dep.], 49:15-19. An “ideal line” would presumably have very little or no
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`width, but Dr. Neikirk admitted that the claims challenged in the Petition do not
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`“say anything about ranges of widths.” Id., 91:6-12.
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`’552 patent, as well as in Figure 3 of Owada, and Figure 4 of Cwynar. See also
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`Petition, 57-60.
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`2. Oda Teaches Interconnect Layer That Is “Used For
`Wiring Or Interconnect Other Than Directly To The First
`Bond Pad” And Has “Dummy Metal Lines.”
`PO argues that Petitioner has improperly relied on layer 200 for an
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`interconnect layer that is “used for wiring or interconnect other than directed to the
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`first bond pad” and has dummy metal lines. POR, 42-44. But that is exactly what
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`Oda teaches—Oda is explicit in multiple instances that lower layer 200, including
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`layer 210, can include both dummy and active metals. Ex. 1203, [0054]
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`(“Although not shown in FIG. 2A, … internal circuits … and circuit interconnects
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`are formed from conductive layers such as copper layers that are formed on the
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`same layer as … lower copper layer 200.”), [0055] (“The patterns of upper copper
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`layer 100 and lower copper layer 200 are referred to as ‘dummy patterns.’”). Thus,
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`Oda expressly teaches that it is not necessarily one or the other, and instead both
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`dummy and active metal lines can co-exist on the same layer. See Petition, 47-49,
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`55-60.
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`3. It Would Have Been Obvious To Combine Oda With
`Cwynar.
`PO’s arguments for why Oda would not have been combined with Cwynar
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`mirror those it makes for Oda and Owada, and fail for the same reasons: Oda and
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`Cwynar are in the same field of endeavor, both articulate a need to address the
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`Petitioner’s Reply
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`problem of keeping surfaces of interconnect layers planar during manufacture, and
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`both offer a similar solution which is to add dummy features to maintain a
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`consistent metal density. See Petition, 53-55, 57-59, 64-68; Ex. 1202, ¶¶ 117-125,
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`129-133, 145-152. For these reasons, and for the additional reasons discussed in
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`Section II.B.1 above, a POSA would be motivated to combine Oda with Cwynar.
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`Id.
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`4. Oda and Owada Show An Interconnect Layer “Used For
`Wiring Or Interconnect Other Than Directly To The First
`Bond Pad” And Has “Dummy Metal Lines.”
`PO does not dispute that Owada teaches an interconnect layer that is used for
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`wiring or interconnect other than directly to the first bond pad and has dummy
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`metal lines. See POR, 49; Petition, 74-85. Instead, for this limitation, the POR
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`merely repeats its arguments that Oda and Owada would not have been combined,
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`and otherwise do not teach the “not being electrically connected to the first bond
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`pad” limitation. PO’s arguments are unavailing for the reasons described above in
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`Section II.A.2.
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`C. The Petition Demonstrated that Oda and Owada Both Teach
`Integrated Circuits with a “Force Region.”
`Unlike PO’s POPR, the POR does not dispute that the claim limitation
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`“force region” should be construed to mean “a region within the integrated circuit
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`in which forces are exerted on the interconnect structure when a die attach is
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`Petitioner’s Reply
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`performed.” POR, 50.
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`The POR repeats, however, the arguments made in PO’s POPR that the
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`wire-bonding process disclosed in Oda is purportedly not a “die attach.” POR, 50-
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`63. PO is, in effect, attempting to construe the term “die attach” (which appears
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`only in the construction of “force region”) to exclude the act of making electrical
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`connections to the bond pad in the context of wire-bonding.
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`Rather than making arguments based on any intrinsic evidence, PO submits
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`unrelated extrinsic evidence that purportedly differentiates a “die attach” from the
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`act of making electrical connections to the bond pad in a wire-bonding process.
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`POR, 57-62. PO requests that the Board read “die attach” in the wire-bonding
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`process to encompass only the step of adding an adhesive on the opposite side of
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`the die from where the electrical connections are being made (i.e., the side that
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`does not have any bond pads). Id. As previously explained in Petitioner’s Reply
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`to the POPR, PO’s arguments are contrary to both the intrinsic and extrinsic
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`evidence. See Petitioner’s Reply to POPR, 6-10.
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`First, PO’s purported interpretation of “die attach” is contrary to the
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`intrinsic evidence. PO focuses on the mechanical adhering of the back of the die to
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`the carrier, but the ’552 patent is directed to addressing stresses experienced by
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`metal interconnect layers underlying a bond pad when electrical connections are
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`Petitioner’s Reply
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`made to the bond pad:
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`A smaller bond pad region results in increased stress to the bond pad
`structure when physical connection is made to the semiconductor die.
`The bond pad structure includes a metal bond pad and an underlying
`stack of metal interconnect and dielectric laye