Petition for Inter Partes Review of U.S. Patent No. 7,247,552
`Claim 11
`IPR2019-01200
`
`
`DOCKET NO.: 0107131-00648US3
`Filed on behalf of Intel Corporation
`By: Yung-Hoon Ha, Reg. No. 56,368
`Theodoros Konstantakopoulos, Reg. No. 74,155
`Taeg Sang Cho, Reg. No. 69,618
`Calvin Walden (pro hac to be requested)
`Wilmer Cutler Pickering Hale and Dorr LLP
`7 World Trade Center
`250 Greenwich Street
`New York, New York 10007
`Email: Yung-Hoon.Ha@wilmerhale.com
` Theodoros.Konstantakopoulos@wilmerhale.com
` Tim.Cho@wilmerhale.com
` Calvin.Walden@wilmerhale.com
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________________________________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________________________________________
`Intel Corporation
`Petitioner
`
`v.
`
`VLSI Technology LLC
`Patent Owner
`___________________________________________
`
`Case IPR2019-01200
`____________________________________________
`
`PETITION FOR INTER PARTES REVIEW OF
`U.S. PATENT NO. 7,247,552
`CHALLENGING CLAIM 11
`
`
`
`
`
`
`
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,247,552
`Claim 11
`IPR2019-01200
`
`
`
`TABLE OF CONTENTS
`
`I. 
`INTRODUCTION ........................................................................................... 1 
`II.  MANDATORY NOTICES ............................................................................. 1 
`A. 
`Real Party-in-Interest ............................................................................ 1 
`B. 
`Related Matters ...................................................................................... 2 
`C. 
`Counsel .................................................................................................. 2 
`D. 
`Service Information ............................................................................... 2 
`III.  CERTIFICATION OF GROUNDS FOR STANDING .................................. 3 
`IV.  OVERVIEW OF CHALLENGE AND RELIEF REQUESTED .................... 3 
`A. 
`Prior Art Patent and Printed Publications ............................................. 3 
`B. 
`Grounds for Challenge .......................................................................... 4 
`V.  DISCRETION UNDER 35 U.S.C. § 314(A) AND § 325(D) ......................... 5 
`VI.  BRIEF DESCRIPTION OF TECHNOLOGY ................................................ 6 
`VII.  OVERVIEW OF THE ’552 PATENT ............................................................ 9 
`A.  Alleged Prior Art Problem .................................................................... 9 
`B. 
`Alleged Invention ................................................................................ 10 
`C. 
`Challenged Claim ................................................................................ 10 
`D. 
`Relevant Prosecution History .............................................................. 10 
`VIII.  OVERVIEW OF THE PRIOR ART REFERENCES ................................... 11 
`A.  Overview of Oda ................................................................................. 11 
`B. 
`Overview of Cwynar ........................................................................... 16 
`C. 
`Overview of Owada ............................................................................. 19 
`D.  Overview of Reddy ............................................................................. 23 
`Developing a Circuit Design ..................................................... 24 
` 
`Developing a Layout According to the Circuit Design ............ 25 
` 
`  Modifying the Layout ............................................................... 26 
`  Making the Integrated Circuit ................................................... 28 
`Overview of Vuong ............................................................................. 29 
`
`E. 
`
`i
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,247,552
`Claim 11
`IPR2019-01200
`
`
`IX.  CLAIM CONSTRUCTION .......................................................................... 34 
`A. 
`“force region” ...................................................................................... 35 
`LEVEL OF ORDINARY SKILL IN THE ART ........................................... 37 
`X. 
`XI.  SPECIFIC GROUNDS FOR PETITION ...................................................... 38 
`A. 
`Claim 11 is Obvious Over Oda in Combination with Cwynar
`and Reddy. ........................................................................................... 38 
`Claim 11 .................................................................................... 38 
` 
`Additional Reasons to Combine Oda, Cwynar, and
` 
`Reddy ........................................................................................ 64 
`Ground II: Claim 11 is Obvious Over Oda in Combination with
`Owada and Vuong. .............................................................................. 68 
`Claim 11 .................................................................................... 68 
` 
`Additional Reasons to Combine Oda, Owada, and Vuong ...... 85 
` 
`XII.  CONCLUSION .............................................................................................. 88 
`
`B. 
`
`ii
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,247,552
`Claim 11
`IPR2019-01200
`
`
`
`Petitioner Intel Corporation (“Intel”) respectfully requests inter partes
`
`review of claim 11 of U.S. Patent No. 7,247,552 (“the ’552 patent”) (Ex. 1201)
`
`pursuant to 35 U.S.C. §§ 311-19 and 37 C.F.R. § 42.1 et seq.
`
`I.
`
`INTRODUCTION
`The ’552 patent addresses a simple problem in integrated circuit (“IC”)
`
`manufacturing. To interconnect transistors in an IC, layers that contain both
`
`electrically-conductive metal pathways and dielectric/insulating materials are
`
`formed over a substrate. Near the top of these layers are small regions called
`
`“bond pads” that are used to connect the IC to external devices (like a circuit
`
`board). During manufacture, however, the region under the bond pad can be
`
`subjected to forces/stresses applied to that region when external connections are
`
`made.
`
`Claim 11 is directed to a method that purports to address this issue by adding
`
`“dummy” metal lines underneath the bond pad. But that basic idea was already
`
`well-known before the ’552 application was filed.
`
`II. MANDATORY NOTICES
`A. Real Party-in-Interest
`Intel Corporation (“Petitioner”) is a real party-in-interest and submits this
`
`inter partes review Petition challenging claim 11 of the ’552 patent.
`
`1
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,247,552
`Claim 11
`IPR2019-01200
`
`
`
`B. Related Matters
`VLSI Technology LLC (“Patent Owner”) has asserted the ’552 patent
`
`against Intel in VLSI Technology LLC v. Intel Corporation, No. 1:18-cv-00966-
`
`CFC (D. Del.).
`
`Petitioner has filed separate inter partes review petitions challenging claims
`
`1, 2, and 20 of the ʼ552 patent.
`
`C. Counsel
`Lead Counsel: Yung-Hoon Ha (Registration No. 56,368)
`
`Backup Counsel: Theodoros Konstantakopoulos (Registration No. 74,155),
`
`Taeg Sang Cho (Registration No. 69,618), Calvin Walden (pro hac vice to be
`
`requested).
`
`D.
`Service Information
`E-mail:
`
`
`Yung-Hoon.Ha@wilmerhale.com
`
`Theodoros.Konstantakopoulos@wilmerhale.com
`
`Tim.Cho@wilmerhale.com
`
`Calvin.Walden@wilmerhale.com
`
`Post and hand delivery: Wilmer Cutler Pickering Hale and Dorr LLP
`
`
`
`
`
`
`
`
`
`7 World Trade Center
`
`250 Greenwich Street
`
`2
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,247,552
`Claim 11
`IPR2019-01200
`
`
`
`New York, New York 10007
`
`Telephone: 212-230-8800
`
`Fax: 212-230-8888
`
`Petitioner consents to email delivery on lead and backup counsel.
`
`III. CERTIFICATION OF GROUNDS FOR STANDING
`Petitioner certifies pursuant to Rule 42.104(a) that the ’552 patent is
`
`available for inter partes review and that Petitioner is not barred or estopped from
`
`requesting an inter partes review challenging claim 11 on the grounds identified in
`
`this Petition.
`
`IV. OVERVIEW OF CHALLENGE AND RELIEF REQUESTED
`Pursuant to Rules 42.22(a)(1) and 42.104(b)(1)-(2), Petitioner challenges
`
`claim 11 of the ’552 patent.
`
`A.
`Prior Art Patent and Printed Publications
`The ’552 patent was filed on January 11, 2005, and does not claim priority
`
`to any prior applications. The following prior art references, none of which was
`
`considered during prosecution of the ’552 patent, are pertinent to the grounds of
`
`unpatentability explained below: 1
`
`
`1 The pre-AIA statutory framework applies for the ’552 patent.
`
`3
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,247,552
`Claim 11
`IPR2019-01200
`
`
`
`1.
`
`U.S. Patent Publication No. 2004/0150112 (“Oda”) (Ex. 1203), which
`
`was filed January 22, 2004, and published August 5, 2004, is prior art
`
`under at least 35 U.S.C. §§ 102(a) and (e).
`
`2.
`
`U.S. Patent Publication No. 2002/0162082 (“Cwynar”) (Ex. 1204),
`
`which was filed May 16, 2002, and published October 31, 2002, is
`
`prior art under at least 35 U.S.C. § 102(b).
`
`3.
`
`“Digital Design Flow Options,” Sagar V. Reddy, M.S. Thesis, 2001
`
`(“Reddy”) (Ex. 1205), which was made available to the public on
`
`April 15, 2002, is prior art under at least 35 U.S.C. §102(b). See Dr.
`
`Gretchen L. Hoffman’s Declaration (Ex. 1211) (discussing public
`
`availability of Ex. 1205).
`
`4.
`
`U.S. Patent No. 5,027,188 (“Owada”) (Ex. 1206), which was filed
`
`September 13, 1989, and issued June 25, 1991, is prior art under at
`
`least 35 U.S.C. § 102(b).
`
`5.
`
`U.S. Patent Publication No. US 2004/0098674 (“Vuong”) (Ex. 1207),
`
`which was filed November 19, 2002, and published May 20, 2004, is
`
`prior art under at least 35 U.S.C. §§ 102(a) and (e).
`
`B. Grounds for Challenge
`Petitioner requests cancellation of claim 11 of the ’552 patent as
`
`4
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,247,552
`Claim 11
`IPR2019-01200
`
`
`unpatentable under 35 U.S.C. § 103 in view of (1) Oda in combination with
`
`Cwynar and Reddy, and (2) Oda in combination with Owada and Vuong. This
`
`Petition, supported by the declarations of Dr. John C. Bravman (Ex. 1202) and Dr.
`
`Gretchen L. Hoffman (Ex. 1211), demonstrates a reasonable likelihood that
`
`Petitioner will prevail with respect to cancellation of the challenged claim. See 35
`
`U.S.C. § 314(a).
`
`V. DISCRETION UNDER 35 U.S.C. § 314(A) AND § 325(D)
`The ’552 patent is one of numerous patents asserted by VLSI in multiple
`
`district court jurisdictions. Patent Owner has asserted four other patents in the
`
`parallel Delaware action. Patent Owner has also asserted 16 additional patents in 4
`
`separate cases: VLSI Technology LLC v. Intel Corporation, Nos. 6-19-cv-00254, 6-
`
`19-cv-00255, 6-19-cv-00256 (W.D. Tex.) and 5-17-cv-05671 (N.D. Cal.). Intel
`
`has moved to transfer the Texas actions to Delaware, and the timing of the cases
`
`are overlapping and may need to be adjusted. Intel has diligently pursued its
`
`defenses, including the assertions of prior art, from when the complaint containing
`
`the ’552 patent was filed. Intel brings this IPR to adjudicate validity for claims
`
`that VLSI has asserted because (i) the same or substantially the same arguments
`
`made in this Petition have not been presented to the Office, (ii) there is uncertainty
`
`whether a trial in the district court would conclude before or after the trial of this
`
`5
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,247,552
`Claim 11
`IPR2019-01200
`
`
`Petition, (iii) given the complexity of the cases, the number of patents asserted, and
`
`the breadth of products accused of infringement, Intel will have a limited amount
`
`of time during trial to mount an invalidity defense; and (iv) Petitioner has been
`
`ordered to narrow its invalidity defenses, and cannot pursue in the district court
`
`litigation the defense outlined in the Petition’s Ground II, and thus is not arguing
`
`for invalidity in this forum based on the same art and arguments as in the district
`
`court. Petitioner respects the limited resources of the Board, but because this
`
`Petition presents unique issues and would be an effective and efficient alternative
`
`to the district court litigation, Petitioner requests that the Petition be granted under
`
`35 U.S.C. §§ 314(a) and 325(d). Petitioner may request additional briefing if
`
`Patent Owner urges the Board to exercise its discretion to deny this Petition under
`
`Sections 314(a) or 325(d).
`
`VI. BRIEF DESCRIPTION OF TECHNOLOGY
`In an IC, millions of tiny electronic components are formed in and over a
`
`“substrate.” For these electronic components to communicate with each other,
`
`electrically conductive pathways must interconnect them. To form these
`
`interconnects, layers that contain both electrically-conductive and
`
`dielectric/insulating materials are built over the substrate. Ex. 1202, ¶ 26.
`
`Figure 1 of the ’552 patent shows the basic arrangement:
`
`6
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,247,552
`Claim 11
`IPR2019-01200
`
`
`
`
`
`Ex. 1201, Fig. 1. Over substrate 122, a first metal interconnect layer 26 (blue
`
`circle) containing conductive materials 56, 58, 60 (blue highlighting), such as
`
`copper, is formed. These conductive materials provide pathways for electrical
`
`signals (or power) to flow, and are electrically isolated from each other by
`
`
`2 All color, annotations, and bold/italics emphases in this Petition are added.
`
`7
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,247,552
`Claim 11
`IPR2019-01200
`
`
`dielectric material 62, such as silica. Ex. 1201, 3:35-38; Ex. 1202, ¶¶ 27-28.
`
`
`
`Metal interconnect layer 26 is then polished, and interlevel dielectric layer
`
`24 (light green circle) is deposited on top of that metal layer. Vertical pathways
`
`connecting the conductive materials (e.g., 50 and 58) in different metal
`
`interconnect layers (e.g., layers 22 and 26) are formed in the interlevel dielectric
`
`layer 24 to create via 59. The process of forming alternating metal interconnect
`
`layers 22, 18, and 14 and interlevel dielectric layers 20 and 16 then repeats until
`
`all desired layers are built. Ex. 1201, 2:64-67, 3:9-10, 3:35-38, Fig. 1; Ex. 1202, ¶
`
`29.
`
`Metals in the top metal interconnect layer are often used to form bond pads
`
`32 to provide electrical connections to other external components (e.g., a circuit
`
`board). These external connections can be made by placing additional metal (e.g.,
`
`bump 28) on the bond pad 32. Ex. 1201, 3:10-12, 3:20-25; Ex. 1202, ¶ 30.
`
`In addition to these “active” metal interconnects, “dummy” filler metals can
`
`be added. These dummy metals are generally electrically “floating” (i.e., not
`
`electrically connected to other metal), but can also be physically connected to other
`
`metal structures. It was well-known that “dummy” metals can provide added
`
`structural reinforcement as well as improved planarity of the layers during
`
`fabrication (e.g., during a polishing step). Ex. 1202, ¶ 31.
`
`8
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,247,552
`Claim 11
`IPR2019-01200
`
`
`
`The method of making an IC typically includes a series of basic design
`
`phases: (1) developing a circuit design; (2) developing a layout corresponding to
`
`the circuit design; and (3) modifying the layout to comply with design rules. Long
`
`before the ’552 patent, computer aided design (“CAD”) tools were used for these
`
`design steps. Ex. 1215, 1:45-58. After completing the design phase, the IC is
`
`fabricated according to the modified layout. Ex. 1202, ¶ 32.
`
`
`
`VII. OVERVIEW OF THE ’552 PATENT
`A. Alleged Prior Art Problem
`The ’552 patent does not claim to have invented ICs that include substrates,
`
`interconnect layers, interlayer dielectrics, vias, bond pads, or conductive balls. To
`
`the contrary, it admits they were well-known in the prior art. Ex. 1201, 1:25-2:4
`
`(describing “conductive balls … to make electrical connection to a bond pad,”
`
`“structures fabricated with copper interconnect metallization and low dielectric
`
`constant (low-k) dielectrics,” “interlayer dielectrics,” and “vias” were known).
`
`According to the ’552 patent, however, shrinking die sizes and brittle dielectric
`
`materials resulted in ICs becoming more susceptible to damage due to the
`
`“increased stress … when physical connection is made to the semiconductor die.”
`
`Id., Abstract, 1:33-55; Ex. 1202, ¶ 33.
`
`9
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,247,552
`Claim 11
`IPR2019-01200
`
`
`
`B. Alleged Invention
`The ’552 patent purports to address this issue by defining a “force region”
`
`near the bond pad, and adding “dummy” metal structures to “increase the metal
`
`density of the interconnect layers.” Ex. 1201, Abstract, 4:37-56. However, (1)
`
`Oda, Cwynar and Owada all teach using “dummy” metal structures, and (2) Reddy
`
`and Vuong both teach methods for making an IC using well-known design phases.
`
`Ex. 1202, ¶¶ 34-35.
`
`C. Challenged Claim
`This Petition challenges claim 11 of the ’552 patent.
`
`D. Relevant Prosecution History
`The ’552 patent issued from U.S. Application No. 11/033,009, filed on
`
`January 11, 2005. The Examiner rejected all originally-filed claims over U.S.
`
`Patent Publication No. 2005/0082577. Ex. 1208, 3-7. In response, the applicant
`
`amended (among other things) challenged claim 11 to add the following underlined
`
`language and remove the bracketed language:
`
`wherein the layout comprises a plurality of interconnect layers
`underlying a first bond pad of the plurality of bond pads, at
`least one of the plurality of interconnect layers not being
`electrically connected to the first bond pad and used for wiring
`or interconnect other than directly to the first bond pad;
`
`defining a force region [[around and]] at least under [[a]] the
`first bond pad of the plurality of bond pads
`
`10
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,247,552
`Claim 11
`IPR2019-01200
`
`
`
`
`Ex. 1209, 5; Ex. 1202, ¶ 36.
`
`The Examiner allowed claim 11 as amended. Ex. 1210, 2; Ex. 1202, ¶ 37.
`
`VIII. OVERVIEW OF THE PRIOR ART REFERENCES
`A. Overview of Oda
`Oda identifies the same alleged problem and solution as the ’552 patent.
`
`Specifically, Oda notes that cracking can occur under the bond pad due to load
`
`applied to the bond pad when external connections are made. Ex. 1203, [0008]
`
`(“[T]he load of a needle during probing or bonding depresses the bonding pads and
`
`may cause cracks in the interlevel dielectric film that underlies the bonding
`
`pads.”); id., [0005] (“[S]tress … occurs when bonding is exerted upon passivation
`
`insulation film 740 and interlevel dielectric film 750 that underlie bonding portion
`
`735.”); Ex. 1202, ¶ 39.
`
`Oda addresses this issue by adding “dummy” metal patterns below a bond
`
`pad. This is shown in Figure 2A below:
`
`11
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,247,552
`Claim 11
`IPR2019-01200
`
`
`
`
`
`Ex. 1203, Fig. 2A. Under bond pad 130 are layers that include dummy patterns
`
`(pink rectangles in layers 110 and 120, collectively called “upper copper layer
`
`100,” and in layers 210 and 220, collectively called “lower copper layer 200”). Id.,
`
`[0050], [0052]; Ex. 1202, ¶¶ 40-41.
`
`
`
`These “dummy patterns” are added to help avoid damage resulting from
`
`stress during bonding. Ex. 1203, [0055] (“‘[D]ummy patterns’ …, rather than
`
`constituting the interconnects of internal circuits, function as dummy layers for
`
`distributing the shock applied to bonding pad 130.”); id., [0074]; Ex. 1202, ¶ 42.
`
`Oda’s Figures 2B and 2C below show the top-down view of two exemplary
`
`metal dummy patterns with dielectric material 14:
`
`12
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,247,552
`Claim 11
`IPR2019-01200
`
`
`
`
`
`
`
`Ex. 1203, Figs. 2B-2C, [0057]-[0059]. As shown by the greater amount of pink
`
`within the same given area, the metal density in Figure 2B is higher than that of
`
`Figure 2C. Ex. 1202, ¶¶ 43-44.
`
`
`
`Oda explains that “the dummy patterns … are not limited to the shapes that
`
`are shown in FIG. 2B and FIG. 2[C], and other patterns may be applied.” Ex.
`
`1203, [0107]. Oda further teaches the metal density can be controlled to be
`
`above15%, Ex. 1203, [0059], and that shock resistance improves as more metal is
`
`added. Id., [0057] (“The copper area ratio is the proportion of the area that is
`
`occupied by copper (copper-occupied area ratio), and shock resistance improves as
`
`13
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,247,552
`Claim 11
`IPR2019-01200
`
`
`this ratio increases.”). However, Oda provides an upper limit (95%) to the pattern
`
`density to avoid defects (called “dishing”) that can arise during the chemical
`
`mechanical polishing (“CMP”) step used during manufacturing. Id., [0057],
`
`[0065], [0068], [0070]; Ex. 1202, ¶¶ 44-46.
`
`Although dummy patterns are generally not used as active circuit
`
`interconnects (Ex. 1203, [0055]), Oda contemplates that metal patterns could be
`
`used as an active circuit interconnect for efficient use of space below the bond pad.
`
`Id., [0061] (“Using lower copper layer 200 as a circuit interconnect layer …
`
`enables the effective utilization of the area below bonding pad 130”). To illustrate,
`
`the first lower copper layer 210 has been colored blue to indicate use as active
`
`circuit interconnects:
`
`14
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,247,552
`Claim 11
`IPR2019-01200
`
`
`
`
`
`Id., Fig. 2A. Ex. 1202, ¶¶ 47-48.
`
`
`
`
`
`In addition, dummy patterns can co-exist in the same layer with active
`
`circuit interconnects. Ex. 1203, [0054] (“Although not shown in FIG. 2A, …
`
`internal circuits … are formed on the same layer as either of [dummy] upper
`
`copper layer 100 and lower copper layer 200….”). For example, Figure 4B shows
`
`“first lower copper interconnects 212 for circuit interconnects [being] formed on
`
`the same level as [dummy] first lower copper layer 210” below pad 132:
`
`15
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,247,552
`Claim 11
`IPR2019-01200
`
`
`
`
`
`Id., [0089], [0090]; Ex. 1202, ¶ 49.
`
`B. Overview of Cwynar
`Cwynar also teaches adding dummy fill features in an interconnect layer.”
`
`Ex. 1204, [0001]. Specifically, Cwynar teaches adding dummy lines to achieve
`
`“uniform” metal density without introducing unwanted electrical interactions.
`
`Cwynar explains that if metal density across an interconnect layer is not uniform,
`
`overpolishing can occur in the low metal density regions, leading to undesirable
`
`non-planar surfaces. Id., [0007]. Too many dummy lines, however, can result in
`
`unwanted electrical interactions between two nearby metal structures (called
`
`“parasitic capacitance”). Id., [0010] (describing attempts “for achieving a uniform
`
`density throughout the interconnect layer,” while recognizing that “[u]nnecessarily
`
`16
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,247,552
`Claim 11
`IPR2019-01200
`
`
`placing dummy fill features adds to the parasitic capacitance of the interconnect
`
`layer.”); id., [0042] (similar); Ex. 1202, ¶¶ 50-52.
`
`As shown in Figure 4 below, Cwynar divides the layout into regions 60(1)-
`
`60(N) (the squares):
`
`Ex. 1204, Fig. 4, [0026]-[0027]. [E]ach of these regions 60(1)-60(N) contain
`
`“active interconnect features 70(1)-70(N),” and “[e]ach [blue] shaded area
`
`comprises a plurality of metal lines or traces connecting the active areas in the
`
`
`
`17
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,247,552
`Claim 11
`IPR2019-01200
`
`
`semiconductor substrate 82.” Id., [0027]; Ex. 1202, ¶ 53.
`
`
`
`A “desired target” metal density is set for a region 60(N), and the metal
`
`density in each region 60(1)-60(N) is determined from the active interconnect
`
`features 70(1)-70(4) “using a layout algorithm.” Id., [0030], [0028]; Ex. 1202, ¶
`
`54.
`
`
`
`For example, “if the density of the active interconnect features 70[2] is less
`
`than 50 percent in layout region 60(2), then the density of the dummy fill features
`
`74(2) added is more than 50 percent so that the desired target density … for the
`
`layout region is once again 50 percent”3:
`
`
`3 As with areas 70(1)-70(N), Cwynar explains that “[e]ach shaded area [74(1)-
`
`74(n)] [pink] … comprises dummy metal lines or traces.” Ex. 1204, [0029]; Ex.
`
`1202, ¶ 55.
`
`18
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,247,552
`Claim 11
`IPR2019-01200
`
`
`
`
`
`Ex. 1204, [0029]-[0030], Fig. 4. Ex. 1202, ¶ 55.
`
`C. Overview of Owada
`Owada relates to problems that can arise when attaching ICs to a substrate.
`
`
`
`Ex. 1206, 1:57-2:8. As shown in Owada’s Figure 10 below, Owada explains that a
`
`defect 54 can form in a solder bump due to non-flat surfaces. As shown, two
`
`adjacent “uppermost layer wirings 50” at slightly different heights are covered
`
`with a passivation film 52, with one of the wirings 50 having an opening for the
`
`“solder base layer 53” and the solder bump 51:
`
`19
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,247,552
`Claim 11
`IPR2019-01200
`
`
`
`
`
`Ex. 1206, 3:22-30, Fig. 10. Owada explains that the uneven height can lead to
`
`“crevice A,” and “defect 54 [white] such as voids and cracks” can occur. Id.; id.,
`
`2:67-3:2; Ex. 1202, ¶¶ 64-65.
`
`To address these problems, Owada teaches adding dummy metal lines below
`
`the bond pad 6, as shown in Figure 4 below:
`
`20
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,247,552
`Claim 11
`IPR2019-01200
`
`
`
`
`
`Ex. 1206, Fig. 4. The cross-sectional view shows four metal aluminum wiring
`
`layers: first, second, third, and fourth layer Al wirings 22a-22d, 25a-25b, 7a-7e,
`
`and 3. Inter-level insulator films—first, second, and third inter-level insulator
`
`films 24, 27, and 29—separate the various metal wiring layers. Fourth layer
`
`wiring 3 (top blue layer) has electrode pad 6 with solder bump 2. Id., 6:17-7:53;
`
`Ex. 1202, ¶ 66.
`
`
`
`21
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,247,552
`Claim 11
`IPR2019-01200
`
`As shown below in Figure 3, in the third metal wiring layer, dummy metal
`
`
`
`
`lines 8 can be added in the empty regions next to active metal lines 7a-7d below
`
`solder bump 2. Ex. 1205, 5:5-46, 8:3-25.
`
`
`
`Id., Fig. 3. By adding these dummy metal lines 8, “the wiring density (inclusive of
`
`the dummy patterns) becomes higher in this region.” Id., 8:8-10. Adding such
`
`dummy metals below the solder bump 2 allows the insulating film 29 and the
`
`electrode pad 6 (not shown) to become flat. Id., 8:10-14 (“[T]he surface of the
`
`22
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,247,552
`Claim 11
`IPR2019-01200
`
`
`inter-level insulator film 29 … becomes flat, the fourth layer Al wiring 3 (the
`
`electrode pad 6) formed on the inter-level insulator film 29 is flattened.”); Ex.
`
`1202, ¶¶ 67-68.
`
`D. Overview of Reddy
`Reddy describes the process for designing an IC using well known CAD
`
`tools. Ex. 1205, 1-2. In Figure 1.1 below (modified to improve resolution), Reddy
`
`shows a “generic IC design flow” for the various design phases, which correspond
`
`to claim 11 as follows:
`
`23
`
`

`

`
`
`Petition for Inter Partes Review of U.S. Patent No. 7,247,552
`Claim 11
`IPR2019-01200
`
`
`
`Id., 1-2, Fig. 1.1 (“Design Flow is a term used to describe the various design
`
`phases of an IC design.”); Ex. 1202, ¶¶ 56, 57.
`
`
`Developing a Circuit Design
`Steps 1 to 4 of Figure 1.1 describe developing a circuit design of an IC:
`
`
`
`
`
`24
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,247,552
`Claim 11
`IPR2019-01200
`
`
`
`
`
`Ex. 1205, Fig. 1.1. Step 1 involves coming up with the idea of the IC design; steps
`
`2 and 3 involve developing a behavioral and structural description of that design;
`
`and step 4 involves creating a schematic overview of the design (including a timing
`
`analysis and simulation). Id., 2-4, Fig. 1.1; Ex. 1202, ¶ 58.
`
`
`Developing a Layout According to the Circuit Design
`Step 5 of Figure 1.1 illustrates developing a “layout” according to the circuit
`
`design:
`
`
`
`25
`
`
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,247,552
`Claim 11
`IPR2019-01200
`
`
`Ex. 1205 at 4-5, Fig. 1.1. In this context, “layout generation” refers to developing
`
`a representation of the geometric shapes of the electrical components on the
`
`substrate and the electrically conductive pathways in different metal interconnect
`
`layers and interlevel dielectric layers. As Reddy explains, “semi or fully
`
`automated [electronic design automation] tools” can be used to generate the layout.
`
`Id.; Ex. 1202, ¶ 59.
`
` Modifying the Layout
`Steps 6 and 7 involve performing a design rule check (“DRC”) and layout
`
`vs. schematic (“LVS”) check:
`
`
`
`Ex. 1205, Fig. 1.1. The LVS check “ensures that the layout is in conformance with
`
`
`
`26
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,247,552
`Claim 11
`IPR2019-01200
`
`
`the schematic” of the circuit design, and the “design rule check ensures that [the
`
`layout does not violate] the rules laid down by the fabrication process technology.”
`
`Id., 5. “The design process moves back and forth between Layout [(step 5)], LVS
`
`[(step 7)] and DRC [(step 6)].” Id. In this iterative process, “design rules are
`
`checked” every time the “layout is modified,” id., 105, and the layout is modified
`
`to ensure compliance with the DRC that occurs in step 6. Id., 5-6 (“[A] design
`
`rule check ensures that the rules laid down by the fabrication process technology
`
`are not violated. A good example would be, some processes need transistors, wires
`
`and polysilicon to be of a certain minimum width. The layout would have to be
`
`drawn based on such constraints.”); Ex. 1202, ¶ 60.
`
`
`
`The design rules “are flexible and can be customized.” Ex. 1205, 105. For
`
`example, in Figure 5.29, Reddy shows an exemplary “DRC customization
`
`window” in which a DRC is performed on different metal interconnect layers of
`
`the IC under design (“Metal-1,” “Metal-2,” “Metal-3,” etc.).
`
`27
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,247,552
`Claim 11
`IPR2019-01200
`
`
`
`
`
`Ex. 1205, Fig. 5.29; Ex. 1202, ¶ 61.
`
` Making the Integrated Circuit
`In steps 8-9, final simulation is carried out and “files that describe the [IC]
`
`layout” are generated. Ex. 1205, 6. Then, in step 10, Reddy teaches fabrication of
`
`ICs using the modified layout:
`
`28
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,247,552
`Claim 11
`IPR2019-01200
`
`
`
`
`
`Ex. 1205, Fig. 1.1; Ex. 1202, ¶ 63.
`
`E. Overview of Vuong
`Vuong also describes steps to design and manufacture an IC, but explicitly
`
`includes a “metal fill” step in the design flow process. Ex. 1207, Abstract. Vuong
`
`states that increasing metal density by adding “metal-fill patterning” was a
`
`“common approach” used to avoid having too much space between active metal
`
`29
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,247,552
`Claim 11
`IPR2019-01200
`
`
`lines and unwanted “bumps” in layers in the finished chip (which can adversely
`
`affect polishing those layers). Id., [0003]-[0004] (“If there is an insufficient
`
`amount of metal …, then metal-fill is required to increase the proportion of metal
`
`….”); Ex. 1202, ¶¶ 69, 72.
`
`Vuong describes several approaches for adding metal-fill patterning during
`
`chip design. For example, Vuong explains that, after an IC design and layout are
`
`created, the layout can be divided into “portions or windows,” and checks can be
`
`carried out to determine if the amount of metal in those portions/windows meets
`
`certain metal density requirements. Ex. 1207, [0006] (“[A] chip layout is divided
`
`into a set of delineated portions or windows” and calculations are performed to
`
`determine the proportion of metal materials versus non-metal materials in each
`
`window); Ex. 1202, ¶ 73.
`
`If the calculations reveal that the amount of metal density in those areas falls
`
`below a threshold level, the layout is modified by adding a “fill template” (i.e., a
`
`“fixed pattern of uniform metal shapes”) to perform “fill patterning” “resulting in
`
`the new chip layout.” Ex. 1207, [0007], [0006] (“If the proportion of metal in that
`
`window is below a specified minimum percentage, then metal-fill patterning is
`
`performed to increase the amount of metal.”). Thereafter, “a determination is
`
`made whether the layout meets minimum and maximum metal requirements.” Id.,
`
`30
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,247,552
`Claim 11
`IPR2019-01200
`
`
`[0008]. If not, the process repeats “until th