(19) United States
`(12) Patent Application Publication (10) Pub. No.: US 2002/0162082 A1
`Cwynar et al.
`(43) Pub. Date:
`Oct. 31, 2002
`
`US 2002O162082A1
`
`(54) METHOD FOR MAKING AN
`INTERCONNECT LAYER AND A
`SEMCONDUCTOR DEVICE INCLUDING
`THE SAME
`
`(76) Inventors: Donald Thomas Cwynar, Orlando, FL
`(US); Sudhanshu Misra, Orlando, FL
`(US); Dennis Okumu Ouma, Somerset,
`NJ (US); Vivek Saxena, Orlando, FL
`(US); John Michael Sharpe,
`Allentown, PA (US)
`Correspondence Address:
`HTT GANES & BOSBRUN PC.
`P.O. BOX 832570
`RICHARDSON, TX 75083 (US)
`(21) Appl. No.:
`10/147,384
`(22) Filed:
`May 16, 2002
`Related U.S. Application Data
`(62) Division of application No. 09/484,310, filed on Jan.
`18, 2000, now Pat. No. 6,436,807.
`
`Publication Classification
`
`(51) Int. Cl." ....................... G06F 17/50; H01L 21/4763
`(52) U.S. Cl. ............................ 716/12; 438/618; 438/926;
`716/8; 716/10
`
`(57)
`
`ABSTRACT
`
`A method for making a layout for an interconnect layer of a
`Semiconductor device to facilitate uniformity of planariza
`tion during manufacture of the Semiconductor device
`includes determining an active interconnect feature density
`for each of a plurality of layout regions of the interconnect
`layout. The method further includes adding dummy fill
`features to each layout region to obtain a desired density of
`active interconnect features and dummy fill features to
`facilitate uniformity of planarization during manufacturing
`of the Semiconductor device. By adding dummy fill features
`to obtain a desired density of active interconnect features
`and dummy fill features, dummy fill features are not unnec
`essarily added, and each layout region has a uniform density.
`
`D - frr i Ve a active
`to-arear- 6 for
`a/o as ty (r ea. A
`layal- re yaw a 6.
`-Pg fa-'er law e
`la Ya
`
`
`
`
`
`Ae/e/ 4-nry All
`(a fur
`ae- i.
`laya- re?rom fo
`at-le- a ?esire /
`1ems -ty of -4.
`/-ir Cowe. -(e. lure
`cave/ / rary Alf
`4-fre
`
`so
`
`512
`
`5-y
`
`162.
`
`Intel Exhibit 1204
`
`

`

`Patent Application Publication Oct. 31, 2002 Sheet 1 of 3
`
`US 2002/0162082 A1
`
`
`
`2, s. 7 (re of Ali)
`
`

`

`Patent Application Publication Oct. 31, 2002 Sheet 2 of 3
`
`US 2002/0162082 A1
`
`2 o
`
`Du l- frr i Ve a active
`a-arear-fi fore
`
`layall re yaw a 6
`Pla ?a-free we
`fa Ye
`
`Ae/e/ 272-nrhy A 1/
`6- Aure f
`l ea
`laya- re.77 am. fo
`oblaw a -?es i? a 1
`/ems ify of a -4.
`?trico wr. -6. lure
`a wa? c/- may Af
`4a-fire r
`
`
`
`
`
`
`
`
`
`An//s. A
`
`1(2.
`
`21g2. 3
`
`

`

`Patent Application Publication Oct. 31, 2002 Sheet 3 of 3
`
`US 2002/0162082 A1
`
`
`
`1 sidi)
`
`

`

`US 2002/0162082 A1
`
`Oct. 31, 2002
`
`METHOD FOR MAKING AN INTERCONNECT
`LAYER AND A SEMCONDUCTOR DEVICE
`INCLUDING THE SAME
`
`FIELD OF THE INVENTION
`0001. The present invention relates to the field of inte
`grated circuit manufacturing, and, more particularly, to
`dummy fill features in an interconnect layer.
`
`BACKGROUND OF THE INVENTION
`0002 Chemical-mechanical polishing (CMP) is a tech
`nique for planarizing an interconnect layer overlying a
`Semiconductor Substrate. Typically, multiple interconnect
`layers are Stacked over the Semiconductor Substrate, wherein
`each interconnect layer includes active interconnect features
`connecting active areas of the Semiconductor Substrate. An
`active area is that portion of the Semiconductor Substrate in
`which components are built, Such as transistors, capacitors
`and resistors.
`0003. It is desirable to have a flat or planarized upper
`Surface of each interconnect layer prior to forming Subse
`quent interconnect layers. Depending on the density of the
`area occupied by the active interconnect features, the upper
`Surface may not always be flat after deposition of a dielectric
`material, thus the need for CMP.
`0004. The active interconnect features in an interconnect
`layer are separated by trenches. Referring to FIG. 1., the
`trenches 10 and 12 between active interconnect features 20,
`22 and 24 are much narrower than the trench 14 between
`active interconnect features 24 and 26. One approach for
`filling the trenches 10, 12 and 14 with dielectric material,
`particularly when the trenches are between closely spaced
`active interconnect features, is by a high density plasma
`chemical vapor deposition (HDP-CVD) process. If the
`deposited dielectric material 34 has a Sufficient thickness,
`then the Single Step deposition proceSS allows the intercon
`nect layer 30 to be planarized.
`0005. As a result of the HDP-CVD process, there are
`protrusions 32 in the upper Surface of the dielectric material
`34 above respective active interconnect features 20-26. Each
`protrusion 32 has associated therewith a bias. This bias can
`be defined as either positive or negative. For the HDP-CVD
`process as illustrated in FIG. 1, each protrusion 32 has a
`negative bias, i.e., the width of the protrusion is less than the
`width or lateral dimension 90 of the underlying active
`interconnect feature. Where there are no active interconnect
`features, Such as between active interconnect features 24 and
`26, the upper surface of the dielectric material 34 is rela
`tively flat.
`0006 Another approach for depositing the dielectric
`material is by a two-step process, as shown in FIG. 2. The
`first step is the HDP-CVD process for filling in the trenches
`10-14 with the dielectric material 34 between the active
`interconnect features 20-26. Once the trenches 10-14 are
`filled, a plasma enhanced chemical vapor deposition (PE
`CVD) process adds additional dielectric material 35 allow
`ing a combined thickness Sufficient for planarization. The
`protrusions 42 formed above the respective active intercon
`nect features 20-26 after the PE-CVD process results in a
`positive bias. Positive bias is where the width of the pro
`trusion 42 is greater than the width or lateral dimension 90
`of the underlying active interconnect feature.
`
`0007 Depending on the deposition process, CMP is used
`to eliminate the protrusions 42 having positive bias and the
`protrusions 32 having a negative bias. However, if pattern
`density variations of the active interconnect features 20-26
`are large, CMP is not adequate to Sufficiently planarize the
`interconnect layer 30. For example, planarization of the
`relatively flat dielectric material overlying active intercon
`nect features 24 and 26 results in over polishing. This causes
`significant dishing in the dielectric material 34 or 35, which
`results in a non-planarized Surface. A non-planarized Surface
`of the interconnect layer 30 may cause reliability problems
`with an overlying interconnect layer.
`0008 One approach for preventing over polishing is to
`place dummy fill features in the open regions adjacent active
`interconnect features for preventing pattern density varia
`tions of the active interconnect features. Placement of the
`dummy fill features is typically done using a layout algo
`rithm as part of a layout editor or an automated pattern
`generator.
`0009 Conventional layout algorithms for placing dummy
`fill features in open areas of the interconnect layer are
`performed based upon a predetermined Set density. Each
`open area to be filled with dummy fill features will have the
`Same density. In other words, the dummy fill feature density
`is independent of the density of the adjacent active inter
`connect features. An open area is defined as any area within
`the interconnect layer that does not have metal therein. The
`fill feature density is defined as the ratio of the area occupied
`by the metal to the total area.
`0010. However, if the density of an active interconnect
`feature is high with respect to an adjacent open area, it is not
`always necessary to place dummy fill features in the corre
`sponding open area at the same predetermined Set density.
`Unnecessarily placing dummy fill features adds to the para
`Sitic capacitance of the interconnect layer. Moreover, there is
`no constant overall fill density between open areas of the
`interconnect layer. This variation in the density of the
`interconnect layer also causes deviations when the intercon
`nect layer is planarized. Therefore, there is a need for
`making a layout for an interconnect layer that determines
`placement of dummy fill features for achieving a uniform
`density throughout the interconnect layer.
`
`SUMMARY OF THE INVENTION
`0011. An object of the present invention is to provide a
`method for making a layout for an interconnect layer that has
`uniform density throughout to facilitate planarization during
`manufacturing of a Semiconductor device.
`0012 Another object of the present invention is to posi
`tion dummy fill features within the interconnect layer to
`minimize parasitic capacitance with adjacent interconnect
`features.
`0013 These and other objects, advantages and features in
`accordance with the present invention are provided by a
`method for making a layout for an interconnect layer of a
`Semiconductor device to facilitate uniformity of planariza
`tion during manufacture of the Semiconductor device,
`wherein the method comprises the Steps of determining an
`active interconnect feature density for each of a plurality of
`layout regions of the interconnect layout, and adding
`dummy fill features to each layout region to obtain a desired
`
`

`

`US 2002/0162082 A1
`
`Oct. 31, 2002
`
`density of active interconnect features and dummy fill
`features to facilitate uniformity of planarization during
`manufacturing of the Semiconductor device.
`0.014) An important feature of the present invention is
`that each layout region preferably has a uniform density. By
`adding dummy fill features to obtain a desired density of
`active interconnect features and dummy fill features, dummy
`fill features are not unnecessarily added. Unnecessarily
`adding dummy fill features would undesirably increase the
`parasitic capacitance of the interconnect layer.
`0.015 When each layout region has a uniform density, the
`dummy fill features thus facilitate uniformity of planariza
`tion during manufacturing of the Semiconductor device.
`Another important feature of the present invention is that
`positioning of the dummy fill features is preferably based
`upon capacitance with adjacent active interconnect features.
`Likewise, the dummy fill features are also preferably posi
`tioned based upon capacitance with adjacent active inter
`connect features in an adjacent interconnect layer.
`0016 Yet another important feature of the method of the
`present invention preferably includes defining a minimum
`dummy fill feature lateral dimension based upon a dielectric
`layer deposition bias for a dielectric layer to be deposited
`over the interconnect layer. After a single step HDP-CVD
`process, the protrusion in the dielectric material overlying a
`respective active interconnect feature has a negative bias.
`Negative bias is where the width of the protrusion is less
`than the width or lateral dimension of the underlying active
`interconnect feature. In one embodiment, the lateral dimen
`sion of the dummy fill feature is preferably at least twice as
`great as an absolute value of a negative dielectric layer
`deposition bias.
`0.017. Another aspect of the present invention relates to a
`method for making a Semiconductor device comprising the
`Steps of making active regions in a Semiconductor Substrate,
`making a layout for an interconnect layer comprising the
`Steps of determining an active interconnect feature density
`for each of a plurality of layout regions of the interconnect
`layout; and adding dummy fill features to each layout region
`to obtain a desired density of active interconnect features
`and dummy fill features to facilitate uniformity of planariza
`tion during manufacturing of the Semiconductor device. The
`method preferably further comprises using the layout to
`make the interconnect layer overlying the Semiconductor
`Substrate.
`0.018 Yet another aspect of the present invention is a
`Semiconductor device comprising a Semiconductor Sub
`Strate, and at least one interconnect layer overlying the
`Semiconductor Substrate comprising a plurality of layout
`regions. Each layout region preferably comprises an active
`interconnect feature region and a dummy fill feature region
`adjacent thereto for facilitating uniformity of planarization
`during manufacturing of the Semiconductor device.
`0.019
`Each of the dummy fill regions preferably has a
`different density with respect to other dummy fill regions So
`that a combined density of the active interconnect feature
`region and the dummy fill feature region for a respective
`layout region is Substantially uniform with respect to a
`combined density of other layout regions. The interconnect
`layer preferably comprises metal, and each layout region
`preferably has a uniform density.
`
`DETAILED DESCRIPTION OF THE DRAWINGS
`0020 FIG. 1 is a partial cross-sectional view of a semi
`conductor device illustrating negative bias of the intercon
`nect layer produced by a single-step deposition process
`before planarization in accordance with the prior art.
`0021
`FIG. 2 is a partial cross-sectional view of a semi
`conductor device illustrating positive bias of the intercon
`nect layer produced by a two-step deposition process before
`planarization in accordance with the prior art.
`0022 FIG. 3 is a flowchart illustrating the method for
`making a layout for an interconnect layer in accordance with
`the present invention.
`0023 FIG. 4 is a partial top plan view of an interconnect
`layer divided into layout regions in accordance with the
`present invention.
`0024 FIG. 5 is a partial cross-sectional view of a semi
`conductor device including the interconnect layer illustrated
`in FIG. 4.
`
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENTS
`0025 The present invention will now be described more
`fully hereinafter with reference to the accompanying draw
`ings, in which preferred embodiments of the invention are
`shown. This invention may, however, be embodied in many
`different forms and should not be construed as limited to the
`embodiments set forth herein. Rather, these embodiments
`are provided so that this disclosure will be thorough and
`complete, and will fully convey the Scope of the invention
`to those skilled in the art. Like numbers refer to like
`elements throughout.
`0026. A method for making a layout for an interconnect
`layer of a Semiconductor device to facilitate uniformity of
`planarization during manufacture of the Semiconductor
`device is described with reference to FIGS. 3-5. From the
`start (Block 50), the method comprises the step of deter
`mining an active interconnect feature density for each of a
`plurality of layout regions 60(1)-60(n) of the interconnect
`layout 30 at Block 52 and as shown in FIG. 4.
`0027. The dimensions of each layout region 60(1)-60(n)
`are preferably equal, and an illustrative size may be 100
`micrometers by 100 micrometers. Moreover, the layout
`regions 60(1)-60(n) are contiguous. However, other dimen
`Sions are acceptable and the dimensions of each layout
`region do not have to be equal, as readily appreciated by one
`skilled in the art. For purposes of illustration, the active
`interconnect features 70(1)-70(n) are generally indicated by
`a single shaded area within each layout region 60(1)-60(n).
`Each shaded area comprises a plurality of metal lines or
`traces connecting the active areas in the Semiconductor
`Substrate 82, as readily appreciated by one skilled in the art.
`0028. The density of the active interconnect features
`70(1)-70(n) for respective layout regions 60(1)-60(n) is
`determined using a layout algorithm. This layout algorithm
`may be the same layout algorithm used for preforming the
`steps illustrated in FIG. 3 for making the desired layout of
`the interconnect layer, as readily appreciated by one skilled
`in the art.
`0029. The method further comprises the step of adding
`dummy fill features 74(1)-74(n) to each respective layout
`
`

`

`US 2002/0162082 A1
`
`Oct. 31, 2002
`
`region 60(1)-60(n) to obtain a desired density of active
`interconnect features and dummy fill features to facilitate
`uniformity of planarization during manufacturing of the
`semiconductor device 80 at Block 54. For purposes of
`illustration, the dummy fill features 74(1)-74(n) are gener
`ally indicated by a single Shaded area within each layout
`region 60(1)-60(n). Each shaded area thus comprises
`dummy metal lines or traces, as readily appreciated by one
`skilled in the art. The method advantageously adds dummy
`fill features 74(1)-74(n) so that a uniform density is obtained
`for each layout region 60(1)-60(n). Making the interconnect
`layer 30 is completed at Block 56.
`0.030. For example, if the density of the active intercon
`nect features 70(1) in layout region 60(1) is 50 percent, and
`the desired target density of active interconnect features and
`dummy fill features is also 50 percent, then the density of the
`dummy fill features 74(1) added is also 50 percent. How
`ever, if the density of the active interconnect features 70(1)
`is less than 50 percent in layout region 60(2), then the
`density of the dummy fill features 74(2) added is more than
`50 percent So that the desired target density of active
`interconnect features and dummy fill features for the layout
`region is once again 50 percent. Minimizing overall density
`variations between layout regions 60(1)-60(n) of the inter
`connect layer 30 facilitates planarization by chemical
`mechanical polishing (CMP) during manufacturing of the
`semiconductor device 80.
`0031 When each layout region 60(1)-60(n) has a uniform
`density, the dummy fill features 74(1)-74(n) thus facilitate
`uniformity of planarization during manufacturing of the
`Semiconductor device. However, the density does not have
`to be uniform for every layout region 60(1)-60(n) since each
`Semiconductor device can significantly vary in terms of the
`density of the active areas in the Semiconductor Substrate 82,
`which in turn effects the layout of the active interconnect
`features in the overlying interconnect layer 30.
`0032. Nonetheless, each layout region 60(1)-60(n) pref
`erably has a uniform density. By adding dummy fill features
`74(1)-74(1) to obtain a desired density of active interconnect
`features and dummy fill features, dummy fill features are not
`unnecessarily added. Unnecessarily adding dummy fill fea
`tures would undesirably increase the parasitic capacitance of
`the interconnect layer 30.
`0033. Another important feature of the present invention
`is that positioning of the dummy fill features 74(1)-74(n) is
`based upon capacitance with adjacent active interconnect
`features 70(1)-70(n). Likewise, the dummy fill features
`74(1)-74(n) are also preferably positioned based upon
`capacitance with adjacent active interconnect features in an
`adjacent interconnect layer. In other words, the dummy fill
`features are Selectivity positioned SO-that the added parasitic
`capacitance resulting therefrom is minimized.
`0034 AS readily known by one skilled in the art, there are
`two types of dummy fill features: grounded and floating.
`When the grounded configuration is used, all dummy fill
`features are at a known potential, Such as ground. Conse
`quently, the layout algorithm can calculate capacitance after
`the dummy fill features are positioned. In the floating
`configuration, the dummy fill features are added to low
`density areas. However, floating dummy fill features Serve as
`additional coupling paths and effect the total parasitic
`capacitance of the interconnect layer 30. Determination of
`the capacitance from the floating configuration is difficult to
`calculate Since there is no path to ground.
`
`0035. The layout algorithm used in the present invention
`for making a layout for an interconnect layer 30 determines
`placement of the dummy fill features 74(1)-74(n) for mini
`mizing overall parasitic capacitance as a result of the added
`dummy fill features. This algorithm places restrictions on the
`floating dummy fill features 74(1)-74(n) so that they are
`connected to ground if within a certain range to the active
`interconnect features 70(1)-70(n).
`0036) This range may be the buffer length specified in the
`algorithm, which is the minimum distance allowed between
`any active interconnect feature region 70(1)-70(n) and the
`dummy fill feature region. In this case, the dummy fill
`74(1)-74(n) features immediately surrounding the active
`interconnect features would all be grounded. In general, the
`range can be optimized to get the best trade-off between the
`design resources available and the additive component of
`capacitance introduced due to the coupling effects of the
`dummy fill features.
`0037 Yet another important feature of the method of the
`present invention includes defining a minimum dummy fill
`feature lateral dimension 90 based upon a dielectric layer
`deposition bias for the dielectric material 34 or 35 to be
`deposited over the interconnect layer 30, as illustrated in
`FIGS. 1 and 2. The dielectric material is silicon dioxide.
`After the single step HDP-CVD process illustrated in FIG.
`1, the protrusions 32 in the dielectric material Overlying a
`respective active interconnect feature has a negative bias.
`Negative bias is where the width of the protrusion 32 is less
`than the width or lateral dimension 90 of the underlying
`active interconnect feature 20-26.
`0038 Referring to FIG. 1, a dummy fill feature is nec
`essary between active interconnect features 24 and 26 to
`cause another protrusion 32 in the upper Surface of the
`dielectric material 34 to facilitate planarization of the inter
`connect layer 30. Ideally, the protrusions 32 are positioned
`in the dielectric material 34 So that dishing during the
`planarization process is prevented.
`0039. With respect to a negative dielectric layer deposi
`tion bias, the lateral dimension 90 of any dummy fill feature
`to be added needs to be a minimum size to cause the desired
`protrusion. For example, if the negative bias is -1.5 microns,
`then the lateral dimension of the dummy fill feature needs to
`be at least twice an absolute value of the negative dielectric
`layer deposition bias. In other words, the lateral dimension
`needs to be at least 3 microns to cause a negative bias of -1.5
`at the upper Surface of the dielectric material.
`0040 For a positive dielectric layer deposition bias, as
`shown in FIG. 2, there is no minimum lateral dimension
`requirement for the dummy fill feature for causing a pro
`trusion 42 at the upper surface of the dielectric material 35
`Since the positive bias is always greater than a lateral
`dimension of a respective dummy fill feature.
`0041 Another aspect of the present invention relates to a
`Semiconductor device 80 comprising a Semiconductor Sub
`strate 82, and at least one interconnect layer 30 overlying the
`semiconductor Substrate. The interconnect layer 30 com
`prises a Semiconductor Substrate 82, and at least one inter
`connect layer overlying the Semiconductor Substrate com
`prising a plurality of layout regions 60(1)-60(n).
`0042 Each layout region 60(1)-60(n) comprises an active
`interconnect feature region 70(1)-70(n) and a dummy fill
`feature region 74(1)-74(n) adjacent thereto for facilitating
`uniformity of planarization during manufacturing of the
`Semiconductor device. Each of the dummy fill regions
`
`

`

`US 2002/0162082 A1
`
`Oct. 31, 2002
`
`74(1)-74(n) has a different density with respect to other
`dummy fill regions So that a combined density of the active
`interconnect feature region 70(1)-70(n) and the dummy fill
`feature region for a respective layout region 60(1)-60(n) is
`Substantially uniform with respect to a combined density of
`other layout regions. The interconnect layer 30 comprises
`metal, and each layout region 60(1)-60(n) has a uniform
`density.
`0.043 Many modifications and other embodiments of the
`invention will come to the mind of one skilled in the art
`having the benefit of the teachings presented in the forego
`ing descriptions and the associated drawings. Therefore, it is
`to be understood that the invention is not to be limited to the
`Specific embodiments disclosed, and that modifications and
`embodiments are intended to be included within the scope of
`the appended claims.
`
`That which is claimed is:
`1. A method for making a layout for an interconnect layer
`of a Semiconductor device to facilitate uniformity of pla
`narization during manufacture of the Semiconductor device,
`the method comprising the Steps of
`determining an active interconnect feature density for
`each of a plurality of layout regions of the interconnect
`layout; and
`adding dummy fill features to each layout region to obtain
`a desired density of active interconnect features and
`dummy fill features to facilitate uniformity of pla
`narization during manufacturing of the Semiconductor
`device
`2. A method according to claim 1 further comprising
`positioning the dummy fill features based upon capacitance
`with adjacent active interconnect features.
`3. A method according to claim 1 further comprising
`positioning the dummy fill features based upon capacitance
`with adjacent active interconnect features in an adjacent
`interconnect layer.
`4. A method according to claim 1 wherein the Step of
`adding the dummy fill features comprises defining a mini
`mum dummy fill feature lateral dimension based upon a
`dielectric layer deposition bias for a dielectric layer to be
`deposited over the interconnect layer.
`5. A method according to claim 4 wherein the lateral
`dimension is at least twice as great as an absolute value of
`a negative dielectric layer deposition bias.
`6. A method according to claim 1 wherein the interconnect
`layer comprises metal.
`7. A method according to claim 1 wherein each layout
`region has a uniform density.
`8. A method according to claim 1 wherein the layout
`regions are contiguous.
`9. A method according to claim 1 wherein all the layout
`regions have a Same size.
`10. A method for making a Semiconductor device com
`prising the Steps of
`making active regions in a Semiconductor Substrate;
`making a layout for an interconnect layer comprising the
`Steps of
`determining an active interconnect feature density for
`each of a plurality of layout regions of the intercon
`nect layout, and
`
`adding dummy fill features to each layout region to
`obtain a desired density of active interconnect fea
`tures and dummy fill features to facilitate uniformity
`of planarization during manufacturing of the Semi
`conductor device; and
`using the layout to make the interconnect layer overlying
`the Semiconductor Substrate.
`11. A method according to claim 10 further comprising
`planarizing the interconnect layer.
`12. A method according to claim 11 wherein the Step of
`planarizing is performed using chemical mechanical polish
`ing.
`13. A method according to claim 10 further comprising
`positioning the dummy fill features based upon capacitance
`with adjacent active interconnect features.
`14. A method according to claim 10 further comprising
`positioning the dummy fill features based upon capacitance
`with adjacent active interconnect features in an adjacent
`interconnect layer.
`15. A method according to claim 10 wherein the step of
`adding the dummy fill features comprises defining a mini
`mum dummy fill feature lateral dimension based upon a
`dielectric layer deposition bias for a dielectric layer to be
`deposited over the interconnect layer.
`16. A method according to claim 15 wherein the lateral
`dimension is at least twice as great as an absolute value of
`a negative dielectric layer deposition bias.
`17. A method according to claim 10 wherein the inter
`connect layer comprises metal.
`18. A method according to claim 10 wherein each layout
`region has a uniform density.
`19. A method according to claim 10 wherein the layout
`regions are contiguous.
`20. A method according to claim 10 wherein all the layout
`regions have a Same size.
`21. A Semiconductor device comprising:
`a Semiconductor Substrate; and
`at least one interconnect layer overlying Said Semicon
`ductor Substrate comprising a plurality of layout
`regions, each layout region comprising an active inter
`connect feature region and a dummy fill feature region
`adjacent thereto for facilitating uniformity of planariza
`tion during manufacturing of the Semiconductor device,
`each of Said dummy fill regions having a different density
`with respect to other dummy fill regions So that a
`combined density of Said active interconnect feature
`region and Said dummy fill feature region for a respec
`tive layout region is Substantially uniform with respect
`to a combined density of other layout regions.
`22. A Semiconductor device according to claim 21
`wherein Said interconnect layer comprises metal.
`23. A Semiconductor device according to claim 21
`wherein each layout region has a uniform density.
`24. A Semiconductor device according to claim 21
`wherein the layout regions are contiguous.
`25. A Semiconductor device according to claim 21
`wherein all the layout regions have a Same size.
`
`