(19) United States
`(12) Patent Application Publication (10) Pub. No.: US 2004/0150112 A1
`Oda
`(43) Pub. Date:
`Aug. 5, 2004
`
`US 2004O15O112A1
`
`(54) SEMICONDUCTOR DEVICE AND METHOD
`OF EABRICATION SAME
`
`(75) Inventor: Noriaki Oda, Kanagawa (JP)
`
`Correspondence Address:
`YOUNG & THOMPSON
`745 SOUTH 23RD STREET 2ND FLOOR
`ARLINGTON, VA 2.2202
`
`(73) Assignee: NEC ELECTRONICS CORPORA-
`TION, KANAGAWA (JP)
`(21) Appl. No.:
`10/761,204
`
`(22) Filed:
`
`Jan. 22, 2004
`
`Foreign Application Priority Data
`(30)
`Jan. 30, 2003 (JP)...................................... 2003-021959
`O
`O
`Publication Classification
`
`51) Int. Cl. ........................... H01L 23/48; HO1L 29/40
`(
`reo.
`(52) U.S. Cl. ............................................ 257/758; 257/762
`(57)
`ABSTRACT
`
`A Semiconductor device having bonding pads on a Semi
`conductor Substrate includes: an upper copper layer that is
`formed on the lower surface of the bonding pads with a
`barrier metal interposed and that has a copper area ratio that
`is greater than layers in which circuit interconnects are
`formed; and a lower copper layer that is electrically insu
`lated from the upper copper layer and that is formed closer
`to the Semiconductor Substrate than the upper copper layer.
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`Patent Application Publication Aug. 5, 2004 Sheet 1 of 5
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`

`US 2004/015O112 A1
`
`Aug. 5, 2004
`
`SEMCONDUCTOR DEVICE AND METHOD OF
`FABRICATION SAME
`
`BACKGROUND OF THE INVENTION
`0001) 1. Field of the Invention
`0002 The present invention relates to a semiconductor
`device having bonding pads for wire bonding, and to a
`method of fabricating the Semiconductor device.
`0003 2. Description of the Related Art
`0004. When forming bonding pads over copper intercon
`nects in Semiconductor devices of the prior art that employ
`copper interconnects, the bonding portions are in Some cases
`provided at positions that are shifted from above the copper
`interconnects (refer to Japanese Patent Laid-Open Publica
`tion No. 2001-15516, pp. 4-5, FIG. 2).
`0005 FIG. 1 is a sectional structural view showing an
`example of the construction of a Semiconductor device of
`the prior art. Referring to FIG. 1, a plurality of copper pads
`are provided on copper interconnects 700 that are formed on
`Semiconductor Substrate 10, uppermost layer aluminum
`interconnect 730 being formed over uppermost layer copper
`pad 710 with barrier metal 720 interposed. Bonding portion
`735 of uppermost layer aluminum interconnect 730 is at a
`position that is shifted with respect to copper interconnect
`700. As a result, stress that occurs when bonding is exerted
`upon passivation insulation film 740 and interlevel dielectric
`film 750 that underlie bonding portion 735. The influence of
`StreSS upon copper interconnect 700 during bonding can thus
`be reduced and the exposure of copper interconnects 700 on
`the Surface can be prevented.
`0006 Nevertheless, the above-described semiconductor
`device of the prior art has Several drawbackS.
`0007 First, because this is a construction in which bond
`ing portions are provided at positions that are shifted with
`respect to the copper interconnects, the area of the bonding
`pads is greater than for a case in which the bonding portions
`are provided immediately above the copper interconnects,
`and this construction therefore tends to increase chip size.
`0008 Further, if a low-k film that has a lower relative
`dielectric constant than an oxide film is present below the
`bonding portion, the load of a needle during probing or
`bonding depresses the bonding pads and may cause cracks
`in the interlevel dielectric film that underlies the bonding
`pads or may cause film to peel in the bonding pads.
`
`SUMMARY OF THE INVENTION
`0009. The present invention was developed to solve the
`above-described problems of the prior art and has as an
`object the provision of a Semiconductor device having
`improved resistance to shock to the bonding pads during
`probing and bonding (hereinbelow referred to as "shock
`resistance”), and to a method of fabricating Such a semi
`conductor device.
`0.010 The semiconductor device of the present invention
`for achieving the above-described object includes: bonding
`pads that are formed on a Semiconductor Substrate; an upper
`copper layer that is formed on the lower Surface of these
`bonding pads with a barrier metal interposed; and a lower
`copper layer that is formed closer to the Semiconductor
`
`Substrate than the upper copper layer; wherein the lower
`copper layer has a copper area ratio that is equal to or leSS
`than that of the upper copper layer.
`0011) Another semiconductor device of the present
`invention includes: bonding pads that are formed on a
`Semiconductor Substrate; an upper copper layer that is
`formed on the lower surface of the bonding pads with a
`barrier metal interposed; and a lower copper layer that is
`formed closer to the Semiconductor Substrate than the upper
`copper layer; wherein the upper copper layer is electrically
`insulated from the lower copper layer, and the copper area
`ratio of the upper copper layer is greater than that of circuit
`interconnect layers that are formed on the Semiconductor
`Substrate.
`0012. In each of the above-described semiconductor
`devices, the copper area ratio of the upper copper layer may
`be at least 70%.
`0013 In addition, the planar dimensions of the bonding
`pads and the upper copper layer may be Substantially the
`SC.
`0014 Further, the upper copper layer may be constituted
`by a plurality of copper layers. In Such a case, the copper
`area ratio of each of the copper layers of the upper copper
`layer may be the same. In addition, the Semiconductor
`device may further include: interlevel dielectric films that
`are provided between each of the copper layers of the upper
`copper layer; and via-plugs composed of copper that are
`embedded in the interlevel dielectric films; wherein each of
`the copper layers of the upper copper layer are connected by
`way of the Via-plugs. Further, the copper layer pattern of the
`copper layer that is located in the uppermost layer of the
`upper copper layer and the Via-plugs that are connected to
`this copper layer pattern may be embedded in a dielectric
`film that is composed of a first material.
`0015 The copper area ratio of the lower copper layer
`may be at least 15% and not greater than 95%.
`0016. The lower copper layer may be composed of a
`plurality of copper layers. In Such a case, the copper area
`ratio of each of the copper layers of the lower copper layer
`may be the same. Further, dielectric films composed of a first
`material may be interposed between each of the copper
`layers of the lower copper layer. Each of the copper layers
`of the lower copper layer may be constituted by a copper
`layer pattern that is embedded in a dielectric film composed
`of a Second material having a lower relative dielectric
`constant than the first material. The Second material may be
`a softer Substance than the first material. Still further, the
`dielectric films that are composed of the Second material
`may contain any one of: a SiOC film, a silicon carbide (SiC)
`film, a SiOF film, a porous silicon dioxide (SiO2) film, a
`porous SiOC film, and a ladder oxide film having a ladder
`type hydrogenated Siloxane.
`0017. A dielectric film that is composed of a third mate
`rial that has a lower relative dielectric constant than the first
`material may be interposed between each of the copper
`layers of the lower copper layer. In Such a case, the third
`material may be a Softer Substance than the first material. In
`addition, the dielectric films that are composed of the third
`material may contain any one of a SiOC film, a Silicon
`carbide (SiC) film, a SiOF film, a porous silicon dioxide
`
`

`

`US 2004/015O112 A1
`
`Aug. 5, 2004
`
`(SiO2) film, a porous SiOC film, and a ladder oxide film
`having a ladder-type hydrogenated Siloxane.
`0.018. The barrier metal may contain either of titanium
`nitride (TiN) and tantalum nitride (TaN).
`0019. The semiconductor device may further include:
`internal circuits that are provided on the Semiconductor
`Substrate; and auxiliary copper interconnects that are elec
`trically connected to the internal circuits, and
`0020 these auxiliary copper interconnects may be elec
`trically connected to a portion of the bonding pads by way
`of via-holes.
`0021. In the method of fabricating the semiconductor
`device of the present invention, the upper copper layer and
`lower copper layer are formed by a damascene method.
`0022. In another method of fabricating the semiconductor
`device of the present invention, the copper layer pattern of
`the copper layer that is positioned in the uppermost layer of
`the upper copper layer and the Via-plugs that connect to this
`copper pattern are formed by a dual damascene method.
`0023 The present invention as described in the foregoing
`explanation takes advantage of one of the characteristics of
`copper, i.e., that copper has greater elasticity than an oxide
`film, elasticity is the property to rebound from force that is
`applied from the outside. In other words, the Semiconductor
`device of the present invention has a structure in which the
`upper copper layer and lower copper layer below the bond
`ing pads function as shock-resistant layers that impede the
`transmission of Shocks below the bonding pads.
`0024.
`In forms of the present invention in which the
`copper area ratio of the upper copper layer is at least 70%,
`Shock resistance during probing and bonding is more greatly
`improved.
`0.025
`In forms of the present invention in which the
`planar dimensions of the bonding pads and upper copper
`layer are Substantially the Same, the contact area between the
`bonding pads and upper copper layer can be made Sufficient.
`0026. In forms of the present invention in which the
`upper copper layer is constituted by a plurality of copper
`layers, shocks are distributed among each of the copper
`layers. In addition, Shocks are more evenly distributed in
`forms of the present invention in which the copper area
`ratioS of each of the copper layers of the upper copper layer
`are the Same.
`0027. In forms of the present invention in which each of
`the copper layers of the upper copper layer are connected by
`way of Via-plugs, shocks to the uppermost layer are more
`easily distributed to the other layers.
`0028. In forms of the present invention in which the
`dielectric film that is composed of a first material and in
`which the uppermost layer of the upper copper layer and the
`Via-plugs that connect to this uppermost layer are embedded
`is a hard material, the uppermost layer and the Via-plugs that
`receive the greatest shock during bonding are uniformly
`Supported by a hard dielectric film.
`0029. Forms of the present invention in which the copper
`area ratio of the lower copper layer is at least 15% and not
`greater than 95% allow a Still greater improvement in Shock
`resistance. As a result, the lower copper layer can be used as
`
`a circuit interconnect layer having a copper area ratio of at
`least 15% and at most 95%, and the region underlying the
`bonding pads can be more effectively utilized.
`0030. In forms of the present invention in which the
`lower copper layer is constituted by a plurality of copper
`layers, shocks that are conveyed to the lower copper layer
`are distributed among each of the copper layers. Shocks that
`are conveyed to the lower copper layer are more evenly
`distributed by making the copper area ratioS of each of the
`copper layers of the lower copper layer the same.
`0031. In forms of the present invention that include
`dielectric films that are composed of the first material
`between each of the copper layers of the lower copper layer,
`the lower copper layer can be more uniformly Supported by
`the dielectric films.
`0032. In forms of the present invention in which each of
`the copper layers of the lower copper layer is constituted by
`a copper layer pattern that is embedded in a dielectric film
`that is composed of a Second material having a lower relative
`dielectric constant than the first material, the capacitance
`between copper layer patterns can be reduced within the
`Same copper layer.
`0033. In forms of the present invention in which dielec
`tric films that are composed of a third material that includes
`a material having a lower relative dielectric constant than the
`first material are used as the interlevel dielectric films of the
`lower copper layer, the capacitance between a plurality of
`interconnect layers that are formed on the same level as the
`lower copper layer can be reduced.
`0034.
`In forms of the present invention in which either
`one of titanium nitride (TiN) and tantalum nitride (TaN) are
`used as the barrier metal, the barrier metal can prevent the
`mutual diffusion of aluminum and copper between layers
`overlying and underlying the barrier metal.
`0035) In forms of the present invention in which bonding
`pads are connected to auxiliary copper interconnects, elec
`trical connection between bonding pads and internal circuits
`can be guaranteed even when shocks that occur during
`bonding cause cracks in the upper copper layer and thus
`cause defective connections.
`0036) The above and other objects, features, and advan
`tages of the present invention will become apparent from the
`following description with reference to the accompanying
`drawings, which illustrate examples of the present invention.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`0037 FIG. 1 is a sectional structural view showing one
`example of the construction of a Semiconductor device of
`the prior art.
`0038 FIG. 2A is a sectional structural view showing the
`construction of a region that includes a bonding pad of the
`Semiconductor device that is the first working example of
`the present invention.
`0039 FIG. 2B is a schematic view showing an example
`of the dummy pattern of the first upper copper layer.
`0040 FIG. 2C is a schematic view showing an example
`of the dummy pattern of the first lower copper layer.
`
`

`

`US 2004/015O112 A1
`
`Aug. 5, 2004
`
`FIG. 3 is a sectional structural view of the semi
`0041
`conductor device that is the Second working example of the
`present invention.
`0.042
`FIG. 4A is a plan view of the semiconductor
`device that is the third working example of the present
`invention.
`0.043
`FIG. 4B is a sectional structural view showing the
`portion along double-dot-single-dash line A-A in FIG. 4A.
`0044 FIG. 5 is a sectional structural view showing the
`configuration of the Semiconductor device that is the fourth
`working example of the present invention.
`
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENTS
`004.5 The semiconductor device of the present invention
`is provided with: an upper copper layer that is formed below
`bonding pads with a barrier metal interposed; and a lower
`copper layer that is electrically insulated from this upper
`copper layer; wherein these copper layerS Serve as a shock
`resistant layers.
`0046) First Working Example
`0047 FIG. 2A is a sectional structural view showing the
`configuration of an area that includes a bonding pad of the
`Semiconductor device that is the first working example of
`the present invention.
`0.048
`Referring now to FIG. 2A, the semiconductor
`device of the present working example includes upper
`copper layer 100 for improving shock resistance, this upper
`copper layer 100 being formed below bonding pad 130 that
`includes a metal film having aluminum (Al) as its chief
`component, a barrier metal being interposed between upper
`copper layer 100 and bonding pad 130. The barrier metal is
`provided for preventing the aluminum that is contained in
`bonding pad 130 from reacting with elements that are
`contained in the upper layer. Lower copper layer 100 and
`bonding pad 130 have substantially identical planar dimen
`Sions (meaning that the planar dimensions are identical
`within the range of fabrication error), and upper copper layer
`100 uniformly supports bonding pad 130 from below.
`0049. To provide additional shock resistance, lower cop
`per layer 200 that is electrically insulated from upper copper
`layer 100 is provided below upper copper layer 100 with
`oxide film (SiO film)32 interposed. Silicon dioxide (SiO2)
`film 32 is a dielectric film that is harder than a low-k film.
`The interposition of this SiO film 32 between upper copper
`layer 100 and lower copper layer 200 prevents denting due
`to force that is applied during bonding.
`0050. Upper copper layer 100 is composed of first upper
`copper layer 110 and Second upper copper layer 120, and
`first upper copper layer 110 and Second upper copper layer
`120 are electrically connected by via-plugs 140 that are
`chiefly composed of copper. Upper copper layer 100 is
`therefore a two-layer Structure, whereby Shocks that are
`exerted upon bonding pad 130 are distributed between each
`of the layerS and an improvement in Shock resistance is
`obtained. The number of copper layers that are formed as
`upper copper layer 100 may be three or more.
`0051 Since second upper copper layer 120 and via-plugs
`140 receive most of the force that is applied during bonding,
`
`a dielectric film (SiO film) that is harder than a low-k film
`is preferably employed as the dielectric film composed of a
`first material within which these constituent elements are
`buried. In the present working example, Second upper cop
`per layer 120 and via-plugs 140 are each buried in silicon
`dioxide (SiO) films 42 and 44, respectively, these films 42
`and 44 being composed of the first material. Silicon dioxide
`(SiO2) films 42 and 44 are hard, and Second upper copper
`layer 120 and via-plugs 140 are therefore uniformly Sup
`ported by these silicon dioxide (SiO2) films 42 and 44.
`0052 Lower copper layer 200 is composed of two layers,
`first lower copper layer 210 and Second lower copper layer
`220, and first lower copper layer 210 and second lower
`copper layer 220 are insulated by silicon dioxide (SiO2) film
`22. The use of a plurality of copper layers for lower copper
`layer 200 provides the same effects as in upper copper layer
`100 that has been described above.
`0053 Laminated dielectric film 14, which is composed of
`a ladder-oxide film and a silicon dioxide (SiO) film, is
`interposed between the copper layer patterns of first lower
`copper layer 210. The ladder-oxide film in this case is L-OX,
`(a trademark of NEC Electronics Corporation (now in the
`application process)), which is a low-k film having a ladder
`type hydrogenated Siloxane. Laminated dielectric film 24
`that is composed of L-OX film and a silicon dioxide (SiO2)
`film is Similarly interposed between the copper layer pat
`terns in Second lower copper layer 220. Forming laminated
`dielectric films 14 and 24 from dielectric films (L-OX films)
`composed of a Second material that has a lower relative
`dielectric constant than the first material reduces the capaci
`tance between interconnects of the copper interconnects that
`are formed on the same level as lower copper layer 200.
`0054 Although not shown in FIG. 2A, in addition to
`regions that contain the above-described bonding pads,
`internal circuits including Semiconductor elements Such as
`transistors, resistors, and capacitors and the circuit intercon
`nects for interconnecting these Semiconductor elements are
`also provided on semiconductor substrate 10. The circuit
`interconnects are formed from conductive layerS Such as
`copper layers that are formed on the same layer as either of
`upper copper layer 100 and lower copper layer 200, diffu
`Sion layers that are formed on Semiconductor Substrate 10,
`and polysilicon in which impurities are diffused. Connec
`tions between bonding pad 130 and internal circuits are
`realized by way of, for example, upper copper layer 100.
`0055 Explanation next regards the planar patterns of
`upper copper layer 100 and lower copper layer 200. The
`patterns of upper copper layer 100 and lower copper layer
`200 are referred to as “dummy patterns” in the following
`explanation based on the view that upper copper layer 100
`and lower copper layer 200, rather than constituting the
`interconnects of internal circuits, function as dummy layers
`for distributing the shock applied to bonding pad 130.
`0056 FIG. 2B is a schematic view showing an example
`of a dummy pattern (planar pattern) of first upper copper
`layer 110, the sectional structure along the double-dot
`single-dash line A-A being shown in FIG. 2A. The dummy
`pattern of Second upper copper layer 120 is identical to that
`of first upper copper layer 110 and explanation is therefore
`here omitted.
`0057. As shown in FIG. 2B, square-shaped patterns of a
`plurality of laminated dielectric films 34 are scattered in the
`
`

`

`US 2004/015O112 A1
`
`Aug. 5, 2004
`
`dummy pattern of first upper copper layer 110 Such that the
`overall area density of copper is uniform. The copper area
`ratio is the proportion of the area that is occupied by copper
`(copper-occupied area ratio), and shock resistance improves
`as this ratio increases. In this case, the copper area ratio of
`the dummy pattern is made greater than that of the copper
`layer in which the circuit interconnects are formed in order
`to raise the shock resistance. Based on experimental results
`obtained to date, the copper area ratio of a dummy pattern
`is preferably at least 70%. In addition, the copper area ratio
`of a dummy pattern is preferably not greater than 95% to
`prevent dishing during the CMP (Chemical Mechanical
`Polishing) processing of the copper layer.
`0.058
`FIG. 2C is a schematic view showing an example
`of a dummy pattern (planar pattern) of first lower copper
`layer 210, the Sectional Structure along double-dot-Single
`dash line B-B' being shown in FIG. 2A. The dummy pattern
`of second lower copper layer 220 is identical to that of first
`lower copper layer 210, and explanation of this dummy
`pattern is therefore here omitted.
`0059. As shown in FIG. 2C, cross-shaped patterns of a
`plurality of laminated dielectric films 14 are scattered in the
`dummy pattern of first lower copper layer 210 such that the
`overall copper area density is uniform. The copper area ratio
`of first lower copper layer 210 is preferably at least 15% for
`improving shock resistance, and further, preferably not
`greater than 95% for the same reasons Stated regarding
`upper copper layer 100.
`0060 Since lower copper layer 200 is subjected to less
`StreSS during bonding than upper copper layer 100, the
`copper area ratio of lower copper layer 200 is preferably
`equal to or less than that of upper copper layer 100.
`0061. In addition, the dummy pattern of lower copper
`layer 200 is electrically insulated from upper copper layer
`100, and this dummy pattern may therefore be used as a
`pattern for circuit interconnects. Using lower copper layer
`200 as a circuit interconnect layer in this way enables the
`effective utilization of the area below bonding pad 130.
`However, the copper area ratio of lower copper layer 200 in
`this case is Smaller than the copper area ratio of upper copper
`layer 100.
`0.062
`Further, first lower copper layer 210 and second
`lower copper layer 220 are electrically insulated by an
`interlevel dielectric film, but these layers may also be
`electrically connected by Via-plugs.
`0.063. The method of fabricating the semiconductor
`device of the above-described working example is next
`explained with reference to FIG. 2A. The following expla
`nation deals only with the procedures for fabricating ele
`ments for improving shock resistance of the bonding pads,
`these elements being the distinguishing feature of the Semi
`conductor device of the present working example, and
`detailed explanation regarding the circuit interconnects that
`are formed on the same level as each of the copper layers
`that Serve as shock resistance layerS is therefore omitted.
`0.064 Semiconductor elements such as transistors, resis
`tors, and capacitors (not shown in the figure) are formed on
`semiconductor Substrate 10, a silicon dioxide (SiO2) film 12
`is formed over these elements by a CVD method to a
`thickness of 300-500 nm as an interlevel dielectric film,
`following which stopper-SiCN film 13 is further formed to
`
`a thickness of 30-50 nm as a film for preventing etching
`(hereinbelow referred to as an “etching stopper film’). Next,
`an L-OX film is formed to a thickness of 300-500 nm over
`Stopper-SiCN film 13 by an application and Sintering pro
`cess and a silicon dioxide (SiO2) film is grown to a thickness
`of 100-200 nm over this L-OX film to form laminated
`dielectric film 14 that is composed of the L-OX film and
`Silicon dioxide (SiO2) film. A resist pattern is next formed on
`laminated dielectric film 14 by means of a photolithographic
`process, following which etching is carried out using this
`resist pattern as a mask to form a prescribed dummy pattern
`and interconnect trenches for forming circuit interconnects
`(not shown in the figure) on laminated dielectric film 14. The
`resist pattern is then removed.
`0065) Next, a barrier metal having a thickness of 30-50
`nm and a seed layer having a thickness of 50-200 nm are
`successively formed on laminated dielectric film 14 in which
`the dummy pattern and interconnect trenches have been
`formed, and a copper film having a thickness of 500-1000
`nm is additionally formed over these layers by means of an
`electroplating method. After employing a CMP process to
`grind the copper film until the upper Surface of laminated
`dielectric film 14 is exposed, cap-SiCN film 15 having a
`thickness of 30-50 nm is formed as a film for preventing the
`diffusion of copper. First lower copper layer 210 having the
`dummy pattern shown in FIG. 2C is thus completed.
`0066. After forming first lower copper layer 210, silicon
`dioxide (SiO2) film 22 having a thickness of 300-500 nm is
`formed over first lower copper layer 210, and second lower
`copper layer 220 is formed by the same procedure as the
`above-described fabrication process of first lower copper
`layer 210.
`0067 Silicon dioxide (SiO) film 32 having a thickness
`of 300-500 nm and stopper-SiCN film 33 having a thickness
`of 30-50 nm are next formed over second lower copper layer
`220. Laminated dielectric film 34 that is composed of an
`L-OX film having a thickness of 300-500 nm and a silicon
`dioxide (SiO2) film having a thickness of 100-200 nm is then
`formed. A resist pattern is next formed on laminated dielec
`tric film 34 by means of a photolithographic process, fol
`lowing which a prescribed dummy pattern and interconnect
`trenches for forming circuit interconnects not shown in the
`figure are formed on laminated dielectric film 34 by an
`etching process. The resist pattern is then removed.
`0068 Abarrier metal having a thickness of 30-50 nm, a
`Seed layer having a thickness of 50-100 nm, and a copper
`film having a thickness of 600-1000 nm are next succes
`sively formed on laminated dielectric film 34 on which the
`dummy pattern and interconnect trenches have been formed.
`The copper film is next ground by a CMP process until the
`upper Surface of laminated dielectric film 34 is exposed,
`following which cap-SiCN film 35 having a thickness of
`30-50 nm is formed. In this way, first upper copper layer 110
`having the dummy pattern shown in FIG. 2B is formed.
`0069 Silicon dioxide (SiO2) film 42 having a thickness
`of 300-500 nm, stopper-SiCN film 43 having a thickness of
`50-70 nm, and silicon dioxide (SiO2) film 44 having a
`thickness of 300-500 nm are next successively grown over
`first upper copper layer 110. A resist pattern for forming
`via-plugs 140 is next formed on silicon dioxide (SiO2) film
`44 by means of a photolithographic process, and etching is
`carried out using this resist pattern as a mask until cap-SiCN
`
`

`

`US 2004/015O112 A1
`
`Aug. 5, 2004
`
`film 35 is exposed to form the via portions, following which
`the resist pattern is removed. A resist pattern for forming
`Second upper copper layer 120 is then formed on Silicon
`dioxide (SiO2) film 44 by a photolithographic process and
`etching is carried out using this resist pattern as a mask to
`form the dummy pattern that is shown in FIG.2B on silicon
`dioxide (SiO2) film 44. Then, after removing the resist
`pattern, cap-SiCN film 35, which is the bottom surface of the
`Vias, is removed by etching.
`0070 A barrier metal having a thickness of 30-50 nm, a
`Seed layer having a thickness of 50-100 nm, and a copper
`film having a thickness of 600-1000 nm are next formed in
`succession. The copper film is then ground by a CMP
`process until the upper Surface of Silicon dioxide (SiO2) film
`44 is exposed, following which cap-SiCN film 45 is formed
`to a thickness of 30-50 nm. In this way, Second upper copper
`layer 120 having the dummy pattern that is shown in FIG.
`2B is formed.
`0071 Silicon dioxide (SiO2) film 52 having a thickness
`of 300-500 nm is next formed on cap-SiCN film 45, and a
`resist pattern for forming openings for connecting Second
`upper copper layer 120 and bonding pad 130 is formed by
`a photolithographic process on Silicon dioxide film 52.
`Silicon dioxide (SiO) film 52 and the underlying cap-SiCN
`film 45 are next etched using the resist pattern as a mask to
`form openings. Then, after removing the resist pattern,
`titanium nitride (TiN) film 54 having a thickness of 100-200
`nm, this film being a barrier metal, an Al-Cu film (in which
`the ratio of aluminum to copper is 99.5% to 0.5%) having a
`thickness of 800-1000 nm, and titanium nitride (TiN) film 64
`having a thickness of 50-100 nm, this film being an antire
`flective coating, are Successively formed using a Sputtering
`proceSS.
`0.072 A resist pattern for forming bonding pad 130 is
`then formed on titanium nitride (TiN) film 64 by a photo
`lithographic process, following which titanium nitride (TiN)
`film 64 and the underlying Al-Cu (in which the ratio of
`aluminum to copper is 99.5% to 0.5%) film and titanium
`nitride (TiN) film 54 are subjected to etching using this resist
`pattern as a mask. The Al-Cu (0.5%) film that is left by this
`etching becomes bonding pad 130. The resist pattern is
`removed after forming bonding pad 130. Silicon dioxide
`(SiO2) film 62 is next formed to a thickness of 100-200 nm
`so as to cover TiN film 64 on bonding pad 130, following
`which polyimide film 66 is further formed to a thickness of
`800-1000 nm on silicon dioxide (SiO2) film 62.
`0.073
`Finally, a resist pattern for forming openings for
`exposing a prescribed portion of bonding pad 130 (the
`portion in which bonding is realized) is formed on polyimide
`film 66 by a photolithographic process, and using this resist
`pattern as a mask, polyimide film 66 and the underlying
`silicon dioxide (SiO2) film 62 and titanium nitride (TiN) film
`64 are etched to expose bonding pad 130. The semiconduc
`tor device of the construction shown in FIG. 2A is thus
`obtained.
`0.074 According to the semiconductor device of the
`present working example described hereinabove, a copper
`layer having greater elasticity than an oxide film (elasticity
`being the property by which force that is applied from the
`outside is repelled) is formed below bonding pad 130 with
`a barrier metal interposed, whereby a construction is
`obtained