UNITED STATES PATENT AND TRADEMARK OFFICE
`____________________________________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________________________________________
`
`Intel Corporation
`Petitioner
`
`v.
`
`VLSI Technology LLC
`Patent Owner
`
`Case IPR2019-01200
`
`DECLARATION OF JOHN C. BRAVMAN, PH.D.
`ON BEHALF OF PETITIONER
`
`Intel Exhibit 1202
`
`

`

`U.S. Patent 7,247,552
`Declaration of John C. Bravman, Ph.D.
`IPR2019-01200 (Claim 11)
`
`
`Page
`
`TABLE OF CONTENTS
`
`
`I. 
`II. 
`
`Background ...................................................................................................... 1 
`Relevant Law ................................................................................................... 5 
`A. 
`Claim Construction ............................................................................... 6 
`B. 
`Obviousness ........................................................................................... 6 
`Summary of Opinions ...................................................................................... 9 
`III. 
`IV.  Brief Description of Technology ..................................................................... 9 
`V.  Overview of the ’552 Patent .......................................................................... 13 
`A.  Alleged Prior Art Problem .................................................................. 13 
`B. 
`Alleged Invention ................................................................................ 15 
`C. 
`Relevant Prosecution History .............................................................. 16 
`VI.  Overview of the Primary Prior Art References ............................................. 17 
`A.  Overview of Oda ................................................................................. 18 
`B. 
`Overview of Cwynar ........................................................................... 25 
`C. 
`Overview of Reddy ............................................................................. 29 
`1.  Developing a Circuit Design ........................................................ 31 
`2.  Developing a Layout According to the Circuit Design ................ 31 
`3.  Modifying the Layout ................................................................... 33 
`4.  Forming the Integrated Circuit ..................................................... 35 
`D.  Overview of Owada ............................................................................. 36 
`E. 
`Overview of Vuong ............................................................................. 41 
`VII.  Claim Construction ........................................................................................ 45 
`A. 
`“force region” ...................................................................................... 46 
`VIII.  Level of Ordinary Skill In The Art ................................................................ 48 
`IX.  Specific Grounds for Petition ........................................................................ 48 
`
`i
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`

`

`A. 
`
`B. 
`
`U.S. Patent 7,247,552
`Declaration of John C. Bravman, Ph.D.
`IPR2019-01200 (Claim 11)
`
`
`Claim 11 is Obvious Over Oda in Combination with Cwynar
`and Reddy ............................................................................................ 48 
`1.  Claim 11 ....................................................................................... 49 
`a) 
`[11A] “A method of making an integrated circuit having a
`plurality of bond pads, comprising:” ............................................... 49 
`b) 
`[11B] “developing a circuit design of the integrated circuit” . 50 
`c) 
`[11C] “developing a layout of the integrated circuit according
`to the circuit design, wherein the layout comprises a plurality of
`interconnect layers underlying a first bond pad of the plurality of
`bond pads” ....................................................................................... 52 
`d) 
`[11D] “at least one of the plurality of interconnect layers not
`being electrically connected to the first bond pad and used for
`wiring or interconnect other than directly to the first bond pad” .... 59 
`e) 
`[11E] “defining a force region at least under the first bond pad
`of the plurality of bond pads, wherein the force region comprises a
`first portion of each of the plurality of interconnect layers”; ......... 62 
`f) 
`[11F] “identifying a first interconnect layer of the plurality of
`interconnect layers in which the first portion of the first
`interconnect layer has a metal density below a predetermined
`percentage” ...................................................................................... 66 
`g) 
`[11G] “modifying the layout by adding dummy metal lines to
`the first portion of the first interconnect layer to increase the metal
`density of the first portion of the first interconnect layer”.............. 72 
`h) 
`[11H] “making the integrated circuit comprising the dummy
`metal lines.” ..................................................................................... 82 
`2.  Additional Reasons to Combine Oda, Cwynar, and Reddy ......... 82 
`Ground II: Claim 11 is Obvious Over Oda in Combination with
`Owada and Vuong ............................................................................... 86 
`1.  Claim 11 ....................................................................................... 87 
`a) 
`[11A] “A method of making an integrated circuit having a
`plurality of bond pads, comprising” ................................................ 87 
`b) 
`[11B] “developing a circuit design of the integrated circuit” . 87 
`
`ii
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`

`

`U.S. Patent 7,247,552
`Declaration of John C. Bravman, Ph.D.
`IPR2019-01200 (Claim 11)
`
`
`c) 
`[11C] “developing a layout of the integrated circuit according
`to the circuit design, wherein the layout comprises a plurality of
`interconnect layers underlying a first bond pad of the plurality of
`bond pads ......................................................................................... 90 
`d) 
`[11D] “at least one of the plurality of interconnect layers not
`being electrically connected to the first bond pad and used for
`wiring or interconnect other than directly to the first bond pad” .... 93 
`e) 
`[11E] “defining a force region at least under the first bond pad
`of the plurality of bond pads, wherein the force region comprises a
`first portion of each of the plurality of interconnect layers” ........... 96 
`f) 
`[11F] “identifying a first interconnect layer of the plurality of
`interconnect layers in which the first portion of the first
`interconnect layer has a metal density below a predetermined
`percentage” ...................................................................................... 96 
`g) 
`[11G] “modifying the layout by adding dummy metal lines to
`the first portion of the first interconnect layer to increase the metal
`density of the first portion of the first interconnect layer”............101 
`h) 
`[11H] “making the integrated circuit comprising the dummy
`metal lines” ....................................................................................109 
`2.  Additional Reasons to Combine Oda, Owada, and Vuong ........ 110 
`X.  Availability for Cross-Examination ............................................................ 114 
`XI.  Right to Supplement .................................................................................... 114 
`XII.  Jurat .............................................................................................................. 115 
`
`
`
`
`iii
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`

`

`U.S. Patent 7,247,552
`Declaration of John C. Bravman, Ph.D.
`IPR2019-01200 (Claim 11)
`
`
`I, John C. Bravman, declare as follows:
`1.
`My name is John C. Bravman.
`
`I.
`
`BACKGROUND
`2.
`My academic training was at Stanford University, where I received
`
`my Bachelor of Science degree in Materials Science and Engineering in 1979, and
`
`a Master of Science degree in 1981, also in Materials Science and Engineering. I
`
`completed my Doctor of Philosophy degree in 1984, with a dissertation that
`
`focused on the nature of silicon – silicon dioxide interfaces as found in integrated
`
`circuit devices.
`
`3.
`
`From 1979 to 1984, while a graduate student at Stanford, I was
`
`employed part-time by Fairchild Semiconductor in their Palo Alto Advanced
`
`Research Laboratory. I worked in the Materials Characterization group. In 1985,
`
`upon completion of my doctorate, I joined the faculty at Stanford as Assistant
`
`Professor of Materials Science and Engineering. I was promoted to Associate
`
`Professor with tenure in 1991 and achieved the rank of Professor in 1995. In 1997
`
`I was named to the Bing Professorship.
`
`4.
`
`At Stanford, I was Chairman of the Department of Materials Science
`
`and Engineering from 1996 to 1999, and Director of the Center for Materials
`
`Research from 1998 to 1999. I served as Senior Associate Dean of the School of
`
`1
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`

`

`Engineering from 1992 to 2001 and the Vice Provost for Undergraduate Education
`
`U.S. Patent 7,247,552
`Declaration of John C. Bravman, Ph.D.
`IPR2019-01200 (Claim 11)
`
`
`from 1999 to 2010. On July 1, 2010, I retired from Stanford University and
`
`assumed the Presidency of Bucknell University, where I also became a Professor
`
`of Electrical Engineering.
`
`5.
`
`I have worked for more than 25 years in the areas of thin film
`
`materials processing and analysis. Much of my work has involved materials for use
`
`in microelectronic interconnects and packaging, and in superconducting structures
`
`and systems. With regard to integrated circuits, I led investigations involving
`
`aluminum, copper and tungsten metallizations, polycrystalline silicon, metal
`
`silicides, a variety of oxide and nitride dielectrics, and barrier layers such as
`
`titanium and tantalum-based nitrides. Further, my groups blended fundamental
`
`aspects of the behavior of microelectromechanical systems—specifically,
`
`compliant multilayer cantilever beams—for possible test probe and package
`
`implementations. In this work my group investigated the mechanical behavior of
`
`package underfill systems, focusing on the relationship between microstructures,
`
`processing, and adhesion. I have also led multiple development efforts of
`
`specialized equipment and methods for determining the microstructural and
`
`mechanical properties of materials and structures. My groups designed and built
`
`the first high voltage SEM for in-situ studies of electromigration, the first high
`
`2
`
`

`

`temperature wafer curvature system, and the first microtensile tester for micron-
`
`U.S. Patent 7,247,552
`Declaration of John C. Bravman, Ph.D.
`IPR2019-01200 (Claim 11)
`
`
`scale structures, amongst many others. As a graduate student I developed one of
`
`the earliest methodologies for obtaining high resolution cross section transmission
`
`electron micrographs of integrated circuit structures.
`
`6.
`
`I have taught a wide variety of courses at the undergraduate and
`
`graduate level in materials science and engineering, emphasizing both basic
`
`science and applied technology, including coursework in the areas of integrated
`
`circuit materials and processing. Some of these courses focused on processes (e.g.,
`
`cleaning, etching, deposition, doping, oxidation, etc.) used in the production of
`
`integrated circuits. More than two thousand students have taken my classes, and I
`
`have trained 24 doctoral students, most of whom now work in the microelectronics
`
`industry.
`
`7.
`
`I am a member of many professional societies, including the Materials
`
`Research Society, the Institute of Electrical and Electronic Engineers, the
`
`American Society of Metals, and the American Physical Society. I served as
`
`President of the Materials Research Society in 1994.
`
`8.
`
`A copy of my curriculum vitae (including a list of all publications
`
`authored in the previous 10 years) is attached as Appendix A.
`
`
`
`3
`
`

`

`U.S. Patent 7,247,552
`Declaration of John C. Bravman, Ph.D.
`IPR2019-01200 (Claim 11)
`
`
`I have reviewed the specification, claims, and file history of U.S.
`
`9.
`
`Patent No. 7,247,552 (“the ’552 patent”) (Ex. 1201). I understand that the ’552
`
`patent was filed on January 11, 2005 as U.S. Patent Application No. 11/033,009.
`
`10.
`
`I have also reviewed the following references, all of which I
`
`understand to be prior art to the ’552 patent:
`
`1.
`
`U.S. Patent Publication No. 2004/0150112, titled “Semiconductor
`
`Device and Method of Fabrication Same” (“Oda”) (Ex. 1203), filed on
`
`January 22, 2004.
`
`2.
`
`U.S. Patent Publication No. 2002/0162082, titled “Method for Making
`
`an Interconnect Layer and a Semiconductor Device Including the
`
`Same” (“Cwynar”) (Ex. 1204), filed on May 16, 2002.
`
`3.
`
`“Digital Design Flow Options,” Sagar V. Reddy, M.S. Thesis, 2001
`
`(“Reddy”) (Ex. 1205), which was made available to the public on
`
`April 15, 2002.
`
`4.
`
`U.S. Patent No. 5,027,188, titled “Semiconductor Integrated Circuit
`
`Device in Which a Semiconductor Chip is Mounted with Solder
`
`Bumps for Mounting to a Wiring Substrate” (“Owada”) (Ex. 1206),
`
`filed on September 13, 1989.
`
`5.
`
`U.S. Patent Publication No. US 2004/0098674, titled “Place and
`
`4
`
`

`

`U.S. Patent 7,247,552
`Declaration of John C. Bravman, Ph.D.
`IPR2019-01200 (Claim 11)
`
`
`Route Tool That Incorporates Metal-Fill Mechanism” (“Vuong”) (Ex.
`
`1207), filed on November 19, 2002.
`
`11.
`
`I have also reviewed the exhibits and references cited in this
`
`Declaration.
`
`12.
`
`I have considered certain issues from the perspective of a person of
`
`ordinary skill in the art as described below at the time the ’552 patent application
`
`was filed.
`
`13.
`
`I have been retained by the Petitioner as an expert in the field of
`
`semiconductor device fabrication and design. I am working as an independent
`
`consultant in this matter and am being compensated at my normal consulting rate
`
`of $550 per hour for my time. My compensation is not dependent on and in no
`
`way affects the substance of my statements in this Declaration.
`
`14.
`
`I have no financial interest in the Petitioner. I similarly have no
`
`financial interest in the ’552 patent and have had no contact with the named
`
`inventor of the ’552 patent.
`
`II. RELEVANT LAW
`15.
`I am not an attorney. For the purposes of this declaration, I have been
`
`informed about certain aspects of the law that are relevant to my opinions. My
`
`understanding of the law is as follows:
`
`5
`
`

`

`U.S. Patent 7,247,552
`Declaration of John C. Bravman, Ph.D.
`IPR2019-01200 (Claim 11)
`
`
`A. Claim Construction
`16.
`I have been informed that claim construction is a matter of law and
`
`that the final claim construction will ultimately be determined by the Board. For
`
`the purposes of my analysis in this proceeding and with respect to the prior art, I
`
`have been informed that IPRs are currently reviewed under “the Phillips standard.”
`
`17.
`
`I have been informed that under the Phillips standard, claim terms are
`
`given their plain and ordinary meaning as understood by a person of ordinary skill
`
`in the art at the time of the invention in light of the claim language and the patent
`
`specification.
`
`18.
`
`I have been informed that embodiments described in the specification
`
`are encompassed by the claim terms.
`
`19.
`
`I have been informed that the patentee can serve as their
`
`lexicographer. As such, if a claim term is provided with a specific definition in the
`
`specification, I should interpret that claim term in light of the particular definition
`
`provided by the patentee.
`
`B. Obviousness
`20.
`I have been informed and understand that a patent claim can be
`
`considered to have been obvious to a person of ordinary skill in the art at the time
`
`the application was filed. This means that, even if all of the requirements of a
`
`6
`
`

`

`claim are not found in a single prior art reference, the claim is not patentable if the
`
`U.S. Patent 7,247,552
`Declaration of John C. Bravman, Ph.D.
`IPR2019-01200 (Claim 11)
`
`
`differences between the subject matter in the prior art and the subject matter in the
`
`claim would have been obvious to a person of ordinary skill in the art at the time
`
`the application was filed.
`
`21.
`
`I have been informed and understand that a determination of whether
`
`a claim would have been obvious should be based upon several factors, including,
`
`among others:
`
` the level of ordinary skill in the art at the time the application was filed;
`
` the scope and content of the prior art; and
`
` what differences, if any, existed between the claimed invention and the
`
`prior art.
`
`22.
`
`I have been informed and understand that the teachings of two or
`
`more references may be combined in the same way as disclosed in the claims, if
`
`such a combination would have been obvious to one having ordinary skill in the
`
`art. In determining whether a combination based on either a single reference or
`
`multiple references would have been obvious, it is appropriate to consider, among
`
`other factors:
`
`7
`
`

`

`U.S. Patent 7,247,552
`Declaration of John C. Bravman, Ph.D.
`IPR2019-01200 (Claim 11)
`
`
` whether the teachings of the prior art references disclose known concepts
`
`combined in familiar ways, which, when combined, would yield
`
`predictable results;
`
` whether a person of ordinary skill in the art could implement a
`
`predictable variation, and would see the benefit of doing so;
`
` whether the claimed elements represent one of a limited number of
`
`known design choices, and would have a reasonable expectation of
`
`success by those skilled in the art;
`
` whether a person of ordinary skill would have recognized a reason to
`
`combine known elements in the manner described in the claim;
`
` whether there is some teaching or suggestion in the prior art to make the
`
`modification or combination of elements claimed in the patent; and
`
` whether the claim applies a known technique that had been used to
`
`improve a similar device or method in a similar way.
`
`23.
`
`I understand that one of ordinary skill in the art has ordinary creativity
`
`and is not an automaton.
`
`24.
`
`I understand that in considering obviousness, it is important not to
`
`determine obviousness using the benefit of hindsight derived from the patent being
`
`considered.
`
`8
`
`

`

`U.S. Patent 7,247,552
`Declaration of John C. Bravman, Ph.D.
`IPR2019-01200 (Claim 11)
`
`
`III. SUMMARY OF OPINIONS
`25.
`It is my opinion that every limitation of the method described in claim
`
`11 of the ’552 patent is disclosed by the prior art, and that claim 11 is rendered
`
`obvious by the prior art.
`
`IV. BRIEF DESCRIPTION OF TECHNOLOGY
`26.
`Integrated circuits contain millions or even billions of tiny electronic
`
`components (e.g., transistors). These transistor structures are typically formed in
`
`and over a semiconducting substrate, such as silicon. Electrically connecting these
`
`millions or even billions of tiny transistor structures with one another so that they
`
`can electrically communicate with each other also requires millions or billions of
`
`electrically conductive pathways. To form these interconnects, engineers have
`
`layered electrically-conductive (e.g., metal) structures over one another,
`
`surrounding them with dielectric/insulating materials for electrical insulation.
`
`27.
`
`Figure 1 of the ’552 patent, which I have colored below, is one
`
`exemplary arrangement of such an interconnect structure shown in a cross-
`
`sectional view:
`
`9
`
`

`

`U.S. Patent 7,247,552
`Declaration of John C. Bravman, Ph.D.
`IPR2019-01200 (Claim 11)
`
`
`
`
`Ex. 1201 [the ’552 patent] at Fig. 1.
`
`28.
`
`Specifically, the electrical components, such as transistors (not
`
`shown), are formed in and on the substrate 12. Over the substrate are shown the
`
`alternating layers of interconnect layers. For example, a first metal interconnect
`
`layer 26 containing conductive materials 56, 58, 60 is shown. Those conductive
`
`materials are shown in side-view and run in a direction perpendicular to the cross-
`
`section, so that they can provide electrical pathways for electricity to flow. These
`
`10
`
`

`

`electrical pathways can carry electrical signals or power. Moreover, these
`
`U.S. Patent 7,247,552
`Declaration of John C. Bravman, Ph.D.
`IPR2019-01200 (Claim 11)
`
`
`conductive materials are electrically isolated from each other by dielectric material
`
`62. Ex. 1201 [the ’552 patent] at 3:35-38. One example, among many, of a
`
`conductive material is copper and one example, among many, of a dielectric
`
`material is silica.
`
`29.
`
`In addition to the metals running in a direction perpendicular to the
`
`cross-section, the metals can also run vertically by introducing structures called
`
`vias. To form such vias, metal interconnect layer 26 can be polished, and
`
`interlevel dielectric layer 24 can be deposited on top of that metal layer. Vertical
`
`pathways connecting the wires in first metal interconnect layer 26 to wires in one
`
`or more different metal interconnect layers are then formed in the interlevel
`
`dielectric layer 24 to create via 59 (purple), over with the metal interconnect layer
`
`22 is formed so that conductive material 50 is electrically connected to the
`
`conductive material 58. This process of forming alternating metal interconnect
`
`layers 22, 18 and 14 and interlevel dielectric layers 20 and 16 is then repeated.
`
`Ex. 1201 [the ’552 patent] at 2:64-67, 3:9-10, 3:35-38, Fig. 1.
`
`30. When all the desired layers of the integrated circuit are formed, the
`
`top interconnect metal layer can be used to make electrical connections to other
`
`external components (e.g., to other components on a printed circuit board or other
`
`11
`
`

`

`semiconductor devices). The metals in the top interconnect metal layer used to
`
`U.S. Patent 7,247,552
`Declaration of John C. Bravman, Ph.D.
`IPR2019-01200 (Claim 11)
`
`
`make such external connections are generally called “bond pads” because they
`
`serve as a pad to form bonds with additional metal structures that are placed
`
`thereon. For example, the ’552 patent explains that some examples of these pads
`
`include “wire bond pad, a probe pad, a flip-chip bump pad, a test point or other
`
`packaging or test pad structures.” Ex. 1201 [the ’552 patent] at 2:42-45. As an
`
`example, Figure 1 shows a conductive ball 28 on bond pad 32. Ex. 1201 [the ’552
`
`patent] at 3:10-12, 3:20-25.
`
`31.
`
`These interconnects that electrically connect different electrical
`
`components (e.g., transistors) together to deliver electrical signals/power are often
`
`called “active” metal interconnects. In addition, “dummy” metals are often added
`
`as “filler” material. These dummy metals are often not electrically connected to
`
`other metal structures – hence, they electrically “float.” Nevertheless, dummy
`
`structures can be connected to other metal structures. For example, dummy metals
`
`can be connected to another dummy metal in a different layer through a via.
`
`Alternatively, a dummy metal can be connected to a dummy bond pad through a
`
`via. Engineers have long been adding such “dummy” metal fillers because they
`
`can provide a number of desired effects. For example, it was well-known that
`
`adding dummy fillers can provide added structural protection to certain areas of the
`
`12
`
`

`

`integrated circuit as metals provide more mechanical robustness compared to
`
`U.S. Patent 7,247,552
`Declaration of John C. Bravman, Ph.D.
`IPR2019-01200 (Claim 11)
`
`
`potentially brittle dielectric materials. As another example, it was well-known that
`
`the rate of polishing can be controlled by introducing a desired amount of metal,
`
`which can ultimately lead to improved planarity of the interconnect layers during
`
`polishing.
`
`32.
`
`Building an integrated circuit typically begins with a high-level design
`
`idea that addresses the desired functionality of the circuit. After the idea is formed,
`
`a series of design steps are undertaken, including: (1) developing a circuit design;
`
`(2) developing a layout corresponding to the circuit design; and (3) modifying the
`
`layout to comply with design rules. Long before the ’552 patent, computer aided
`
`design (“CAD”) tools were used for these design steps. Ex. 1215 [U.S. 4,922,432]
`
`at 1:45-58 (“CAD techniques have been used with success in design and
`
`verification of integrated circuits, at both the structural level and at the physical
`
`layout level.”). After the design phase is complete, the integrated circuit is then
`
`fabricated according to the modified layout.
`
`V. OVERVIEW OF THE ’552 PATENT
`A. Alleged Prior Art Problem
`33.
`The ’552 patent notes that “[t]he use of conductive balls, such as
`
`solder balls, to make electrical connection to a bond pad is a known method to
`
`13
`
`

`

`make electrical connection to electrical circuitry of a semiconductor die.” Ex.
`
`U.S. Patent 7,247,552
`Declaration of John C. Bravman, Ph.D.
`IPR2019-01200 (Claim 11)
`
`
`1201 [the ’552 patent] at 1:25-28. The ’552 patent further notes that “[b]ecause the
`
`advanced low-k interlayer dielectrics used today have a lower dielectric constant
`
`and lower Young's modulus than dielectrics used in earlier generation products,
`
`flip chip die attach may more easily mechanically fracture the underlying stack of
`
`metal and dielectric layers.” Ex. 1201 [the ’552 patent] at 1:42-46. Moreover,
`
`the ’552 patent notes that “[a] known method to address the stresses present
`
`underlying a bond pad is to use a dedicated support structure. A common structure
`
`is the use of at least two metal layers under the bonding pad that are connected
`
`together and to the bonding pad by large arrays of vias distributed across a
`
`majority of the bond pad area.” Ex. 1201 [the ’552 patent] at 1:53-58.
`
`Furthermore, the ’552 patent notes that “[a]nother known method of mitigating
`
`stresses in a bond pad region is to replace low-k dielectric layers with higher k
`
`dielectric and higher elastic modulus dielectric layers until the die exhibits
`
`resistance to cracking.” Ex. 1201 [the ’552 patent] at 1:65-2:4. The ’552 patent,
`
`however, notes that the shrinking die sizes and more brittle dielectric materials
`
`render them more susceptible to damage due to the “increased stress to the bond
`
`pad structure when physical connection is made to the semiconductor die.” Ex.
`
`1201 [the ’552 patent] at Abstract, 1:33-35.
`
`14
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`

`

`U.S. Patent 7,247,552
`Declaration of John C. Bravman, Ph.D.
`IPR2019-01200 (Claim 11)
`
`
`B. Alleged Invention
`34.
`The ’552 patent alleges that such problems can be solved by first
`
`defining a “force region” that is beneath and around the bond pad, and adding
`
`“dummy” metal lines in the interconnect layers to “increase the metal density of
`
`the interconnect layers.” Ex. 1201 [the ’552 patent] at Abstract, 4:37-56.
`
`Challenged claim 11, reproduced below, is directed to a method that requires
`
`developing a design and layout for an integrated circuit, “modifying the layout by
`
`adding dummy metal lines to the first portion of the first interconnect layer to
`
`increase the metal density of the first portion of the first interconnect layer,” and
`
`then making the integrated circuit comprising the dummy metal lines:
`
`11. A method of making an integrated circuit having a plurality of
`bond pads, comprising:
`developing a circuit design of the integrated circuit;
`developing a layout of the integrated circuit according to the
`circuit design, wherein the layout comprises a plurality of interconnect
`layers underlying a first bond pad of the plurality of bond pads, at
`least one of the plurality of interconnect layers not being electrically
`connected to the first bond pad and used for wiring or interconnect
`other than directly to the first bond pad;
`defining a force region at least under the first bond pad of the
`plurality of bond pads, wherein the force region comprises a first
`portion of each of the plurality of interconnect layers;
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`15
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`

`

`U.S. Patent 7,247,552
`Declaration of John C. Bravman, Ph.D.
`IPR2019-01200 (Claim 11)
`
`
`identifying a first interconnect layer of the plurality of
`interconnect layers in which the first portion of the first interconnect
`layer has a metal density below a predetermined percentage;
`modifying the layout by adding dummy metal lines to the first
`portion of the first interconnect layer to increase the metal density of
`the first portion of the first interconnect layer; and
`
`making the integrated circuit comprising the dummy metal
`lines.
`
`Ex. 1201 [the ’552 patent] at claim 11.
`
`35.
`
`In my opinion, claim 11 is not patentable as being obvious. As I
`
`explain below, the approach of claim 11 was well-known and disclosed in the prior
`
`art—including by (1) Oda, which teaches using “dummy patterns” in interconnect
`
`layers; (2) Owada, which teaches adding “dummy lines;” (3) Cwynar, which
`
`teaches using “lines or traces” in regions that it calls “dummy fill features,” (4)
`
`Reddy, which teaches a process for designing an integrated circuit, and (5) Vuong,
`
`which also describes integrated circuit design processes, including adding dummy
`
`“metal fill” to increase metal density.
`
`C. Relevant Prosecution History
`36.
`I have been informed that the ’552 patent issued from U.S. Patent
`
`Application No. 11/033,009, filed January 11, 2005. I understand that during
`
`prosecution, the Examiner initially rejected all originally-filed claims over U.S.
`
`16
`
`

`

`U.S. Patent 7,247,552
`Declaration of John C. Bravman, Ph.D.
`IPR2019-01200 (Claim 11)
`
`
`Patent Application Publication No.
`
`2005/0082577 (“Usui”). Ex. 1208 [Jan. 24, 2007 Non-Final Rejection] at 3-7. I
`
`further understand that the applicant amended (among other things) challenged
`
`claim 11 to add the following underlined language and remove the bracketed
`
`language:
`
`wherein the layout comprises a plurality of interconnect layers
`underlying a first bond pad of the plurality of bond pads, at least one
`of the plurality of interconnect layers not being electrically connected
`to the first bond pad and used for wiring or interconnect other than
`directly to the first bond pad; defining a force region [[around and]] at
`least under [[a]] the first bond pad of the plurality of bond pads.
`
`Ex. 1209 [Apr. 5, 2007 Response to Office Action] at 5.
`
`37.
`
`I further understand that the Examiner allowed claim 11 as amended,
`
`Ex. 1210 [May 25, 2007 Notice of Allowability] at 2.
`
`VI. OVERVIEW OF THE PRIMARY PRIOR ART REFERENCES
`38.
`In my opinion, there is nothing novel or inventive in claim 11 of
`
`the ’552 patent. The claimed method of making an integrated circuit was well-
`
`known in the art. This is demonstrated by the prior art that is relied upon in my
`
`declaration. For example, Reddy and Vuong demonstrate the well-known fact that
`
`17
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`

`

`making an integrated circuit involved a series of design flow steps. This overall
`
`U.S. Patent 7,247,552
`Declaration of John C. Bravman, Ph.D.
`IPR2019-01200 (Claim 11)
`
`
`concept is ubiquitous in the production of almost all complex systems. Indeed, as
`
`recognized in the seminal work by Mead and Conway, Introduction to VLSI
`
`Systems, published in 1980, “Wafer fabrication is probably the most exacting
`
`production process ever developed.” Ex. 1217 [Mead] at 38. As part of that design
`
`flow, adding dummy metal lines to a layout was well-known, as demonstrated by
`
`Oda, Cwynar, and Owada. My opinions are discussed in greater detail below, but
`
`I, first, provide brief summaries of the prior art references: Oda, Cwynar, Reddy,
`
`Owada, and Vuong.
`
`A. Overview of Oda
`39.
`Oda, like the ’552 patent, notes that mechanical damage, such as
`
`cracking, can occur below the bond pad when load is applied to the bond pad. Ex.
`
`1203 [Oda] at [0005] (“As a result, stress that occurs when bonding is exerted upon
`
`passivation insulation film 740 and interlevel dielectric film 750 that underlie
`
`bonding portion 735. The influence of stress upon copper interconnect 700 during
`
`bonding can thus be reduced and the exposure of copper interconnects 700 on the
`
`surface can be prevented..”); Ex. 1203 [Oda] at [0008] (“Further, if a low-k film
`
`that has a lower relative dielectric constant than an oxide film is present below the
`
`bonding portion, the load of a needle during probing or bonding depresses the
`
`18
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`

`

`bonding pads and may cause cracks in the interlevel dielectric film that underlies
`
`U.S. Patent 7,247,552
`Declaration of John C. Bravman, Ph.D.
`IPR2019-01200 (Claim 11)
`
`
`the bonding pads or may cause film to peel in the bonding pads.”); Ex. 1203 [Oda]
`
`at Abstract.
`
`40.
`
`Oda addresses this issue by adding “dummy” metal patterns below a
`
`bond pad—which improves the mechanical integrity of the are