Trials@uspto.gov
`571-272-7822
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`Paper # 48
`Entered: January 14, 2021
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`INTEL CORPORATION,
`Petitioner,
`
`v.
`
`VLSI TECHNOLOGY LLC,
`Patent Owner.
`____________
`
`IPR2019-01198, IPR2019-01199, IPR2019-01200,
`Patent 7,247,522 B2
`____________
`
`Record of Oral Hearing
`Held: November 2, 2020
`____________
`
`Before THU A. DANG, LYNNE E. PETTIGREW, and KIMBERLY
`MCGRAW, Administrative Patent Judges.
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`
`
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`

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`IPR2019-01198, IPR2019-01199, IPR2019-01200
`Patent 7,247,552 B2
`
`
`APPEARANCES:
`
`ON BEHALF OF THE PETITIONER:
`
`
`S. CALVIN WALDEN, ESQUIRE
`JOHN HOBGOOD, ESQUIRE
`Wilmer Hale
`2445 M St, N.W., Suite 500
`Washington, D.C. 20037
`
`
`ON BEHALF OF THE PATENT OWNER:
`
`
`BRIDGET SMITH, ESQUIRE
`FLAVIO ROSE, ESQUIRE
`EDWARD HSIEH, ESQUIRE
`Lowenstein and Weatherwax
`1880 Century Park, E, Suite 815
`Los Angeles, CA 90067
`
`
`
`
`The above-entitled matter came on for hearing on Monday,
`November 2, 2020 by video/by telephone.
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`IPR2019-01198, IPR2019-01199, IPR2019-01200
`Patent 7,247,552 B2
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`
`P R O C E E D I N G S
`- - - - -
`JUDGE MCGRAW: We will now hear argument for three related
`inter parte review trials, which are IPR2019-01198, IPR2019-01199, and
`IPR2019-01200, each involving U.S. Patent Number 7,247,552. Intel
`Corporation is the Petitioner and VLSI Technology LLC is the Patent
`Owner. I am Judge McGraw. With me on the panel are Judge Pettigrew and
`Judge Dang. Let's begin with party appearances, starting with the petitioner.
`MR. HOBGOOD: Good afternoon, Your Honors. This is John
`Hobgood with Wilmer Hale. And I'm here with my colleague Calvin
`Walden. And we represent Petitioner Intel Corporation.
`JUDGE MCGRAW: Hello, Mr. Hobgood. Who will be presenting
`today?
`MR. HOBGOOD: Mr. Walden will be making the argument today,
`Your Honor.
`JUDGE MCGRAW: Thank you very much. And Patent Owner?
`MS. SMITH: This is Bridget Smith for VLSI. With me on the phone
`is Nathan Lowenstein and Edward Hsieh.
`JUDGE MCGRAW: Thank you, all. And --
`MS. SMITH: And I'll be presenting.
`JUDGE MCGRAW: Thank you and welcome back. Well, we did put
`our procedure in the Hearing Order, but to make sure that we're all on the
`same page, I'm going to run through the procedure again quickly. All of the
`cases will be argued together as requested by the parties. Each side will
`have a total of 90 minutes. You may allocate those minutes among the cases
`as you wish. We are not going to break up the transcript among the cases.
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`IPR2019-01198, IPR2019-01199, IPR2019-01200
`Patent 7,247,552 B2
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`Rather, the transcript of this afternoon's hearing will be submitted in each of
`the three cases. Petitioner has the burden and will argue first and may
`reserve time for rebuttal. Patent Owner will then argue its opposition.
`Petitioner may then use its reserved time to respond to Patent Owner's
`arguments and thereafter, Patent Owner may present a brief sur-rebuttal.
`As you're aware, we are holding this conference through a video
`conference. Our primary concern is everyone's right to be heard. If at any
`time during the hearing you encounter any difficulties that might undermine
`your ability to represent your client, please let us know immediately such as
`by contacting the team members who provided you with the connection
`information. Again, when referring to demonstratives, please be sure to
`identify what slide number you are on so that we can all follow along. And
`again, although we do not expect any confidential information to be
`discussed today, please be aware that this transcript will be made public in
`the record and that members of the public may be attending through an audio
`connection.
`Does anyone have any questions about these procedures? With that, I
`invite Mr. Walden to begin. Mr. Walden, how much time would you like to
`reserve for your rebuttal? You do not --
`MR. HOBGOOD: Calvin, I think you're also muted on the Web
`interface.
`JUDGE MCGRAW: Okay, now we hear, I believe that's Mr.
`Hopbood that we hear. Is Mr. Walden?
`MR. HOBGOOD: It is, Your Honor. I just received something from
`Mr. Walden that although we can see him, he doesn't appear to be seeing or
`hearing either of us.
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`IPR2019-01198, IPR2019-01199, IPR2019-01200
`Patent 7,247,552 B2
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`SPEAKER: He's hard muted. Let me unmute him. I'm not sure how
`
`he --
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`MR. HOBGOOD: Okay.
`SPEAKER: -- if I can. I'm trying, requesting it. Mr. Walden, are you
`there? Sir, can you speak? I don't think he can hear but it says he's on a
`phone connection. I’m trying group chat. Standby.
`MR. WALDEN: Can folks hear me?
`JUDGE MCGRAW: We can hear you and see you.
`MR. WALDEN: Sorry, I apologize for that.
`JUDGE MCGRAW: That fine. We ran through the procedures.
`Were you able to hear the procedures that I reviewed?
`MR. WALDEN: I did. I was, Your Honor.
`JUDGE MCGRAW: Okay. How much time would you like to
`reserve for your rebuttal?
`MR. WALDEN: Fifteen minutes, once again.
`JUDGE MCGRAW: Okay, please begin whenever you are ready.
`MR. WALDEN: Thank you. My name is Calvin Walden. And along
`with lead counsel, John Hobgood, we represent the Petitioner Intel. I'd like
`to present argument for the three petitions relating to the patent we're here to
`discuss, the '552 patent, which is 7,247,552.
`I'll start with the first Petition, which is the 01198 Petition. And I will
`refer to my slide, if you would, to Slide No. 2. As an overview of the slide
`that we have presented for the '552 patent today. We have provided an
`overview for each of three IPRs, but I'd note that the disputes with respect to
`IPRs 01198 and 01200 for Claims 1 and 2 and Claim 11 respectively
`overlap. Thus, unless the Board has any particular questions pertaining to
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`IPR2019-01198, IPR2019-01199, IPR2019-01200
`Patent 7,247,552 B2
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`IPR-01200, I do not plan to dwell on Claim 11. And our position is that the
`arguments made with respect to Claims 1 and 2 and IPR-01198 apply
`equally to Claim 11 and IPR-01200. Claim 20 does have one unique issue
`and that is in IPR2019-01199, which I'll address after Claims 1 and 2.
`Please turn to Slide 4, please. So, I'll start with an overview of the
`'552 patent before turning to the claims the prior art and then to the Patent
`Owner's argument. The '552 patent is dated 2007 from an application filed
`in 2005. There's no dispute that the prior art discussed in the petitions and
`addressed today is, in fact, prior art. The only disputes are what does the art
`disclose and whether certain references may be combined.
`This is a patent, the '552 patent, covering an integrated circuit with
`bond pads and layers beneath those bond pads. The abstract note that the
`patent provides the technique for alleviating the problems of defects caused
`by stress applied to the bond pads. The patent describes adding dummy
`layers -- or dummy metal lines -- I'm sorry -- to layers below bond pads to
`increase the metal density of those layers and reinforce them so that they can
`withstand the stresses caused to the bond pads when electrical attachments
`are made to them.
`Turning to Slide 5. So, we're showing Figure 1 from the '552 patent,
`which is a figure of an integrated circuit where if you take out a chip or an
`integrated circuit, slice it, and then you look at it from the side view, this is
`what we're looking at. There's a solder ball also called conductive bump 28
`on the in dark green. Below it is bond pad 32 in red. That bond pad and
`solder ball are the electrical connection between the chip to the outside
`world. And those connections are used to transmit data, both input and
`output, as well as power and ground.
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`IPR2019-01198, IPR2019-01199, IPR2019-01200
`Patent 7,247,552 B2
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`At the bottom as you see in this figure, is the substrate where the
`transistors and the main components of the integrated circuit lie that is
`substrate 12. Below the bond pad and above the substrate are multiple
`layers 14 to 26. These are the interconnect layers. They're used to transmit
`the data and power from the bond pads down to the substrate and up again.
`They are also used to connect components on the substrate to each other.
`As you can see, the layers alternate between being predominately
`lighter green and the layers with both the light green and the blue with
`stripes. The light green is the dielectric, which is the non-conductive layers,
`and serves to insulate the metals in the interconnect layers. So, you will see
`they also contain vias such as you can see with 59. The vias are used to
`connect the metal in the metal layers across the dielectric. The darker blue
`are the metals in the interconnect layers. Note though, even in these layers
`that are often called metal layers, there is dielectric, which serves to separate
`and insulate the metal wires on those layers.
`Figure 1 also shows the via that connects the two, the metal between
`two different layers. At the bottom you then see 64 with the arrows right
`and left showing a force region. This is the region below the bond pad in
`which forces are exerted when a die attach is performed. And that is when
`the electrical connections are being made to the bond pad and the bump
`above putting pressure, heat coming down from that bond pad and the device
`being used to connect it from above and causing stresses below the bond pad
`in this area that's labeled here in 64 called the force region.
`If you'll turn to Slide 6. So, this is Figure 2 from the '552 patent. And
`this shows a top-down view of one of the metal interconnect layers, layer 26,
`showing it showing the force region area of that layer. Now, we're looking
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`IPR2019-01198, IPR2019-01199, IPR2019-01200
`Patent 7,247,552 B2
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`at the integrated circuit from a top-down view. This is the portion of the
`layer underneath one of the bond pads. Metal line 66, 68, 70, et cetera, are
`shown in blue with the stripe. The dielectric material in 62 is shown in light
`green. And you'll note there's a fairly high ratio of dielectric to metal as
`shown. So, the metal density ratio or percentage in this figure is relatively
`low.
`
`If you'll turn to the next Slide 7. We show Figure 3 from the '552
`patent and now we see, again, the force region that we saw from Figure 2 in
`which dummy lines have been added to raise the metal density of this area in
`the force region underneath the bond pad. The dummy lines are shown here
`in light red with stripes. You can see the dummy lines position horizontally,
`for example, dummy line number 75, which is labeled on the upper right.
`You can also see them positioned vertically, so, such as 77 on the left and a
`couple of dummy lines down at the bottom that are positioned vertically.
`Next slide, please, 8. So, that's what the patent covers. The first parts
`of the claims and we're looking at Claim 1, covers standard integrated circuit
`components. Thus, there's no surprise that the integrated circuit prior art the
`Petitioner relies on and that is at issue in this case, covers the limitation and
`there are really no disputes about those. So, there's no dispute that there is a
`substrate having integrated active circuitry in the prior art reference as a
`bond pad over the substrate. There is a dispute over a force region. But
`there's no dispute that there is a region below the bond pads in the art and
`which forces are exerted. There is no dispute that there's a stack of
`interconnect layers and that their plurality of interlayer dielectric.
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`IPR2019-01198, IPR2019-01199, IPR2019-01200
`Patent 7,247,552 B2
`
`
`We get to disputes down near the bottom, but the large portion of the
`claim limitations are not in dispute. And unless the Board has any specific
`questions about them, I'll move on to the more disputed limitations.
`Claim 9 -- I'm sorry, Slide 9, if you would. Finally, we get to the final
`wherein clause which requires that one of the interconnect layers comprises
`functional metal line underlying the bond pad. And if we're looking at
`Figure 3, that would be something like lines 58 or 70. Dummy lines -- and
`those would be the 75 or 77, et cetera, that are in the -- that are both in this
`force region. The upshot is that there needs to be functional metal lines and
`dummy lines underneath the bond pad. And we submit that the prior art
`shows that.
`We'll move on to the art and if the Board would turn to Slide 11. This
`is just a quick summary of the Board's institution -- Decision on Institution.
`There were three grounds that had been asserted by the Petitioner in the
`Petition for Claims 1 and 2, and similarly for Claim 11. And then there's a
`slight difference on Claim 20, and I'll address that.
`The Board agreed that there was a reasonable likelihood of success on
`all of the three grounds that we're respecting Claims 1 and 2. Oda is the
`primary reference that has been relied upon by the Petitioner for all of these
`grounds. Note that when the Petition and Patent Owner's Preliminary
`Response were filed, parties were disputing the meaning of the term, force
`region. The Board did not decide on a meaning for force region but decided
`that the Petition has shown a force region under either party's construction.
`The parties though now agree on a construction for the term, force region,
`which is a region in the integrated circuit in which forces are exerted on the
`interconnect structure when a die attach is performed. But there's a
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`IPR2019-01198, IPR2019-01199, IPR2019-01200
`Patent 7,247,552 B2
`
`disagreement on the meaning of what a die attach is and whether it applies in
`the context of wire bonding, which we will address.
`JUDGE MCGRAW: Do you agree that a die attach has to be
`performed to the integrated circuit under this definition of force region?
`MR. WALDEN: We would, Your Honor. I mean, the definition is
`when a die attach is performed. And the die attach is the process of creating
`an electrical attachment to the bond pad above the region. So, there has to
`be that electrical attachment to the integrated circuit that's being made from
`the bond pad and the ball above it to the outside world. So, that is the die
`attach. So, yes, we would say that this definition requires it. We would
`definitely say that that covers the wire bonding, which we'll get to. But I
`think in answer to specifically your question, we do agree that it needs to be
`-- there needs to be a die attach being performed.
`So, I'll turn to the Oda reference, unless there's any other questions
`about that. And I'll return back to how we submit that Oda teaches the die
`attach in terms of wire bonding. But I'll start with just a quick explanation
`of what Oda shows. And now, I'm looking at Slide 12. Here we have
`Figure 1 from the '552 patent on the left and Oda's Figure 2A on the right.
`Oda, like the '552 patent, covers an integrated circuit with bond pads, a
`substrate, and interconnect layers. You can see from the '552 figure on the
`left and Oda on the right other similarities. The top is the bond pad. Below
`are a mix of metal and dielectric layers. And at the bottom is a substrate.
`And both describe the fact that there can be both dummy materials and
`active metal materials underneath the bond pads at the same time or in
`different layers.
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`IPR2019-01198, IPR2019-01199, IPR2019-01200
`Patent 7,247,552 B2
`
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`If you'll turn to Slide 13, please. Like the '552 patent, Oda also
`describes adding dummy metal patterns below the bond pad to reinforce the
`structure. As Oda states in paragraph 55, the layers of lower copper layer
`200 can function as dummy layers for distributing the shock applied to
`bonding pad 130. These shocks occur as Oda notes in paragraph 74, during
`the probing and bonding. That is during the electrical bonding of the wires
`of the bond pad to the bond pads of the carrier or other device that the
`integrated circuit of Oda's being connected to.
`So, if we turn back to Slide 14, we can see that Oda discloses the
`limitations of Claim 1, 1A through 1F. And to the extent that there's any
`doubts about 1G and 1H, Oda discloses patterns. Oda discloses that the
`pattern -- Oda teaches that the patterns that it discloses are not limiting, that
`other patterns can be chosen. The Petitioner has demonstrated that lines are
`one of the most common forms of patterns and would be an obvious choice
`to be used with Oda. But to the extent there's any concern that there's no
`disclosure or obviousness with of the disclosure of lines, whether a
`functional metal line or a dummy metal line, in Oda, and the Cwynar
`reference discloses those both and we've explained how Oda and Cwynar
`can be combined for that limitation. So, Oda and Cwynar combine for the
`limitations 1G and 1H. And Oda discloses all the other limitations without
`much of a dispute except for that one term, force region.
`I'll turn to Slide 18 just to move ahead. We discussed a little bit more
`how Oda and Cwynar can be combined. But that's also in the papers as well
`in Slides 14 to 17. So, if the Board has any questions about that. We also --
`JUDGE MCGRAW: I think before you move on to Owada, I'd to talk
`a little bit about Claim Element 1G and where Oda discloses an interconnect
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`IPR2019-01198, IPR2019-01199, IPR2019-01200
`Patent 7,247,552 B2
`
`layer that has both a functional metal line as well as a dummy metal line in
`the same layer. Now, I know that you rely on Figures 2A and 4B. What is
`the reason that one skilled in the art would look to combine the teachings of
`these two different embodiments? I understand that 2A is described in Oda
`as a first embodiment and Figure 4 is described as a third embodiment. So,
`what is the reason one skilled in the art would tie in together the first and the
`third embodiment?
`MR. WALDEN: So, Your Honor, I would direct you if you would, to
`Slide 34, where we have I believe we answer this -- we have slides that will
`help answer this question. And this is a showing on Slide 34 both Figure 2A
`and Oda's Figure 4B. And as we describe and discuss in the Petition and in
`the reply for Figure 2A just to start, Figure 2A shows that there's these layers
`220 and 210, which both can contain dummy metal it describes. But it also
`describes in paragraph 54 and again a few paragraphs down that those layers
`can be used for interconnect. And specifically, it notes that layer 210 and 20
`can be used for interconnects because they're insulated from the layers above
`them and as we have explained, you already have a disclosure for Figure 2A
`where you can as the person of skill in the art based on the teachings of Oda,
`you can decide whether to use dummy or active to connect to active devices
`for those layers. And, you know, there's no reason that you couldn't use
`both.
`
`So, then you then have the disclosure in Oda of Figure 4B, which is
`described as essentially examples each for 2A through the other examples
`are provided as examples of the invention in which they're not limiting. And
`they're showing different ways in which the layers can be connected. And
`so, in 4B, we have the situation where underneath the bond pad, you have
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`IPR2019-01198, IPR2019-01199, IPR2019-01200
`Patent 7,247,552 B2
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`both dummy shown in 4B in pink there, and then active metal in the same
`layer underneath the bond pad. And so, once you look at those portions, you
`realize that just with the description of 2A, they're saying you've got options.
`You can use the metal for active layer. You can use it for dummy. You go
`then to 4B you can see that you have the option of actually having dummy
`and active all in the same layer. Dummy performing that shock absorption
`function. And, of course, active being used to make interconnect.
`And then, you know, we -- I'm sorry --we then have on Slide 35, the
`portion of the part of Oda from paragraph 105, which says, the construction
`of the above- described first to fourth working examples are only examples
`of the present invention. And the present invention can be modified as
`appropriate within the range that does not depart from the gist of the
`invention. And we're just saying there's no combining of 2A and 4B that's
`not obvious. And it's all within the gist of this invention described in Oda,
`which is to when you can, use metal to reinforce. And if you also want to,
`you can use that metal to make connections to the interconnect layers.
`JUDGE MCGRAW: If you could, go back to slide 34, please. So
`Oda, as I understand it, states that the dummy lines in layer 210, or I should
`say the lines in 210, and I realize Patent Owner will dispute whether they are
`lines or not, but we’ll call them “lines” for the purposes of this conversation.
`The lines of 210 can also function as interconnects because they are
`insulated from the layer above, but that is not shown in Figure 4b because it
`appears in 4B that layer 212 is connected through vias. So I’m trying to
`understand your argument as to how these two figures together show a layer
`that has both dummy lines and an interconnect in a metal containing layer
`that is not connected to the bond pad.
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`IPR2019-01198, IPR2019-01199, IPR2019-01200
`Patent 7,247,552 B2
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`MR. WALDEN: So, Your Honor, a good question, and with respect
`to slide 34, the argument goes like this: In slide 34 we have a portion of Oda
`that starts at paragraph 54, and in that portion it states that the circuit
`interconnect are going to be made of the same material as the material
`shown in layer 200 which includes of course 220 and 21 as well as in 100,
`but the circuit interconnects and the dummies are going to be made of
`similar same material. The patent then as we discuss -- and we have a couple
`of other slides about it, but I’ll stick with this slide for now -- the patent then
`discusses in paragraphs 55 through 59 that those metal layers, the metal that
`we see in layers 210 and 220 can be used as a dummy materials, and again
`used to reinforce.
`That at paragraph 61 it states that in addition the dummy pattern of the
`lower copper layer of 200 electrically insulated from the upper copper layer
`100, and this dummy pattern may therefore be used as a pattern for circuit
`interconnect. Now what this means is that unlike figure 4b where the
`interconnect is being to the -- from layer 212, for example, or -- yes, from
`layer 212 up to the bond pad above it, what this describes in the Oda
`reference at paragraph 61 is that the layer 210 can be used as interconnect,
`for example, for the substrate below it. And there are things like, and this is
`discussed in the Petition and in the reply -- there are transistors and other
`devices, and those transistors are in the semiconductor substrate, and that is
`at the bottom, and those have to be connected to something always -- always
`something, right?
`They need power, they need usually some kind of signal, and they
`need ground usually, so there has to be multiple connections to a transistor.
`The output of transistors are going to be sent to different places including to
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`IPR2019-01198, IPR2019-01199, IPR2019-01200
`Patent 7,247,552 B2
`
`other transistors. All of these things are integral to integrated circuits. This
`is why you have these complicated layers above them where you’re basically
`routing metal everywhere. Sometimes there are metals being routed all the
`way up to the bond pad above it, but sometimes not. Sometimes the metal is
`used to -- the metal layers are used to route between transistors below it, and
`that’s what Oda is saying.
`Oda is saying because you’re insulated from that bond pad above it,
`you can use the 210 for interconnect for other things, and the point is, is that
`-- you know, the point that relates back to the 552 Patent is that means
`you’re not electrically connected, and therefore you have a functional
`independence, and therefore you can be used for a different function and one
`of those functions can be used as a pattern for circuit interconnect. Just to
`follow up on that, we have, and it’s in our reply, the Patent Owner’s expert
`agreed that the lower layers are going to be the ones that are more likely
`used to connect portions of the substrate, so it all lines up with what Oda
`discloses.
`JUDGE MCGRAW: Thank you.
`MR. WALDEN: Thank you. While we’re at these slides, I’ll just
`back up briefly to slide 32, and this is a response to the question of whether
`Oda discloses lines at all. Now I think we’ve already addressed Oda
`discloses patterns because other patterns can be used, and I don’t think there
`is any disagreement that lines are one of the most common forms of patterns,
`and their expert agreed with that and we’ve got that set out in our slides but
`also in our reply brief.
`The other point here is again that the Cwynar and the Owada
`references both undisputedly show lines. If you’ll turn to slide 33, the Patent
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`IPR2019-01198, IPR2019-01199, IPR2019-01200
`Patent 7,247,552 B2
`
`Owner has argued that there is not enough mechanical support supplied by
`lines and that therefore a person of skill would not be motivated to
`incorporate the lines of Cwynar or Owada into what’s disclosed in Oda, but
`that argument is based mostly it seems on the argument that lines run in one
`direction and therefore apply a mechanical support in only one dimension,
`but that really does not square with what we see in figure 3 of the 552 Patent
`itself where lines are shown extending into two directions therefore
`supplying the same type of support of the pattern, any other type of pattern.
`This is going to be a two-dimensional support. We see shorter and
`longer lines, but the idea of an ideal line or some element of the Manhattan
`Rule we don’t see here. We don’t have lines, whether active or dummy,
`extending in one direction at all, and as we show here in our slide 33 and as
`discussed in the reply, Patent Owner’s expert admitted that he could not say
`whether the disclosure, what’s was in Oda, or the disclosure in the 552
`Patent provide more or less support.
`He’s also admitted, and we have it in our slides and I’ll get to it, other
`things about dummy lines, for example that they existed in the prior art, that
`they were used in both subtractive and additive type processes that they were
`used for both structural and mechanical support and also for polishing
`purposes or what we call planarity purposes. All of that is acknowledged,
`and then finally that the claims don’t require any type of a particular type of
`process for creating the integrated circuit, only that the integrated circuit
`have a forced region and that dummy lines are added below the bond or
`bottom (phonetic) pads or paths to reinforce that forced region.
`I’ll turn back briefly to slide 24, and this addresses the first issue that
`was raised by the Patent Owner and that is whether Oda or Owada teaches a
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`IPR2019-01198, IPR2019-01199, IPR2019-01200
`Patent 7,247,552 B2
`
`functional metal line that is not electrically connected to the bond pad. And
`so Patent Owner disputes whether either of them does teach this. For the
`Petition, count 1, the Petitioner relies on Oda for this limitation, and for
`count 3, Petitioner relies on both Oda or Owada that if the Board finds that
`either satisfies this limitation then it’s just finding for the Petitioner on count
`3.
`
`The Patent Owner claims that the Petitioner is relying on inherency
`for this limitation and that’s not the case. Both Oda and Owada explicitly
`teach a functional metal line underneath the bond pad that is not connected
`to the bond pad, so therefore there’s no inherency argument. It’s not that
`we’re saying though this is true, not that we’re saying only that a person of
`skill in the art would understand an interconnect metal layers there are going
`to be a lot of line, and that those lines are very much likely going to be
`underneath bond pads because there are going to be bond pads that occupy
`space above them, therefore there has to be both metal lines and dummy
`lines.
`
`But, and the person of ordinary skill in the art is going to understand
`that these lines don’t necessarily have to be connected to the bond pad above
`them, so that’s inherency, but that’s not what the Petition or the Petitioner
`relies on. Instead the Petition relies on the disclosure in both of Oda and in
`Owada in which there is an active metal line below. The bond pad does not
`electrically connect it to the bond pad.
`If you turn to slide 24, the Petition explains how Oda teaches this
`limitation and the Petition is pages 36 to 38. So your 2A from Oda shows
`the layer 210, and as we discussed earlier, it describes how that layer can be
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`IPR2019-01198, IPR2019-01199, IPR2019-01200
`Patent 7,247,552 B2
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`used as a pattern for circuit interconnect because of its insulation from the
`layer above it.
`Slide 25. I discussed paragraph 61 of Oda, but that’s shown here in
`slide 25, and again it describes that because that reasoning that it can be used
`for circuit interconnect is its insulation from the layers above it. Slide 26.
`Here we have the admission or the acknowledgment from the Patent
`Owner’s expert that if you’re going to rough (phonetic) around (phonetic)
`between two transistors on a substrate, you’re going to use the lower layers
`of the integrated circuit for that, and he agreed with that.
`Slide 27, here we have figure 3 from Owada, Exhibit 105. Owada
`likewise teaches the functional metal line underlying the bond pad that is not
`electrically connected to the bond pad. Here we can see the green circle, the
`solder-bump which is above the bond pad, so we see the circle there. The
`blue lines are the active metal called signal wiring in Owada, and again the
`pink lines are the dummy line. And this is all described as being the lines in
`a particular layer below a power support -- I’m sorry, a power source supply
`solder-bumps, too. So we have signal lines that are underlying a power
`signal which is evidence that there is active metal lines below the bond pad
`that’s not being used for an electrical connection to the bond pad above it.
`If you turn to slide 28, the Patent Owner argues that the signal wiring
`of the ECL gate array which is what we’re relying upon for the figure in
`slide 27 is electrically connected to the power sources because they’re only
`represented by -- I’m sorry -- they’re only separated by resistors, but there
`can be no dispute that signal lines and power sources are functionally
`independent, and that is what the Patent describes, and the 552 Patent
`describes as not electrically connected. Here we have the portion of the 552
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`IPR2019-01198, IPR2019-01199, IPR2019-01200
`Patent 7,247,552 B2
`
`Patent fro