Petition for Inter Partes Review of U.S. Patent No. 7,247,552
`Claim 20
`IPR2019-01199
`
`
`DOCKET NO.: 0107131-00648US2
`Filed on behalf of Intel Corporation
`By: Yung-Hoon Ha, Reg. No. 56,368
`Theodoros Konstantakopoulos, Reg. No. 74,155
`Taeg Sang Cho, Reg. No. 69,618
`Calvin Walden (pro hac to be requested)
`Wilmer Cutler Pickering Hale and Dorr LLP
`7 World Trade Center
`250 Greenwich Street
`New York, New York 10007
`Email: Yung-Hoon.Ha@wilmerhale.com
` Theodoros.Konstantakopoulos@wilmerhale.com
` Tim.Cho@wilmerhale.com
` Calvin.Walden@wilmerhale.com
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________________________________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________________________________________
`
`Intel Corporation
`Petitioner
`
`v.
`
`VLSI Technology LLC
`Patent Owner
`___________________________________________
`
`Case IPR2019-01199
`____________________________________________
`PETITION FOR INTER PARTES REVIEW OF
`U.S. PATENT NO. 7,247,552
`CHALLENGING CLAIM 20
`
`
`
`
`
`
`
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,247,552
`Claim 20
`IPR2019-01199
`
`
`
`TABLE OF CONTENTS
`I. 
`INTRODUCTION ........................................................................................... 1 
`II.  MANDATORY NOTICES ............................................................................. 2 
`A. 
`Real Party-in-Interest ............................................................................ 2 
`B. 
`Related Matters ...................................................................................... 2 
`C. 
`Counsel .................................................................................................. 2 
`D. 
`Service Information ............................................................................... 2 
`III.  CERTIFICATION OF GROUNDS FOR STANDING .................................. 3 
`IV.  OVERVIEW OF CHALLENGE AND RELIEF REQUESTED .................... 3 
`A. 
`Prior Art Patent and Printed Publications ............................................. 3 
`B. 
`Grounds for Challenge .......................................................................... 5 
`V.  DISCRETION UNDER 35 U.S.C. §314(A) AND §325(D) ........................... 5 
`VI.  BRIEF DESCRIPTION OF TECHNOLOGY ................................................ 6 
`VII.  OVERVIEW OF THE ’552 PATENT ............................................................ 9 
`A.  Alleged Prior Art Problem .................................................................... 9 
`B. 
`Alleged Invention ................................................................................ 10 
`C. 
`Relevant Prosecution History .............................................................. 11 
`VIII.  OVERVIEW OF THE PRIOR ART ............................................................. 12 
`A.  Overview of Reddy ............................................................................. 13 
`Developing a Circuit Design ..................................................... 15 
` 
`Developing a Layout According to the Circuit Design ............ 15 
` 
`  Modifying the Layout ............................................................... 16 
`Forming the Integrated Circuit.................................................. 19 
` 
`Overview of Vuong ............................................................................. 20 
`B. 
`Overview of Kanaoka .......................................................................... 24 
`C. 
`D.  Overview of Weling ............................................................................ 27 
`IX.  CLAIM CONSTRUCTION .......................................................................... 30 
`X. 
`LEVEL OF ORDINARY SKILL IN THE ART ........................................... 30 
`
`i
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,247,552
`Claim 20
`IPR2019-01199
`
`
`XI.  SPECIFIC GROUNDS FOR PETITION ...................................................... 30 
`A.  Ground I: Claim 20 is Obvious Over Kanaoka in Combination
`with Weling and Reddy. ...................................................................... 31 
`Claim 20 .................................................................................... 31 
` 
`Additional Motivations to Combine Kanaoka, Weling,
` 
`and Reddy ................................................................................. 58 
`Ground II: Claim 20 is Obvious Over Kanaoka in Combination
`with Weling and Vuong. ..................................................................... 64 
`Claim 20 .................................................................................... 64 
` 
`Additional Motivations to Combine Kanaoka, Weling,
` 
`and Vuong ................................................................................. 74 
`XII.  CONCLUSION .............................................................................................. 80 
`
`B. 
`
`ii
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,247,552
`Claim 20
`IPR2019-01199
`
`
`
`Petitioner Intel Corporation (“Intel”) respectfully requests inter partes
`
`review of claim 20 of U.S. Patent No. 7,247,552 (“the ’552 patent”) (Ex. 1101)
`
`pursuant to 35 U.S.C. §§ 311-19 and 37 C.F.R. § 42.1 et seq.
`
`I.
`
`INTRODUCTION
`The ’552 patent addresses a simple problem in integrated circuit (“IC”)
`
`manufacturing. To interconnect transistors in an IC, layers that contain both
`
`electrically-conductive metals and dielectric/insulating materials are formed over a
`
`substrate. Near the top of these layers are small metal regions called “bond pads”
`
`that are used to connect the IC to external devices (like a circuit board). During
`
`manufacture, however, the layers under the bond pad can be subjected to
`
`forces/stresses when external connections are made.
`
`Claim 20 of the ’552 patent is directed to a method that purports to address
`
`this issue by developing a circuit design and layout for an integrated circuit that
`
`contains one or more bond pads, modifying the layout to add “dummy metal lines”
`
`to the interconnect layers under the bond pad, and forming the integrated circuit
`
`that contains the dummy metal lines. But that basic process was already well-
`
`known before the ’552 patent was filed— including as disclosed by the prior art
`
`references at issue in this Petition, none of which was before the Patent Office
`
`during prosecution.
`
`1
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,247,552
`Claim 20
`IPR2019-01199
`
`
`
`Accordingly, claim 20 of the ’552 patent should be held unpatentable.
`
`II. MANDATORY NOTICES
`A. Real Party-in-Interest
`Intel Corporation (“Petitioner”) is a real party-in-interest and submits this
`
`inter partes review Petition challenging claim 20 of the ’552 patent.
`
`B. Related Matters
`VLSI Technology LLC (“Patent Owner”) has asserted the ’552 patent
`
`against Intel in VLSI Technology LLC. v. Intel Corporation, No. 18-966-CFC (D.
`
`Del.).
`
`Petitioner has filed and will file separate inter partes review petitions
`
`challenging claims 1, 2, and 11 of the ʼ552 patent.
`
`C. Counsel
`Lead Counsel: Yung-Hoon Ha (Registration No. 56,368).
`
`Backup Counsel: Theodoros Konstantakopoulos (Registration No. 74,155),
`
`Taeg Sang Cho (Registration No. 69,618), Calvin Walden (pro hac vice to be
`
`requested).
`
`D.
`Service Information
`E-mail:
`
`
`Yung-Hoon.Ha@wilmerhale.com
`
`Theodoros.Konstantakopoulos@wilmerhale.com
`
`Tim.Cho@wilmerhale.com
`
`2
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,247,552
`Claim 20
`IPR2019-01199
`
`
`
`Calvin.Walden@wilmerhale.com
`
`Post and hand delivery: Wilmer Cutler Pickering Hale and Dorr LLP
`
`
`
`
`
`
`
`
`
`7 World Trade Center
`
`250 Greenwich Street
`
`New York, New York 10007
`
`Telephone: 212-230-8800
`
`Fax: 212-230-8888
`
`Petitioner consents to email delivery on lead and backup counsel.
`
`III. CERTIFICATION OF GROUNDS FOR STANDING
`Petitioner certifies pursuant to Rule 42.104(a) that the ’552 patent is
`
`available for inter partes review and that Petitioner is not barred or estopped from
`
`requesting an inter partes review challenging claim 20 on the grounds identified in
`
`this Petition.
`
`IV. OVERVIEW OF CHALLENGE AND RELIEF REQUESTED
`Pursuant to Rules 42.22(a)(1) and 42.104(b)(1)-(2), Petitioner challenges
`
`claim 20 of the ’552 patent.
`
`A.
`Prior Art Patent and Printed Publications
`The ’552 patent was filed on January 11, 2005, and does not claim priority
`
`to any prior applications. The following prior art references, none of which was
`
`3
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,247,552
`Claim 20
`IPR2019-01199
`
`
`considered during prosecution of the ’552 patent, are pertinent to the grounds of
`
`unpatentability explained below: 1
`
`1.
`
`U.S. Patent No. 7,102,223 (“Kanaoka”) (Ex. 1103), which was filed
`
`August 5, 2003, and issued September 5, 2006, is prior art under at
`
`least 35 U.S.C. § 102(e).
`
`2.
`
` “Digital Design Flow Options,” Sagar V. Reddy, M.S. Thesis, 2001
`
`(“Reddy”) (Ex. 1104), which was made available to the public on
`
`April 15, 2002, is prior art under at least 35 U.S.C. §102(b). See
`
`Declaration of Dr. Gretchen L. Hoffman (“Hoffman Declaration”)
`
`(Ex. 1108) (discussing public availability of Ex. 1104).
`
`3.
`
`U.S. Patent No. 5,639,697 (“Weling”) (Ex. 1105), which was filed
`
`January 30, 1996, and issued June 17, 1997, is prior art under at least
`
`35 U.S.C. § 102(b).
`
`4.
`
`U.S. Patent Publication No. US 2004/0098674 (“Vuong”) (Ex. 1106),
`
`which was filed on November 19, 2002, and published May 20, 2004,
`
`is prior art under at least 35 U.S.C. §§ 102(a) and (e).
`
`
`1 The ’552 patent issued from an application filed before enactment of the America
`
`Invents Act. Accordingly, the pre-AIA statutory framework applies.
`
`4
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,247,552
`Claim 20
`IPR2019-01199
`
`
`
`B. Grounds for Challenge
`Petitioner requests cancellation of claim 20 of the ’552 patent as
`
`unpatentable under 35 U.S.C. § 103 in view of (1) Kanaoka in combination with
`
`Weling and Reddy; and (2) Kanaoka in combination with Weling and Vuong. This
`
`Petition, supported by the declarations of Dr. John C. Bravman (Ex. 1102) and Dr.
`
`Gretchen L. Hoffman (Ex. 1108), demonstrates a reasonable likelihood that
`
`Petitioner will prevail with respect to cancellation of the challenged claim. See 35
`
`U.S.C. § 314(a).
`
`V. DISCRETION UNDER 35 U.S.C. §314(A) AND §325(D)
`The ’552 patent is one of numerous patents asserted by VLSI in multiple
`
`district court jurisdictions. Patent Owner has asserted four other patents in the
`
`parallel Delaware action. Patent Owner has also asserted 16 additional patents in 4
`
`separate cases: VLSI Technology LLC v. Intel Corporation, Nos. 6-19-cv-00254, -
`
`255, -256 (W.D. Tx.) and 5-17-cv-05671 (N.D. Cal.). Intel has moved to transfer
`
`the Texas actions to Delaware, and the timing of the cases are overlapping and may
`
`need to be adjusted. Intel has diligently pursued its defenses, including the
`
`assertions of prior art, from when the complaint containing the ’552 patent was
`
`filed. Intel brings this IPR to adjudicate validity for claims that VLSI has asserted
`
`because (i) the same or substantially the same arguments made in this Petition have
`
`5
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,247,552
`Claim 20
`IPR2019-01199
`
`
`not been presented to the Office, (ii) there is uncertainty whether a trial in the
`
`district court would conclude before or after the trial of this Petition, (iii) given the
`
`complexity of the cases, the number of patents asserted, and the breadth of
`
`products accused of infringement, Intel will have a limited amount of time during
`
`trial to mount an invalidity defense; and (iv) Petitioner has been ordered to narrow
`
`its invalidity defenses, and cannot pursue in the district court litigation the defense
`
`outlined in this Petition, and thus is not arguing for invalidity in this forum based
`
`on the same art and arguments as in the district court. Petitioner respects the
`
`limited resources of the Board, but because this Petition presents unique issues and
`
`would be an effective and efficient alternative to the district court litigation,
`
`Petitioner requests that the Petition be granted under 35 U.S.C. 314(a) and 325(d).
`
`Petitioner may request additional briefing if Patent Owner urges the Board to
`
`exercise its discretion to deny this Petition under 314(a) or 325(d).
`
`VI. BRIEF DESCRIPTION OF TECHNOLOGY
`In an IC, millions of tiny electronic components are formed in and over a
`
`“substrate.” For these electronic components to communicate with each other,
`
`electrically conductive pathways must interconnect them. To form these
`
`interconnects, layers that contain both electrically-conductive and
`
`dielectric/insulating materials are built over the substrate. Ex. 1102, ¶ 26.
`
`6
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,247,552
`Claim 20
`IPR2019-01199
`
`
`
`Figure 1 of the ’552 patent shows the basic arrangement
`
`Ex. 1101, Fig. 1. Over substrate 122, a first metal interconnect layer 26 (blue
`
`circle) containing conductive materials 56, 58, 60 (blue highlighting), such as
`
`copper, is formed. These conductive materials provide pathways for electrical
`
`
`
`
`2 All color, annotations, and bold/italics emphases in this Petition are added.
`
`7
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,247,552
`Claim 20
`IPR2019-01199
`
`
`signals (or power) to flow, and are electrically isolated from each other by
`
`dielectric material 62, such as silica. Ex. 1101, 3:35-38; Ex. 1102, ¶¶ 27-28.
`
`
`
`Metal interconnect layer 26 is then polished, and interlevel dielectric layer
`
`24 (light green circle) is deposited on top of that metal layer. Vertical pathways
`
`connecting the conductive materials (e.g., 50 and 58) in different metal
`
`interconnect layers (e.g., layers 22 and 26) are formed in the interlevel dielectric
`
`layer 24 to create via 59. The process of forming alternating metal interconnect
`
`layers 22, 18, and 14 and interlevel dielectric layers 20 and 16 then repeats until
`
`all desired layers are built. Ex. 1101, 2:64-67, 3:9-10, 3:35-38, Fig. 1; Ex. 1102, ¶
`
`29.
`
`Metals in the top metal interconnect layer are often used to form bond pads
`
`32 to provide electrical connections to other external components (e.g., a circuit
`
`board). These external connections can be made by placing additional metal (e.g.,
`
`conductive bump 28) to the bond pad 32. Ex. 1101, 3:10-12, 3:20-25, Fig. 1; Ex.
`
`1102, ¶ 30.
`
`In addition to these “active” metal interconnects, “dummy” metals can be
`
`added as “filler” material. These dummy metals are generally electrically
`
`“floating” (i.e., not electrically connected to other metal), but can also be
`
`physically connected to other metal structures. It was well-known that adding
`
`8
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,247,552
`Claim 20
`IPR2019-01199
`
`
`these “dummy metals can provide added structural reinforcement as well as
`
`improved planarity of the layers during fabrication (e.g., during a polishing step).
`
`Ex. 1102, ¶ 31.
`
`The method of making an integrated circuit typically begins with a high-
`
`level design idea, which is followed by a series of basic design phases, including:
`
`(1) developing a circuit design; (2) developing a layout corresponding to the circuit
`
`design; and (3) modifying the layout to comply with design rules. Long before the
`
`’552 patent, computer aided design (“CAD”) tools were used for these design
`
`steps. Ex. 1111, 1:45-58 (“CAD techniques have been used with success in design
`
`and verification of integrated circuits, at both the structural level and at the
`
`physical layout level.”). After the design phase is complete, the integrated circuit
`
`is then fabricated according to the modified layout. Ex. 1102, ¶ 32.
`
`
`
`VII. OVERVIEW OF THE ’552 PATENT
`A. Alleged Prior Art Problem
`The ’552 patent does not claim to have invented ICs that include substrates,
`
`interconnect layers, interlayer dielectrics, vias, bond pads, or conductive balls. To
`
`the contrary, it admits each of these was well-known in the prior art. Ex. 1101,
`
`1:25-2:4 (describing the prior art as involving “conductive balls … to make
`
`electrical connection to a bond pad,” “structures fabricated with copper
`
`9
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,247,552
`Claim 20
`IPR2019-01199
`
`
`interconnect metallization and low dielectric constant (low-k) dielectrics,”
`
`“interlayer dielectrics,” and “vias”). According to the ’552 patent, however,
`
`shrinking die sizes and brittle dielectric materials resulted in ICs becoming more
`
`susceptible to damage due to the “increased stress … when physical connection is
`
`made to the semiconductor die.” Id., Abstract, 1:42-46; Ex. 1102, ¶ 33.
`
`B. Alleged Invention
`The ’552 patent purports to address this issue merely by adding “dummy”
`
`metal structures below the bond pad to “increase the metal density of the
`
`interconnect layers.” Ex. 1101, Abstract, 4:37-56. As shown below, challenged
`
`claim 20 does not explicitly recite adding dummy metal lines to mitigate the ICs
`
`becoming more susceptible to damage due to forces/stresses when physical
`
`connection is made to the semiconductor die. Rather, claim 20 simply recites a
`
`method that requires developing a design and layout for an integrated circuit,
`
`“modifying the layout by adding dummy metal lines … to achieve a metal density
`
`of at least forty percent for each of the plurality of metal-containing interconnect
`
`layers,” and then making an integrated circuit using that modified design layout:
`
`20. A method of making an integrated circuit having a plurality of
`bond pads, comprising:
`developing a circuit design of the integrated circuit;
`
`10
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,247,552
`Claim 20
`IPR2019-01199
`
`
`
`developing a layout of the integrated circuit according to the circuit
`design, wherein the layout comprises a plurality of metal-containing
`interconnect layers that extend under a first bond pad of the plurality of bond
`pads, at least a portion of the plurality of metal-containing interconnect
`layers underlying the first bond pad and not electrically connected to the first
`bond pad as a result of being used for electrical interconnection not directly
`connected to the bond pad;
`modifying the layout by adding dummy metal lines to the plurality of
`metal-containing interconnect layers to achieve a metal density of at least
`forty percent for each of the plurality of metal-containing interconnect
`layers; and
`forming the integrated circuit comprising the dummy metal lines.
`Id., claim 20; Ex. 1102, ¶ 34.
`
`As detailed below, however, adding dummy metal lines to achieve a metal
`
`density of at least forty percent was well known and disclosed in the prior art—
`
`including by (1) Kanaoka, which teaches adding dummy metal lines in an
`
`integrated circuit to achieve desired metal densities above 40%, (2) Weling, which
`
`teaches adding dummy metal lines to areas of an integrated circuit to obtain a
`
`predetermined metal density above 40%, (3) Reddy, which teaches a process for
`
`making an integrated circuit, and (4) Vuong, which also describes integrated circuit
`
`design processes, including adding dummy “metal fill” to increase metal density.
`
`Ex. 1102, ¶ 35.
`
`C. Relevant Prosecution History
`The ’552 patent issued from U.S. Application No. 11/033,009, filed January
`
`11
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,247,552
`Claim 20
`IPR2019-01199
`
`
`11, 2005. The Examiner rejected all original claims over U.S. Patent Publication
`
`No. 2005/0082577. Ex. 1112, 3-7. In response, the applicant amended (among
`
`other things) challenged claim 20 with the following underlined language to recite
`
`“wherein the layout comprises a plurality of metal-containing interconnect layers
`
`that extend under a first bond pad of the plurality of bond pads, at least a portion of
`
`the plurality of metal-containing interconnect layers underlying the first bond pad
`
`and not electrically connected to the first bond pad as a result of being used for
`
`electrical interconnection not directly connected to the bond pad.” Ex. 1113, 6-7.
`
`The Examiner allowed claim 20 as amended. Ex. 1107, 2.
`
`VIII. OVERVIEW OF THE PRIOR ART
`The prior art demonstrate that the claimed method of making an integrated
`
`circuit was well-known in the art. As more fully explained below, Reddy and
`
`Vuong are exemplary prior art that demonstrates the steps involved in designing
`
`and making an integrated circuit were well-known. This overall concept is
`
`ubiquitous in the production of almost all complex systems. Kanaoka, Weling and
`
`Vuong all demonstrate the well-known concept of adding dummy metal lines as
`
`part of a method for designing and making an integrated circuit. Ex. 1102, ¶ 37.
`
`12
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,247,552
`Claim 20
`IPR2019-01199
`
`
`
`A. Overview of Reddy
`Reddy describes the process for designing an integrated circuit using well
`
`known computer aided tools. Ex. 1104, 1. In Figure 1.1 below (modified to
`
`improve resolution of the text), Reddy shows a “generic IC [integrated circuit]
`
`design flow” for the various design phases of an integrated circuit:
`
`13
`
`

`

`
`
`Petition for Inter Partes Review of U.S. Patent No. 7,247,552
`Claim 20
`IPR2019-01199
`
`
`
`Id., 1-2, Fig. 1.1 (“Design Flow is a term used to describe the various design
`
`phases of an IC design.”); Ex. 1102, ¶ 38.
`
`As detailed below more fully, Reddy maps directly to the design flow steps
`
`in challenged claim 20. Id., ¶ 39.
`
`
`
`14
`
`

`

`
`
`Petition for Inter Partes Review of U.S. Patent No. 7,247,552
`Claim 20
`IPR2019-01199
`
`
`Developing a Circuit Design
`In steps 1 to 4 of Figure 1.1, Reddy describes the basic steps involved in
`
`developing a circuit design of an integrated circuit:
`
`
`
`Ex. 1104, Fig. 1.1. Step 1 involves coming up with the idea of the integrated
`
`circuit design; steps 2 and 3 involve developing a behavioral and structural
`
`description of that design; and step 4 involves creating a schematic overview of the
`
`design (including a timing analysis and simulation). Id., 3-4, Fig. 1.1; Ex. 1102, ¶
`
`
`
`40.
`
`
`Developing a Layout According to the Circuit Design
`Step 5 of Figure 1.1 illustrates developing a “layout” according to the circuit
`
`design:
`
`
`
`15
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,247,552
`Claim 20
`IPR2019-01199
`
`
`
`
`
`Ex. 1104, 4-5, Fig. 1.1. In this context, “layout generation” refers to developing a
`
`representation of the geometric shapes of the electrical components on the
`
`substrate and the electrically conductive pathways in different metal interconnect
`
`layers and interlevel dielectric layers. As Reddy explains, “semi or fully
`
`automated [electronic design automation] tools” can be used to generate the layout.
`
`Id.; Ex. 1102, ¶ 41.
`
` Modifying the Layout
`Steps 6 and 7 involve performing a design rule check (“DRC”) and layout
`
`vs. schematic (“LVS”) checks:
`
`
`
`16
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,247,552
`Claim 20
`IPR2019-01199
`
`
`
`
`
`Ex. 1104, Fig. 1.1. The LVS check “ensures that the layout is in conformance with
`
`the schematic” of the circuit design, and the “design rule check ensures that [the
`
`layout does not violate] the rules laid down by the fabrication process technology.”
`
`Id., 5. “The design process moves back and forth between Layout [(step 5)], LVS
`
`[(step 7)] and DRC [(step 6)].” Id. In this iterative process, “design rules are
`
`checked” every time the “layout is modified,” id., 105, and the layout is modified
`
`to ensure compliance with the design rule check that occurs in step 6. Ex. 1104, 5-
`
`6 (“[A] design rule check ensures that the rules laid down by the fabrication
`
`process technology are not violated. A good example would be, some processes
`
`need transistors, wires and polysilicon to be of a certain minimum width. The
`
`layout would have to be drawn based on such constraints.”); Ex. 1102, ¶ 42, 44.
`
`17
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,247,552
`Claim 20
`IPR2019-01199
`
`The design rules “are flexible and can be customized.” Ex. 1104, 105. The
`
`
`
`
`design rule check is carried out for each metal interconnect layer. For example, in
`
`Figure 5.29, Reddy shows an exemplary “DRC customization window” in which a
`
`design rule check is performed on several different metal interconnect layers
`
`(“Metal-1,” “Metal-2,” “Metal-3,” etc.) of the integrated circuit under design.
`
`18
`
`
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,247,552
`Claim 20
`IPR2019-01199
`
`
`Id., Fig. 5.29; Ex. 1102, ¶ 43.
`
`
`Forming the Integrated Circuit
`In steps 8-9, final simulation is carried out and “files that describe the
`
`[integrated circuit] layout” are generated. Ex. 1104, 6. Then, in step 10, Reddy
`
`teaches fabrication of integrated circuits using the modified layout:
`
`Id., Fig. 1.1; Ex. 1102, ¶ 45.
`
`19
`
`
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,247,552
`Claim 20
`IPR2019-01199
`
`
`
`B. Overview of Vuong
`Vuong similarly describes steps to design and manufacture an integrated
`
`circuit, but explicitly includes a “metal fill” step in the design flow process. Ex.
`
`1106, Abstract. Vuong states that increasing metal density by adding “metal-fill
`
`patterning” was a “common approach” used to avoid having too much space
`
`between active metal lines and unwanted “bumps” in layers in the finished chip
`
`(which can adversely affect polishing those layers). Id., [0003]-[0004] (“If there is
`
`an insufficient amount of metal at a particular portion or ‘window’ on the chip,
`
`then metal-fill is required to increase the proportion of metal in that portion or
`
`window.”); Ex. 1102, ¶¶ 46, 49.
`
`Vuong describes several approaches for adding metal-fill patterning during
`
`chip design. For example, Vuong explains that, after an integrated circuit design
`
`and layout are created, the layout can be divided into “portions or windows,” and
`
`checks can be carried out to determine if the amount of metal in those
`
`portions/windows meets certain design requirements. Ex. 1106, [0006] (“[A] chip
`
`layout is divided into a set of delineated portions or windows” and calculations are
`
`performed to determine the proportion of metal materials versus non-metal
`
`materials in each window); Ex. 1102, ¶ 50.
`
`20
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,247,552
`Claim 20
`IPR2019-01199
`
`
`
`If the calculations reveal that the amount of metal density in those areas falls
`
`below a threshold level, the layout is modified by adding a “fill template” (i.e., a
`
`“fixed pattern of uniform metal shapes”) to perform “fill patterning” (i.e., to fill in
`
`portions of the window without active metal lines)—“resulting in the new chip
`
`layout.” Ex. 1106, [0007], [0006] (“If the proportion of metal in that window is
`
`below a specified minimum percentage, then metal-fill patterning is performed to
`
`increase the amount of metal.”). Once a layout has been modified with a new “fill
`
`template,” “a determination is made whether the layout meets minimum and
`
`maximum metal requirements.” Id., [0008]. If not, a new fixed pattern is selected
`
`and the process repeats “until the final layout satisfies the minimum and maximum
`
`metal percentage requirements for the chip.” Id., [0009]-[0010]3; Ex. 1102, ¶ 51.
`
` Vuong discloses that shapes for metal fills include “long wires 804”—also
`
`called “fill lines”—that “split” portions of a window not containing metal
`
`interconnects (“whitespace”) as shown in Figure 8 below:
`
`
`3 Vuong also describes a modification to the “fixed template” approach that
`
`“dynamically adjust[s] shape widths and different shape lengths that best fill [a
`
`window] area, in which only a single pass is needed to appropriately determine the
`
`metal-fill pattern.” Ex. 1106, [0011]; Ex. 1102, ¶ 52.
`
`21
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,247,552
`Claim 20
`IPR2019-01199
`
`
`
`Ex. 1106, Fig. 8, [0044]. Vuong further teaches that “[i]f desired, the long wires of
`
`the metal-fill pattern can be split again in another direction to form smaller metal-
`
`fill pattern element, as shown by elements 806 in Fig. 8.” Id., [0045]; Ex. 1102, ¶
`
`
`
`53.
`
`In Figure 14, Vuong shows an automated tool called “Layout/Place&Route
`
`Tool” 1402:
`
`22
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,247,552
`Claim 20
`IPR2019-01199
`
`
`
`Ex. 1106, [0059], Fig. 14. Vuong teaches that, using the steps depicted in this
`
`figure, “Layout/Place&Route Tool” is configured to:
`
`
`
`(1)
`
`receive a synthesized circuit design 1404 for an integrated circuit (“a
`
`synthesized gate-level netlist 1404 of a circuit design”), id., [0059] (“[The]
`
`layout/place & route tool takes as input a synthesized gate-level netlist 1404 of a
`
`circuit design ….”);
`
`
`
`(2)
`
`develop a layout for the integrated circuit according to the received
`
`circuit design 1404 by using “placement portion 1408 to place the logic gates and
`
`… a routing portion 1410 to route the tracks on a floorplan…,” id.;
`
`
`
`(3) modify the circuit design layout by adding metal fill using “metal-fill
`
`mechanism 1412,” id.; and
`
`23
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,247,552
`Claim 20
`IPR2019-01199
`
`(4) verify the modified layout (verification 1416) to ensure the modified
`
`
`
`
`design functions properly, id. (“[The] verification tool 1416 [is used] to verify the
`
`appropriateness of the physical design.”); Ex. 1102, ¶ 47.
`
`
`
`If the verification step identifies a problem, tool 1402 corrects it by repeating
`
`the layout step to make any necessary further modifications to the layout. Ex.
`
`1106, [0059]. By integrating the “metal fill” step (1412) to the layout
`
`design/modification process of tool 1402, Vuong explains that “the metal-fill
`
`becomes just another set of features of the physical design that is verified during
`
`the ordinary course of performing extraction and verification upon the layout.” Id.,
`
`[0060]; Ex. 1102, ¶ 48.
`
`C. Overview of Kanaoka
`Kanaoka teaches the addition of dummy metal lines below bond pads in
`
`designing and manufacturing an integrated circuit. Ex. 1103, 1:6-26, 11:22-25.
`
`Figure 25 of Kanaoka below provides a top-down plan view showing a
`
`semiconductor chip (labeled “1C”) with multiple electrode bond pads (labeled
`
`“PD”):
`
`24
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,247,552
`Claim 20
`IPR2019-01199
`
`
`
`
`
`Id., Fig. 25, 9:63-67, 10:9-17, 11:59-12:7. Below each bond pad are multiple
`
`metal-containing interconnect layers. Id., 10:45-61. The four corner bond pads
`
`colored in red are called “dummy pads” and, as such, they need not be electrically
`
`connected to any circuitry. Id., 11:3-4 (“The pad PD16 indicates, for example, a
`
`corner dummy pad.”); id., 14:10-12 (“Since the pad PD16 is a dummy pad, it is not
`
`necessary to electrically connect the underlying layers of the second-layer wiring
`
`M2 and the first-layer wiring M1 [that are below it].”). Regardless of whether they
`
`are used for active circuitry or as dummy pads, solder bumps are placed on all
`
`pads. Id., 1:41-42 (“[B]ump electrodes [are] bonded to the respective electrode
`
`pads.”); id., 14:19-22 (“[B]ump 11 [is] bonded to the dummy pad PD16.”); Ex.
`
`1102, ¶ 54.
`
`25
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,247,552
`Claim 20
`IPR2019-01199
`
`
`
`Figure 45 below contains a cross-sectional view of pad PD16 (one of corner
`
`dummy pads of Figure 25 colored in red) on metal layer M3:
`
`
`
`Ex. 1103, Fig. 45. Below pad PD16 are insulating films IS1, IS2 and IS3 (light
`
`green) with metal layers M1 and M2 (blue). Id., 14:23-15:35; Ex. 1102, ¶ 55.
`
`
`
`Kanaoka explains that, during manufacture of an integrated circuit, these
`
`layers are built up sequentially, but that failures can result if uneven amounts of
`
`metal in different layers below the pads exist, resulting in pads of different heights
`
`relative to one another. Ex. 1103, 1:36-46, 9:17-20 (“[W]here a number of
`
`insulating films are provided below the respective pads, the upper surface is
`
`recessed and steps are liable to develop.”); Ex. 1102, ¶ 56.
`
`26
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,247,552
`Claim 20
`IPR2019-01199
`
`
`
`To address this issue, Kanaok