UNITED STATES PATENT AND TRADEMARK OFFICE
`____________________________________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________________________________________
`
`Intel Corporation
`Petitioner
`
`v.
`
`VLSI Technology LLC
`Patent Owner
`
`Case IPR2019-01199
`
`DECLARATION OF JOHN C. BRAVMAN, PH.D.
`ON BEHALF OF PETITIONER
`
`Intel Exhibit 1102
`
`

`

`U.S. Patent 7,247,552
`Declaration of John C. Bravman, Ph.D.
`
`TABLE OF CONTENTS
`
`Page
`
`I.
`II.
`
`Background ...................................................................................................... 1
`Relevant Law ................................................................................................... 5
`A.
`Claim Construction ............................................................................... 5
`Obviousness ........................................................................................... 6
`B.
`Summary of Opinions ...................................................................................... 8
`III.
`IV. Brief Description of Technology ..................................................................... 8
`V.
`Overview of the ’552 Patent .......................................................................... 13
`A.
`Alleged Prior Art Problem .................................................................. 13
`B.
`Alleged Invention ................................................................................ 14
`Relevant Prosecution History .............................................................. 15
`C.
`VI. Overview of the Primary Prior Art References ............................................. 16
`A.
`Overview of Reddy ............................................................................. 17
`1. Developing a Circuit Design ........................................................ 19
`2. Developing a Layout According to the Circuit Design ................ 19
`3. Modifying the Layout ................................................................... 21
`4. Forming the Integrated Circuit ..................................................... 23
`Overview of Vuong ............................................................................. 24
`B.
`Overview of Kanaoka .......................................................................... 29
`C.
`Overview of Weling ............................................................................ 32
`D.
`VII. Claim Construction ........................................................................................ 35
`VIII. Level of Ordinary Skill In The Art ................................................................ 35
`Specific Grounds for Petition ........................................................................ 36
`IX.
`A.
`Ground I: Claim 20 is Obvious Over Kanaoka in Combination
`with Weling and Reddy ....................................................................... 36
`1. Claim 20 ....................................................................................... 36
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`

`U.S. Patent 7,247,552
`Declaration of John C. Bravman, Ph.D.
`
`
`a) 
`[20A] “A method of making an integrated circuit having a
`plurality of bond pads, comprising” ................................................ 36 
`b) 
`[20B] “developing a circuit design of the integrated circuit” . 40 
`c) 
`[20C] “developing a layout of the integrated circuit according
`to the circuit design, wherein the layout comprises a plurality of
`metal-containing interconnect layers that extend under a first bond
`pad of the plurality of bond pads” ................................................... 42 
`d) 
`[20D] “at least a portion of the plurality of metal-containing
`interconnect layers underlying the first bond pad and not
`electrically connected to the first bond pad as a result of being used
`for electrical interconnection not directly connected to the bond
`pad” 49 
`e) 
`[20E] “modifying the layout by adding dummy metal lines to
`the plurality of metal-containing interconnect layers to achieve a
`metal density of at least forty percent for each of the plurality of
`metal-containing interconnect layers; and” ..................................... 52 
`f) 
`[20F] “forming the integrated circuit comprising the dummy
`metal lines.” ..................................................................................... 63 
`2.  Motivation to Combine Kanaoka, Weling, and Reddy ................ 63 
`Ground II: Claim 20 is Obvious Over Kanaoka in Combination
`with Weling and Vuong. ..................................................................... 68 
`1.  Claim 20 ....................................................................................... 68 
`a) 
`[20A] “A method of making an integrated circuit having a
`plurality of bond pads, comprising” ................................................ 69 
`b) 
`[20B] “developing a circuit design of the integrated circuit” . 69 
`c) 
`[20C] “developing a layout of the integrated circuit according
`to the circuit design, wherein the layout comprises a plurality of
`metal-containing interconnect layers that extend under a first bond
`pad of the plurality of bond pads,” .................................................. 72 
`d) 
`[20D] “at least a portion of the plurality of metal-containing
`interconnect layers underlying the first bond pad and not
`electrically connected to the first bond pad as a result of being used
`for electrical interconnection not directly connected to the bond
`pad” 75 
`
`B. 
`
`ii
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`

`U.S. Patent 7,247,552
`Declaration of John C. Bravman, Ph.D.
`
`
`e) 
`[20E] “modifying the layout by adding dummy metal lines to
`the plurality of metal-containing interconnect layers to achieve a
`metal density of at least forty percent for each of the plurality of
`metal-containing interconnect layers; and” ..................................... 75 
`f) 
`[20F] “forming the integrated circuit comprising the dummy
`metal lines.” ..................................................................................... 78 
`2.  Additional Motivation to Combine Kanaoka, Weling, and Vuong
` ...................................................................................................... 79 
`X.  Availability for Cross-Examination .............................................................. 83 
`XI.  Right to Supplement ...................................................................................... 84 
`XII.  Jurat ................................................................................................................ 85 
`
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`iii
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`U.S. Patent 7,247,552
`Declaration of John C. Bravman, Ph.D.
`
`
`I, John C. Bravman, declare as follows:
`1.
`My name is John C. Bravman.
`
`I.
`
`BACKGROUND
`2.
`My academic training was at Stanford University, where I received
`
`my Bachelor of Science degree in Materials Science and Engineering in 1979, and
`
`a Master of Science degree in 1981, also in Materials Science and Engineering. I
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`completed my Doctor of Philosophy degree in 1984, with a dissertation that
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`focused on the nature of silicon – silicon dioxide interfaces as found in integrated
`
`circuit devices.
`
`3.
`
`From 1979 to 1984, while a graduate student at Stanford, I was
`
`employed part-time by Fairchild Semiconductor in their Palo Alto Advanced
`
`Research Laboratory. I worked in the Materials Characterization group. In 1985,
`
`upon completion of my doctorate, I joined the faculty at Stanford as Assistant
`
`Professor of Materials Science and Engineering. I was promoted to Associate
`
`Professor with tenure in 1991 and achieved the rank of Professor in 1995. In 1997 I
`
`was named to the Bing Professorship.
`
`4.
`
`At Stanford, I was Chairman of the Department of Materials Science
`
`and Engineering from 1996 to 1999, and Director of the Center for Materials
`
`Research from 1998 to 1999. I served as Senior Associate Dean of the School of
`
`Engineering from 1992 to 2001 and the Vice Provost for Undergraduate Education
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`from 1999 to 2010. On July 1, 2010, I retired from Stanford University and
`
`U.S. Patent 7,247,552
`Declaration of John C. Bravman, Ph.D.
`
`
`assumed the Presidency of Bucknell University, where I also became a Professor
`
`of Electrical Engineering.
`
`5.
`
`I have worked for more than 25 years in the areas of thin film
`
`materials processing and analysis. Much of my work has involved materials for
`
`use in microelectronic interconnects and packaging, and in superconducting
`
`structures and systems. With regard to integrated circuits, I led investigations
`
`involving aluminum, copper and tungsten metallizations, polycrystalline silicon,
`
`metal silicides, a variety of oxide and nitride dielectrics, and barrier layers such as
`
`titanium and tantalum-based nitrides. Further, my groups blended fundamental
`
`aspects of the behavior of microelectromechanical systems—specifically,
`
`compliant multilayer cantilever beams—for possible test probe and package
`
`implementations. In this work my group investigated the mechanical behavior of
`
`package underfill systems, focusing on the relationship between microstructures,
`
`processing, and adhesion. I have also led multiple development efforts of
`
`specialized equipment and methods for determining the microstructural and
`
`mechanical properties of materials and structures. My groups designed and built
`
`the first high voltage SEM for in-situ studies of electromigration, the first high
`
`temperature wafer curvature system, and the first microtensile tester for micron-
`
`scale structures, amongst many others. As a graduate student I developed one of
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`the earliest methodologies for obtaining high resolution cross section transmission
`
`U.S. Patent 7,247,552
`Declaration of John C. Bravman, Ph.D.
`
`
`electron micrographs of integrated circuit structures.
`
`6.
`
`I have taught a wide variety of courses at the undergraduate and
`
`graduate level in materials science and engineering, emphasizing both basic
`
`science and applied technology, including coursework in the areas of integrated
`
`circuit materials and processing. Some of these courses focused on processes (e.g.,
`
`cleaning, etching, deposition, doping, oxidation, etc.) used in the production of
`
`integrated circuits. More than two thousand students have taken my classes, and I
`
`have trained 24 doctoral students, most of whom now work in the microelectronics
`
`industry.
`
`7.
`
`I am a member of many professional societies, including the Materials
`
`Research Society, the Institute of Electrical and Electronic Engineers, the
`
`American Society of Metals, and the American Physical Society. I served as
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`President of the Materials Research Society in 1994.
`
`8.
`
`A copy of my curriculum vitae (including a list of all publications
`
`authored in the previous 10 years) is attached as Appendix A.
`
`
`
`9.
`
`I have reviewed the specification, claims, and file history of U.S.
`
`Patent No. 7,247,552 (“the ’552 patent”) (Ex. 1101). I understand that the ’552
`
`patent was filed on January 11, 2005 as U.S. Patent Application No. 11/033,009.
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`U.S. Patent 7,247,552
`Declaration of John C. Bravman, Ph.D.
`
`
`I have also reviewed the following references, all of which I
`
`10.
`
`understand to be prior art to the ’552 patent:
`
`1.
`
`U.S. Patent No. 7,102,223 titled “Semiconductor Device and a
`
`Method of Manufacturing the Same” (“Kanaoka”) (Ex. 1103), filed on
`
`August 5, 2003.
`
`2.
`
`“Digital Design Flow Options,” Sagar V. Reddy, M.S. Thesis, 2001
`
`(“Reddy”) (Ex. 1104), which was made available to the public on
`
`April 15, 2002.
`
`3.
`
`U.S. Patent No. 5,639,697, titled “Dummy Underlayers for
`
`Improvement in Removal Rate Consistency During Chemical
`
`Mechanical Polishing” (“Weling”) (Ex. 1105), filed on January 30,
`
`1996.
`
`4.
`
`US Patent Application Publication No. US 2004/0098674, titled
`
`“Place and Route Tool That Incorporates Metal-Fill Mechanism”
`
`(“Vuong”) (Ex. 1106), filed on November 19, 2002.
`
`11.
`
`I have also reviewed the exhibits and references cited in this
`
`Declaration.
`
`12.
`
`I have considered certain issues from the perspective of a person of
`
`ordinary skill in the art as described below at the time the ’552 patent application
`
`was filed.
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`U.S. Patent 7,247,552
`Declaration of John C. Bravman, Ph.D.
`
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`I have been retained by the Petitioner as an expert in the field of
`
`13.
`
`semiconductor device fabrication and design. I am working as an independent
`
`consultant in this matter and am being compensated at my normal consulting rate
`
`of $550 per hour for my time. My compensation is not dependent on and in no
`
`way affects the substance of my statements in this Declaration.
`
`14.
`
`I have no financial interest in the Petitioner. I similarly have no
`
`financial interest in the ’552 patent and have had no contact with the named
`
`inventor of the ’552 patent.
`
`II. RELEVANT LAW
`15.
`I am not an attorney. For the purposes of this declaration, I have been
`
`informed about certain aspects of the law that are relevant to my opinions. My
`
`understanding of the law is as follows:
`
`A. Claim Construction
`16.
`I have been informed that claim construction is a matter of law and
`
`that the final claim construction will ultimately be determined by the Board. For
`
`the purposes of my analysis in this proceeding and with respect to the prior art, I
`
`have been informed that IPRs are reviewed under the “the Phillips standard.”
`
`17.
`
`I have been informed that under the Phillips standard, claim terms are
`
`given their plain and ordinary meaning as understood by a person of ordinary skill
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`in the art at the time of the invention in light of the claim language and the patent
`
`U.S. Patent 7,247,552
`Declaration of John C. Bravman, Ph.D.
`
`
`specification.
`
`18.
`
`I have been informed that embodiments described in the specification
`
`are encompassed by the claim terms.
`
`19.
`
`I have been informed that the patentee can serve as their
`
`lexicographer. As such, if a claim term is provided with a specific definition in the
`
`specification, I should interpret that claim term in light of the particular definition
`
`provided by the patentee.
`
`B. Obviousness
`20.
`I have been informed and understand that a patent claim can be
`
`considered to have been obvious to a person of ordinary skill in the art at the time
`
`the application was filed. This means that, even if all of the requirements of a
`
`claim are not found in a single prior art reference, the claim is not patentable if the
`
`differences between the subject matter in the prior art and the subject matter in the
`
`claim would have been obvious to a person of ordinary skill in the art at the time
`
`the application was filed.
`
`21.
`
`I have been informed and understand that a determination of whether
`
`a claim would have been obvious should be based upon several factors, including,
`
`among others:
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`

` the level of ordinary skill in the art at the time the application was filed;
`
`U.S. Patent 7,247,552
`Declaration of John C. Bravman, Ph.D.
`
`
` the scope and content of the prior art; and
`
` what differences, if any, existed between the claimed invention and the
`
`prior art.
`
`22.
`
`I have been informed and understand that the teachings of two or
`
`more references may be combined in the same way as disclosed in the claims, if
`
`such a combination would have been obvious to one having ordinary skill in the
`
`art. In determining whether a combination based on either a single reference or
`
`multiple references would have been obvious, it is appropriate to consider, among
`
`other factors:
`
` whether the teachings of the prior art references disclose known concepts
`
`combined in familiar ways, which, when combined, would yield
`
`predictable results;
`
` whether a person of ordinary skill in the art could implement a
`
`predictable variation, and would see the benefit of doing so;
`
` whether the claimed elements represent one of a limited number of
`
`known design choices, and would have a reasonable expectation of
`
`success by those skilled in the art;
`
` whether a person of ordinary skill would have recognized a reason to
`
`combine known elements in the manner described in the claim;
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`

` whether there is some teaching or suggestion in the prior art to make the
`
`U.S. Patent 7,247,552
`Declaration of John C. Bravman, Ph.D.
`
`
`modification or combination of elements claimed in the patent; and
`
` whether the claim applies a known technique that had been used to
`
`improve a similar device or method in a similar way.
`
`23.
`
`I understand that one of ordinary skill in the art has ordinary creativity
`
`and is not an automaton.
`
`24.
`
`I understand that in considering obviousness, it is important not to
`
`determine obviousness using the benefit of hindsight derived from the patent being
`
`considered.
`
`III. SUMMARY OF OPINIONS
`25.
`It is my opinion that every step of the method described in claim 20 of
`
`the ’552 patent is disclosed by the prior art, and that claim 20 is rendered obvious
`
`by the prior art.
`
`IV. BRIEF DESCRIPTION OF TECHNOLOGY
`26.
`Integrated circuits contain millions of tiny electronic components
`
`(e.g., transistors). These transistor structures are typically formed in and over a
`
`semiconducting substrate, such as silicon. Electrically connecting these tiny
`
`transistor structures with one another so that they can electrically communicate
`
`with each other also requires a large number of electrically conductive pathways.
`
`To form these interconnects, engineers have layered electrically-conductive (e.g.,
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`metal) structures over one another, surrounding them with dielectric/insulating
`
`U.S. Patent 7,247,552
`Declaration of John C. Bravman, Ph.D.
`
`
`materials for electrical insulation.
`
`27.
`
`Figure 1 of the ’552 patent, which I have colored below, is one
`
`exemplary arrangement of an interconnect structure:
`
`Ex. 1101 [the ’552 patent] at Fig. 1.
`
`28.
`
`Specifically, the electrical components, such as transistors (not
`
`shown), are formed in and on the substrate 12. Over the substrate are shown the
`
`
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`

`

`alternating layers of interconnect layers. For example, a first metal interconnect
`
`U.S. Patent 7,247,552
`Declaration of John C. Bravman, Ph.D.
`
`
`layer 26 containing conductive materials 56, 58, 60 is shown. These conductive
`
`materials run into and out of the paper so that they can provide electrical pathways
`
`for electricity to flow. These electrical pathways can carry electrical signals or
`
`power. Moreover, these conductive materials are electrically isolated from each
`
`other by dielectric material 62. Ex. 1101 [the ’552 patent] at 3:35-38. One
`
`example, among many, of a conductive material is copper and one example, among
`
`many, of a dielectric material is silica.
`
`29.
`
`In addition to the metals running into and out of the paper, the metals
`
`can also run vertically by introducing structures called vias. To form such vias,
`
`metal interconnect layer 26 can be polished, and interlevel dielectric layer 24 can
`
`be deposited on top of that metal layer. Vertical pathways connecting the wires in
`
`first metal interconnect layer 26 to wires in one or more different metal
`
`interconnect layers are then formed in the interlevel dielectric layer 24 to create via
`
`59 (purple), over with the metal interconnect layer 22 is formed so that conductive
`
`material 50 is electrically connected to the conductive material 58. This process of
`
`forming alternating metal interconnect layers 22, 18 and 14 and interlevel
`
`dielectric layers 20 and 16 is then repeated. Ex. 1101 [the ’552 patent] at 2:64-67,
`
`3:9-10, 3:35-38, Fig. 1.
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`

`30. When all the desired layers of the integrated circuit are formed, the
`
`U.S. Patent 7,247,552
`Declaration of John C. Bravman, Ph.D.
`
`
`top interconnect metal layer can be used to make electrical connections to other
`
`external components (e.g., other components on a printed circuit board or other
`
`semiconductor devices). The metals in the top interconnect metal layer used to
`
`make such external connections are generally called “bond pads” because they
`
`serve as a pad to form bonds with additional metal structures that are placed
`
`thereon. For example, the ’552 patent explains that some examples of these pads
`
`include “wire bond pad, a probe pad, a flip-chip bump pad, a test point or other
`
`packaging or test pad structures.” Ex. 1101 [the ’552 patent] at 2:42-45. As an
`
`example, Figure 1 shows a conductive ball 28 on bond pad 32. Ex. 1101 [the ’552
`
`patent] at 3:10-12, 3:20-25, Fig. 1.
`
`31.
`
`These interconnects that electrically connect different electrical
`
`components (e.g., transistors) together to deliver electrical signals/power are often
`
`called “active” metal interconnects. In addition, “dummy” metals can be added as
`
`“filler” material. These dummy metals are generally not electrically connected to
`
`other metal structures – hence, they are generally electrically “floating.”
`
`Nevertheless, dummy structures can also be connected to other metal structures.
`
`For example, dummy metals can be connected to another dummy metal in a
`
`different layer through a via. Alternatively, a dummy metal can be connected to a
`
`dummy bond pad through a via. Engineers have long been adding such “dummy”
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`metal fillers because they can provide a number of desired effects. For example, it
`
`U.S. Patent 7,247,552
`Declaration of John C. Bravman, Ph.D.
`
`
`was well-known that adding dummy fillers can provide added structural protection
`
`to certain areas of the integrated circuit as metals provide more mechanical
`
`robustness compared to potentially brittle dielectric materials. As another
`
`example, it was well-known that the rate of polishing can be controlled by
`
`introducing a desired amount of metal, which can ultimately lead to improved
`
`planarity of the interconnect layers during fabrication (e.g., a polishing step).
`
`32.
`
`Building an integrated circuit typically begins with a high-level design
`
`idea that addresses the desired functionality of the circuit. After the idea is formed
`
`a series of design phases are undertaken, including: (1) developing a circuit design;
`
`(2) developing a layout corresponding to the circuit design; and (3) modifying the
`
`layout to comply with design rules. Long before the ’552 patent, computer
`
`automated design (“CAD”) tools were used for these design steps. Ex. 1111
`
`[Kobayashi] at 1:45-58 (“CAD techniques have been used with success in design
`
`and verification of integrated circuits, at both the structural level and at the
`
`physical layout level.”). After the design phase is complete, the integrated circuit
`
`is then fabricated according to the modified layout.
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`U.S. Patent 7,247,552
`Declaration of John C. Bravman, Ph.D.
`
`
`V. OVERVIEW OF THE ’552 PATENT
`A. Alleged Prior Art Problem
`33.
`The ’552 patent notes that “[t]he use of conductive balls, such as
`
`solder balls, to make electrical connection to a bond pad is a known method to
`
`make electrical connection to electrical circuitry of a semiconductor die.” Ex.
`
`1101 [the ’552 patent] at 1:25-28. The ’552 patent further notes that “[b]ecause the
`
`advanced low-k interlayer dielectrics used today have a lower dielectric constant
`
`and lower Young's modulus than dielectrics used in earlier generation products,
`
`flip chip die attach may more easily mechanically fracture the underlying stack of
`
`metal and dielectric layers.” Ex. 1101 [the ’552 patent] at 1:42-46. Moreover,
`
`the ’552 patent notes that “[a] known method to address the stresses present
`
`underlying a bond pad is to use a dedicated support structure. A common structure
`
`is the use of at least two metal layers under the bonding pad that are connected
`
`together and to the bonding pad by large arrays of vias distributed across a
`
`majority of the bond pad area.” Ex. 1101 [the ’552 patent] at 1:53-58.
`
`Furthermore, the ’552 patent notes that “[a]nother known method of mitigating
`
`stresses in a bond pad region is to replace low-k dielectric layers with higher k
`
`dielectric and higher elastic modulus dielectric layers until the die exhibits
`
`resistance to cracking.” Ex. 1101 [the ’552 patent] at 1:65-2:4. The ’552 patent,
`
`however, notes that the shrinking die sizes and more brittle dielectric materials
`
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`

`render them more susceptible to damage due to the “increased stress to the bond
`
`U.S. Patent 7,247,552
`Declaration of John C. Bravman, Ph.D.
`
`
`pad structure when physical connection is made to the semiconductor die.” Ex.
`
`1101 [the ’552 patent] at Abstract, 1:33-35.
`
`B. Alleged Invention
`34.
`The ’552 patent alleges that such problem can be solved by adding
`
`“dummy” metal lines in the interconnect layers to “increase the metal density of
`
`the interconnect layers.” Ex. 1101 [the ’552 patent] at Abstract, 4:37-56.
`
`Challenged claim 20, reproduced below, is directed to a method that requires
`
`developing a design and layout for an integrated circuit, “modifying the layout by
`
`adding dummy metal lines . . . to achieve a metal density of at least forty percent
`
`for each of the plurality of metal-containing interconnect layers,” and then making
`
`an integrated circuit using that modified design layout:
`
`20. A method of making an integrated circuit having a plurality of
`bond pads, comprising:
`
`developing a circuit design of the integrated circuit;
`
`developing a layout of the integrated circuit according to the
`circuit design, wherein the layout comprises a plurality of metal-
`containing interconnect layers that extend under a first bond pad of
`the plurality of bond pads, at least a portion of the plurality of metal-
`containing interconnect layers underlying the first bond pad and not
`
`14
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`

`U.S. Patent 7,247,552
`Declaration of John C. Bravman, Ph.D.
`
`
`electrically connected to the first bond pad as a result of being used
`for electrical interconnection not directly connected to the bond pad;
`
`modifying the layout by adding dummy metal lines to the
`plurality of metal-containing interconnect layers to achieve a metal
`density of at least forty percent for each of the plurality of metal-
`containing interconnect layers; and
`
`forming the integrated circuit comprising the dummy metal
`
`lines.
`
`
`Ex. 1101 [the ’552 patent] at claim 20.
`
`35.
`
`In my opinion, claim 20 is not patentable for being obvious. As I
`
`explain below, the approach of Claim 20 was well known and disclosed in the prior
`
`art—including by (1) Kanaoka, which teaches adding dummy metal lines in an
`
`integrated circuit to achieve desired metal densities, (2) Weling, which teaches
`
`adding dummy metal lines to areas of an integrated circuit to obtain a
`
`predetermined metal density, (3) Reddy, which teaches a process for designing an
`
`integrated circuit, and (4) Vuong, which also describes integrated circuit design
`
`processes, including adding dummy “metal fill” to increase metal density.
`
`C. Relevant Prosecution History
`36.
`I have been informed that the ’552 patent issued from U.S.
`
`Application No. 11/033,009, filed January 11, 2005. I understand that during
`
`prosecution, the Examiner rejected all original claims over U.S. Patent Publication
`
`15
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`U.S. Patent 7,247,552
`Declaration of John C. Bravman, Ph.D.
`
`No. 2005/0082577 (“Usui”). Ex. 1112 [Jan. 24, 2007 Non-Final Rejection] at 3-7.
`
`I further understand that the applicant amended (among other things) challenged
`
`claim 20 with the following underlined language to recite “wherein the layout
`
`comprises a plurality of metal-containing interconnect layers that extend under a
`
`first bond pad of the plurality of bond pads, at least a portion of the plurality of
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`metal-containing interconnect layers underlying the first bond pad and not
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`electrically connected to the first bond pad as a result of being used for electrical
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`interconnection not directly connected to the bond pad.” Ex. 1113 [Apr. 5, 2007
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`Response to Office Action] at 6-7. I further understand that the Examiner allowed
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`claim 20 as amended. Ex. 1107 [May 25, 2007 Notice of Allowability] at 2.
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`VI. OVERVIEW OF THE PRIMARY PRIOR ART REFERENCES
`37.
`In my opinion, there is nothing novel or inventive in claim 20 of
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`the ’552 patent. The claimed method of making an integrated circuit was well-
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`known in the art. This is demonstrated by the prior art that is relied upon in my
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`declaration. For example, Reddy and Vuong demonstrate the well-known fact that
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`making an integrated circuit involved a series of design flow steps. This overall
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`concept is ubiquitous in the production of almost all complex systems. Indeed, as
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`recognized in the seminal work by Carver and Mead, Introduction to VLSI
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`Systems, published in 1980, “Wafer fabrication is probably the most exacting
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`production process ever developed.” Ex. 1115 [Carver] at 38. As part of that
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`design flow, adding dummy metal lines to a layout was well-known, as
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`U.S. Patent 7,247,552
`Declaration of John C. Bravman, Ph.D.
`
`
`demonstrated by Kanaoka, Weling and Vuong. My opinions are discussed in
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`greater detail below, but I first provide brief summaries of the prior art references:
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`Reddy, Vuong, Kanaoka, and Weling.
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`A. Overview of Reddy
`38.
`Reddy describes the process for designing and making an integrated
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`circuit. Ex. 1104 [Reddy] at 1. Figure 1.1 of Reddy (which I modified to improve
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`resolution of the text) reproduced below, shows a “generic IC [integrated circuit]
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`design flow” with the design phases leading to the fabrication of an integrated
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`circuit:
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`17
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`U.S. Patent 7,247,552
`Declaration of John C. Bravman, Ph.D.
`
`
`
`
`Ex. 1104 [Reddy] at 1-2, Fig. 1.1 (“Design Flow is a term used to describe the
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`various design phases of an IC design.”).
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`39.
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`As I explain below, this disclosure maps directly to the design flow
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`steps in challenged claim 20.
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`18
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`U.S. Patent 7,247,552
`Declaration of John C. Bravman, Ph.D.
`
`
`1.
`Developing a Circuit Design
`Steps 1 through 4 of Figure 1.1 correspond to basic steps involved in
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`40.
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`developing a circuit design of an integrated circuit:
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`
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`Ex. 1104, Fig. 1.1
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`Step 1 (“Design Idea”) involves conceiving of the integrated circuit design; step 2
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`(“Behavioral description and simulation”) and step 3 (“Structural description
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`timing analysis simulation”) involve developing a behavioral and structural
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`description of that design and running simulations; and step 4 (“Schematic capture
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`Timing analysis simulation”) involves creating a schematic of the design
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`(including running a timing analysis and simulation). Ex. 1104 [Reddy] at 2-4,
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`Fig. 1.1.
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`2.
`Developing a Layout According to the Circuit Design
`In step 5 (“Layout generation using semi or fully automated EDA
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`41.
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`tools. Simulation.”) of Figure 1.1, Reddy’s design flow includes the step of
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`19
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`generating (or developing) a “layout” according to the circuit design using
`
`U.S. Patent 7,247,552
`Declaration of John C. Bravman, Ph.D.
`
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`automated computer aided tools and performing simulation:
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`
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`Ex. 1104 [Reddy] at 4-5, Fig. 1.1. “Layout generation” refers to developing a
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`representation of the planar geometric shapes of the various components, such as
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`the transistors, contacts, interconnects, and the like of the integrated circuit.
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`Generally, the layout will show the electrical components in and over the substrate
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`and the metal interconnects in different layers along with the vias in the interlevel
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`dielectric layers connecting the different metal layers. EDA is an industry standard
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`acronym for Electronic Design Automation, also referred to as ECAD, or
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`Electronic Computer Aided Design. EDA tools date from the early 1980s.
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`20
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`U.S. Patent 7,247,552
`Declaration of John C. Bravman, Ph.D.
`
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`3. Modifying the Layout
`After generating the initial layout in step 5, steps 6 (“Perform DRC”)
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`42.
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`and 7 (“Perform LVS”) involve performing design rule check (“DRC”) and layout
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`vs. schematic (“LVS”) checks:
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`
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`Ex. 1104 [Reddy] at Fig. 1.1. The LVS check “ensures that the layout is in
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`conformance with the schematic” of the circuit design, and the “design rule check
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`ensures that [the layout does not violate] the rules laid down by the fabrication
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`process technology.” Ex. 1104 [Reddy] at 5. Reddy explains that “[t]he design
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`process moves back and forth between Layout, LVS and DRC,” Ex. 1104 [Reddy]
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`at 5, and “design rules are checked” every time the “layout is modified,” Ex. 1104
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`[Reddy] at 105.
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`U.S. Patent 7,247,552
`Declaration of John C. Bravman, Ph.D.
`
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`Reddy shows in Figure 5.29 an exemplary “DRC customization
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`43.
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`window” in which des