UNITED STATES PATENT AND TRADEMARK OFFICE
`____________________________________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________________________________________
`
`Intel Corporation
`Petitioner
`
`v.
`
`VLSI Technology LLC
`Patent Owner
`
`Case IPR2019-01198
`
`DECLARATION OF JOHN C. BRAVMAN, PH.D.
`ON BEHALF OF PETITIONER
`
`Intel Exhibit 1002
`
`

`

`U.S. Patent 7,247,552
`Declaration of John C. Bravman, Ph.D.
`
`TABLE OF CONTENTS
`
`Page
`
`I.
`II.
`
`Background ...................................................................................................... 1
`Relevant Law ................................................................................................... 5
`A.
`Claim Construction ............................................................................... 5
`Obviousness ........................................................................................... 6
`B.
`Summary of Opinions ...................................................................................... 8
`III.
`IV. Brief Description of Technology ..................................................................... 8
`V.
`Overview of the ’552 Patent .......................................................................... 12
`A.
`Alleged Prior Art Problem .................................................................. 12
`B.
`Alleged Invention ................................................................................ 13
`Challenged Claims .............................................................................. 14
`C.
`D.
`Relevant Prosecution History .............................................................. 15
`VI. Overview of the Primary Prior Art References ............................................. 16
`A.
`Overview of Oda ................................................................................. 16
`B.
`Overview of Cwynar ........................................................................... 23
`C.
`Overview of Owada ............................................................................. 27
`VII. Claim Construction ........................................................................................ 32
`A.
`“force region” ...................................................................................... 32
`VIII. Level of Ordinary Skill In The Art ................................................................ 34
`IX.
`Specific Grounds for Petition ........................................................................ 34
`A.
`Ground I: Claims 1 and 2 are Obvious Over Oda in
`Combination with Cwynar. ................................................................. 34
`1. Claim 1 ......................................................................................... 35
`a)
`[1A] “An integrated circuit, comprising:” .............................. 35
`[1B] “a substrate having active circuitry” .............................. 36
`b)
`[1C] “a bond pad over the substrate” ...................................... 36
`c)
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`

`U.S. Patent 7,247,552
`Declaration of John C. Bravman, Ph.D.
`
`
`d) 
`[1D] “a force region at least under the bond pad characterized
`by being susceptible to defects due to stress applied to the bond
`pad” 37 
`e) 
`[1E] “a stack of interconnect layers, wherein each interconnect
`layer has a portion in the force region” ........................................... 39 
`f) 
`[1F] “a plurality of interlayer dielectrics separating the
`interconnect layers of the stack of interconnect layers and having at
`least one via for interconnecting two of the interconnect layers of
`the stack of interconnect layers” ..................................................... 42 
`g) 
`[1G] “wherein at least one interconnect layer of the stack of
`interconnect layers comprises a functional metal line underlying the
`bond pad that is not electrically connected to the bond pad and is
`used for wiring or interconnect to the active circuitry” .................. 45 
`h) 
`[1H] “the at least one interconnect layer of the stack of
`interconnect layers further comprising dummy metal lines in the
`portion that is in the force region to obtain a predetermined metal
`density in the portion that is in the force region” ............................ 53 
`2.  Additional Reasons to Combine Oda and Cwynar ...................... 63 
`3.  Claim 2 ......................................................................................... 66 
`a) 
`“The integrated circuit of claim 1, further comprising a
`conductive ball on the bond pad.” ................................................... 66 
`Ground II: Claim 2 is Obvious Over Oda in Combination with
`Cwynar and AAPA .............................................................................. 67 
`1.  Claim 2 ......................................................................................... 67 
`a)  The integrated circuit of claim 1, further comprising a
`conductive ball on the bond pad. .................................................... 67 
`Ground III: Claims 1 and 2 are Obvious Over Oda in
`Combination with Owada. ................................................................... 69 
`1.  Claim 1 ......................................................................................... 70 
`a) 
`[1A] “An integrated circuit, comprising” ............................... 70 
`b) 
`[1B] “a substrate having active circuitry” .............................. 70 
`c) 
`[1C] “a bond pad over the substrate” ...................................... 71 
`
`B. 
`
`C. 
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`

`U.S. Patent 7,247,552
`Declaration of John C. Bravman, Ph.D.
`
`[1D] “a force region at least under the bond pad characterized
`d)
`by being susceptible to defects due to stress applied to the bond
`pad” 73
`e)
`[1E] “a stack of interconnect layers, wherein each interconnect
`layer has a portion in the force region”; and ................................... 73
`[1F] “a plurality of interlayer dielectrics separating the
`f)
`interconnect layers of the stack of interconnect layers and having at
`least one via for interconnecting two of the interconnect layers of
`the stack of interconnect layers” ..................................................... 77
`g)
`[1G] “wherein at least one interconnect layer of the stack of
`interconnect layers comprises a functional metal line underlying the
`bond pad that is not electrically connected to the bond pad and is
`used for wiring or interconnect to the active circuitry” .................. 79
`h)
`[1H] “the at least one interconnect layer of the stack of
`interconnect layers further comprising dummy metal lines in the
`portion that is in the force region to obtain a predetermined metal
`density in the portion that is in the force region” ............................ 87
`2. Additional Reasons to Combine Oda and Owada ........................ 92
`3. Claim 2 ......................................................................................... 95
`a)
`The integrated circuit of claim 1, further comprising a
`conductive ball on the bond pad. .................................................... 95
`Availability for Cross-Examination .............................................................. 97
`X.
`XI. Right to Supplement ...................................................................................... 97
`XII.
`Jurat ................................................................................................................ 98
`
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`U.S. Patent 7,247,552
`Declaration of John C. Bravman, Ph.D.
`
`
`I, John C. Bravman, declare as follows:
`1.
`My name is John C. Bravman.
`
`I.
`
`BACKGROUND
`2.
`My academic training was at Stanford University, where I received
`
`my Bachelor of Science degree in Materials Science and Engineering in 1979, and
`
`a Master of Science degree in 1981, also in Materials Science and Engineering. I
`
`completed my Doctor of Philosophy degree in 1984, with a dissertation that
`
`focused on the nature of silicon – silicon dioxide interfaces as found in integrated
`
`circuit devices.
`
`3.
`
`From 1979 to 1984, while a graduate student at Stanford, I was
`
`employed part-time by Fairchild Semiconductor in their Palo Alto Advanced
`
`Research Laboratory. I worked in the Materials Characterization group. In 1985,
`
`upon completion of my doctorate, I joined the faculty at Stanford as Assistant
`
`Professor of Materials Science and Engineering. I was promoted to Associate
`
`Professor with tenure in 1991 and achieved the rank of Professor in 1995. In 1997 I
`
`was named to the Bing Professorship.
`
`4.
`
`At Stanford, I was Chairman of the Department of Materials Science
`
`and Engineering from 1996 to 1999, and Director of the Center for Materials
`
`Research from 1998 to 1999. I served as Senior Associate Dean of the School of
`
`Engineering from 1992 to 2001 and the Vice Provost for Undergraduate Education
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`from 1999 to 2010. On July 1, 2010, I retired from Stanford University and
`
`U.S. Patent 7,247,552
`Declaration of John C. Bravman, Ph.D.
`
`
`assumed the Presidency of Bucknell University, where I also became a Professor
`
`of Electrical Engineering.
`
`5.
`
`I have worked for more than 25 years in the areas of thin film
`
`materials processing and analysis. Much of my work has involved materials for use
`
`in microelectronic interconnects and packaging, and in superconducting structures
`
`and systems. With regard to integrated circuits, I led investigations involving
`
`aluminum, copper and tungsten metallizations, polycrystalline silicon, metal
`
`silicides, a variety of oxide and nitride dielectrics, and barrier layers such as
`
`titanium and tantalum-based nitrides. Further, my groups blended fundamental
`
`aspects of the behavior of microelectromechanical systems—specifically,
`
`compliant multilayer cantilever beams—for possible test probe and package
`
`implementations. In this work my group investigated the mechanical behavior of
`
`package underfill systems, focusing on the relationship between microstructures,
`
`processing, and adhesion. I have also led multiple development efforts of
`
`specialized equipment and methods for determining the microstructural and
`
`mechanical properties of materials and structures. My groups designed and built
`
`the first high voltage SEM for in-situ studies of electromigration, the first high
`
`temperature wafer curvature system, and the first microtensile tester for micron-
`
`scale structures, amongst many others. As a graduate student I developed one of
`
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`the earliest methodologies for obtaining high resolution cross section transmission
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`U.S. Patent 7,247,552
`Declaration of John C. Bravman, Ph.D.
`
`
`electron micrographs of integrated circuit structures.
`
`6.
`
`I have taught a wide variety of courses at the undergraduate and
`
`graduate level in materials science and engineering, emphasizing both basic
`
`science and applied technology, including coursework in the areas of integrated
`
`circuit materials and processing. Some of these courses focused on processes (e.g.,
`
`cleaning, etching, deposition, doping, oxidation, etc.) used in the production of
`
`integrated circuits. More than two thousand students have taken my classes, and I
`
`have trained 24 doctoral students, most of whom now work in the microelectronics
`
`industry.
`
`7.
`
`I am a member of many professional societies, including the Materials
`
`Research Society, the Institute of Electrical and Electronic Engineers, the
`
`American Society of Metals, and the American Physical Society. I served as
`
`President of the Materials Research Society in 1994.
`
`8.
`
`A copy of my curriculum vitae (including a list of all publications
`
`authored in the previous 10 years) is attached as Appendix A.
`
`
`
`9.
`
`I have reviewed the specification, claims, and file history of U.S.
`
`Patent No. 7,247,552 (“the ’552 patent”) (Ex. 1001). I understand that the ’552
`
`patent was filed on January 11, 2005 as U.S. Patent Application No. 11/033,009.
`
`3
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`U.S. Patent 7,247,552
`Declaration of John C. Bravman, Ph.D.
`
`
`I have also reviewed the following references, all of which I
`
`10.
`
`understand to be prior art to the ’552 patent:
`
`1.
`
`U.S. Patent Publication No. 2004/0150112, titled “Semiconductor
`
`Device and Method of Fabrication Same” (“Oda”) (Ex. 1003), filed on
`
`January 22, 2004.
`
`2.
`
`U.S. Patent Publication No. 2002/0162082, titled “Method for Making
`
`an Interconnect Layer and a Semiconductor Device Including the
`
`Same” (“Cwynar”) (Ex. 1004), filed on May 16, 2002.
`
`3.
`
`U.S. Patent No. 5,027,188, titled “Semiconductor Integrated Circuit
`
`Device in Which a Semiconductor Chip is Mounted with Solder
`
`Bumps for Mounting to a Wiring Substrate” (“Owada”) (Ex. 1005),
`
`filed on September 13, 1989.
`
`4.
`
`Applicant Admitted Prior Art (“AAPA”), particularly the features
`
`admitted to be well-known in the art, in the ’552 patent.
`
`11.
`
`I have also reviewed the exhibits and references cited in this
`
`Declaration.
`
`12.
`
`I have considered certain issues from the perspective of a person of
`
`ordinary skill in the art as described below at the time the ’552 patent application
`
`was filed.
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`U.S. Patent 7,247,552
`Declaration of John C. Bravman, Ph.D.
`
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`I have been retained by the Petitioner as an expert in the field of
`
`13.
`
`semiconductor device fabrication and design. I am working as an independent
`
`consultant in this matter and am being compensated at my normal consulting rate
`
`of $550 per hour for my time. My compensation is not dependent on and in no
`
`way affects the substance of my statements in this Declaration.
`
`14.
`
`I have no financial interest in the Petitioner. I similarly have no
`
`financial interest in the ’552 patent and have had no contact with the named
`
`inventor of the ’552 patent.
`
`II. RELEVANT LAW
`15.
`I am not an attorney. For the purposes of this declaration, I have been
`
`informed about certain aspects of the law that are relevant to my opinions. My
`
`understanding of the law is as follows:
`
`A. Claim Construction
`16.
`I have been informed that claim construction is a matter of law and
`
`that the final claim construction will ultimately be determined by the Board. For
`
`the purposes of my analysis in this proceeding and with respect to the prior art, I
`
`have been informed that IPRs are currently reviewed under “the Phillips standard.”
`
`17.
`
`I have been informed that under the Phillips standard, claim terms are
`
`given their plain and ordinary meaning as understood by a person of ordinary skill
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`in the art at the time of the invention in light of the claim language and the patent
`
`U.S. Patent 7,247,552
`Declaration of John C. Bravman, Ph.D.
`
`
`specification.
`
`18.
`
`I have been informed that embodiments described in the specification
`
`are encompassed by the claim terms.
`
`19.
`
`I have been informed that the patentee can serve as their
`
`lexicographer. As such, if a claim term is provided with a specific definition in the
`
`specification, I should interpret that claim term in light of the particular definition
`
`provided by the patentee.
`
`B. Obviousness
`20.
`I have been informed and understand that a patent claim can be
`
`considered to have been obvious to a person of ordinary skill in the art at the time
`
`the application was filed. This means that, even if all of the requirements of a
`
`claim are not found in a single prior art reference, the claim is not patentable if the
`
`differences between the subject matter in the prior art and the subject matter in the
`
`claim would have been obvious to a person of ordinary skill in the art at the time
`
`the application was filed.
`
`21.
`
`I have been informed and understand that a determination of whether
`
`a claim would have been obvious should be based upon several factors, including,
`
`among others:
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`

` the level of ordinary skill in the art at the time the application was filed;
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`U.S. Patent 7,247,552
`Declaration of John C. Bravman, Ph.D.
`
`
` the scope and content of the prior art; and
`
` what differences, if any, existed between the claimed invention and the
`
`prior art.
`
`22.
`
`I have been informed and understand that the teachings of two or
`
`more references may be combined in the same way as disclosed in the claims, if
`
`such a combination would have been obvious to one having ordinary skill in the
`
`art. In determining whether a combination based on either a single reference or
`
`multiple references would have been obvious, it is appropriate to consider, among
`
`other factors:
`
` whether the teachings of the prior art references disclose known concepts
`
`combined in familiar ways, which, when combined, would yield
`
`predictable results;
`
` whether a person of ordinary skill in the art could implement a
`
`predictable variation, and would see the benefit of doing so;
`
` whether the claimed elements represent one of a limited number of
`
`known design choices, and would have a reasonable expectation of
`
`success by those skilled in the art;
`
` whether a person of ordinary skill would have recognized a reason to
`
`combine known elements in the manner described in the claim;
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`

` whether there is some teaching or suggestion in the prior art to make the
`
`U.S. Patent 7,247,552
`Declaration of John C. Bravman, Ph.D.
`
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`modification or combination of elements claimed in the patent; and
`
` whether the claim applies a known technique that had been used to
`
`improve a similar device or method in a similar way.
`
`23.
`
`I understand that one of ordinary skill in the art has ordinary creativity
`
`and is not an automaton.
`
`24.
`
`I understand that in considering obviousness, it is important not to
`
`determine obviousness using the benefit of hindsight derived from the patent being
`
`considered.
`
`III. SUMMARY OF OPINIONS
`25.
`It is my opinion that every limitation of the structures described in
`
`claims 1 and 2 of the ’552 patent is disclosed by the prior art, and that claims 1 and
`
`2 are rendered obvious by the prior art.
`
`IV. BRIEF DESCRIPTION OF TECHNOLOGY
`26.
`Integrated circuits contain millions or even billions of tiny electronic
`
`components (e.g., transistors). These transistor structures are typically formed in
`
`and over a semiconducting substrate, such as silicon. Electrically connecting these
`
`millions or even billions of tiny transistor structures with one another so that they
`
`can electrically communicate with each other also requires millions or billions of
`
`electrically conductive pathways. To form these interconnects, engineers have
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`8
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`

`layered electrically-conductive (e.g., metal) structures over one another,
`
`U.S. Patent 7,247,552
`Declaration of John C. Bravman, Ph.D.
`
`
`surrounding them with dielectric/insulating materials for electrical insulation.
`
`27.
`
`Figure 1 of the ’552 patent, which I have colored below, is one
`
`exemplary arrangement of such an interconnect structure shown in a cross-
`
`sectional view:
`
`28.
`
`Specifically, the electrical components, such as transistors (not
`
`shown), are formed in and on the substrate 12 . Over the substrate are shown the
`
`
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`alternating layers of interconnect layers. For example, a first metal interconnect
`
`U.S. Patent 7,247,552
`Declaration of John C. Bravman, Ph.D.
`
`
`layer 26 containing conductive materials 56, 58, 60 is shown. Those conductive
`
`materials are shown in side-view and run in a direction perpendicular to the cross-
`
`section, so that they can provide electrical pathways for electricity to flow. These
`
`electrical pathways can carry electrical signals or power. Moreover, these
`
`conductive materials are electrically isolated from each other by dielectric material
`
`62. Ex. 1001 [’552 patent] at 3:35-38. One example, among many, of a
`
`conductive material is copper and one example, among many, of a dielectric
`
`material is silica.
`
`29.
`
`In addition to the metals running in a direction perpendicular to the
`
`cross-section, the metals can also run vertically by introducing structures called
`
`vias. To form such vias, metal interconnect layer 26 can be polished, and
`
`interlevel dielectric layer 24 can be deposited on top of that metal layer. Vertical
`
`pathways connecting the wires in first metal interconnect layer 26 to wires in one
`
`or more different metal interconnect layers are then formed in the interlevel
`
`dielectric layer 24 to create via 59 (purple), over with the metal interconnect layer
`
`22 is formed so that conductive material 50 is electrically connected to the
`
`conductive material 58. This process of forming alternating metal interconnect
`
`layers 22, 18 and 14 and interlevel dielectric layers 20 and 16 is then repeated.
`
`Ex. 1001 [’552 patent] at 2:64-67, 3:9-10, 3:35-38, Fig. 1.
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`

`30. When all the desired layers of the integrated circuit are formed, the
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`U.S. Patent 7,247,552
`Declaration of John C. Bravman, Ph.D.
`
`
`top interconnect metal layer can be used to make electrical connections to other
`
`external components (e.g., to other components on a printed circuit board or other
`
`semiconductor devices). The metals in the top interconnect metal layer used to
`
`make such external connections are generally called “bond pads” because they
`
`serve as a pad to form bonds with additional metal structures that are placed
`
`thereon. For example, the ’552 patent explains that some examples of these pads
`
`include “wire bond pad, a probe pad, a flip-chip bump pad, a test point or other
`
`packaging or test pad structures.” Ex. 1001 [’552 patent] at 2, 42-45. As an
`
`example, Figure 1 shows a conductive ball 28 on bond pad 32. Ex. 1001 [’552
`
`patent] at 3:10-12, 3:20-25.
`
`31.
`
`These interconnects that electrically connect different electrical
`
`components (e.g., transistors) together to deliver electrical signals/power are often
`
`called “active” metal interconnects. In addition, “dummy” metals are often added
`
`as “filler” material. These dummy metals are often not electrically connected to
`
`other metal structures – hence, they electrically “float.” Nevertheless, dummy
`
`structures can be connected to other metal structures. For example, dummy metals
`
`can be connected to another dummy metal in a different layer through a via.
`
`Alternatively, a dummy metal can be connected to a dummy bond pad through a
`
`via. Engineers have long been adding such “dummy” metal fillers because they
`
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`

`can provide a number of desired effects. For example, it was well-known that
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`U.S. Patent 7,247,552
`Declaration of John C. Bravman, Ph.D.
`
`
`adding dummy fillers can provide added structural protection to certain areas of the
`
`integrated circuit as metals provide more mechanical robustness compared to
`
`potentially brittle dielectric materials. As another example, it was well-known that
`
`the rate of polishing can be controlled by introducing a desired amount of metal,
`
`which can ultimately lead to improved planarity of the interconnect layers during
`
`polishing.
`
`V. OVERVIEW OF THE ’552 PATENT
`A. Alleged Prior Art Problem
`32.
`The ’552 patent notes that “[t]he use of conductive balls, such as
`
`solder balls, to make electrical connection to a bond pad is a known method to
`
`make electrical connection to electrical circuitry of a semiconductor die. Ex. 1001
`
`[’552 patent] at 1:25-28. The ’552 patent further notes that “[b]ecause the
`
`advanced low-k interlayer dielectrics used today have a lower dielectric constant
`
`and lower Young's modulus than dielectrics used in earlier generation products,
`
`flip chip die attach may more easily mechanically fracture the underlying Stack of
`
`metal and dielectric layers. Ex. 1001 [’552 patent] at 1:42-46. Moreover, the ’552
`
`patent notes that “a known method to address the stresses present underlying a
`
`bond pad is to use a dedicated Support structure. A common structure is the use of
`
`at least two metal layers under the bonding pad that are connected together and to
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`the bonding pad by large arrays of vias distributed across a majority of the bond
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`U.S. Patent 7,247,552
`Declaration of John C. Bravman, Ph.D.
`
`
`pad area.” Ex. 1001 [’552 patent] at 1:53-58. Furthermore, the ’552 patent notes
`
`that “[a]nother known method of mitigating stresses in a bond pad region is to
`
`replace low-k dielectric layers with higher k dielectric and higher elastic modulus
`
`dielectric layers until the die exhibits resistance to cracking.” Ex. 1001 [’552
`
`patent] at 1:65-2:4. In other words, the ’552 patent notes that just about all of the
`
`structures claimed in claims 1 and 2 were known in the prior art. The ’552 patent,
`
`however, notes that the shrinking die sizes and more brittle dielectric materials
`
`render them more susceptible to damage due to the “increased stress to the bond
`
`pad structure when physical connection is made to the semiconductor die.” Ex.
`
`1001 [’552 patent] at Abstract, 1:42-46.
`
`B. Alleged Invention
`33.
`The ’552 patent alleges that such problems can be solved by first
`
`defining a “force region” that is beneath and around the bond pad, and adding
`
`“dummy” metal lines in the interconnect layers to “increase the metal density of
`
`the interconnect layers.” Ex. 1001 [’552 patent] at Abstract, 4:37-56. However,
`
`adding dummy metal lines to increase the metal density of the interconnect layers
`
`was already well known and disclosed in the prior art. For example, (1) Oda
`
`teaches using “dummy patterns” in interconnect layers; (2) Owada teaches adding
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`

`“dummy lines;” and (3) Cwynar teaches using “lines or traces” in regions that it
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`U.S. Patent 7,247,552
`Declaration of John C. Bravman, Ph.D.
`
`
`calls “dummy fill features.”
`
`C. Challenged Claims
`34.
`In my opinion, claims 1 and 2 of the ’552 patent are not patentable.
`
`Independent claim 1 recites:
`
`1. An integrated circuit, comprising:
`a substrate having active circuitry;
`a bond pad over the substrate;
`a force region at least under the bond pad characterized by
`being susceptible to defects due stress applied to the bond pad;
`a stack of interconnect layers, wherein each interconnect layer
`has a portion in the force region; and
`a plurality of interlayer dielectrics separating the interconnect
`layers of the stack of interconnect layers and having at least one via
`for interconnecting two of the interconnect layers of the stack of
`interconnect layers;
`wherein at least one interconnect layer of the stack of
`interconnect layers comprises a functional metal line underlying the
`bond pad that is not electrically connected to the bond pad and is used
`for wiring or interconnect to the active circuitry, the at least one
`interconnect layer of the stack of interconnect layers further
`comprising dummy metal lines in the portion that is in the force
`region to obtain a predetermined metal density in the portion that is in
`the force region.
`
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`

`35.
`
`Claim 2 recites:
`
`U.S. Patent 7,247,552
`Declaration of John C. Bravman, Ph.D.
`
`
`The integrated circuit of claim 1, further comprising a
`2.
`conductive ball on the bond pad.
`
`D. Relevant Prosecution History
`36.
`I have been informed that the ’552 patent issued from U.S.
`
`Application No. 11/033,009, filed January 11, 2005. I understand that during
`
`prosecution, the Examiner initially rejected all original claims over U.S. Patent
`
`Publication No. 2005/0082577 (“Usui”). Ex. 1006 [Jan. 24, 2007 Non-Final
`
`Rejection] at 3-7. I further understand that the applicant amended (among other
`
`things) challenged claim 1 with the following underlined language to recite “a
`
`force region at least under the bond pad characterized by being susceptible to
`
`defects due to stress applied to the bond pad; … wherein at least one interconnect
`
`layer of the stack of interconnect layers comprises a functional metal line
`
`underlying the bond pad that is not electrically connected to the bond pad and is
`
`used for wiring or interconnect to the active circuitry, the at least one interconnect
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`layer of the stack of interconnect layers further comprising dummy metal lines in
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`the portion that is in the force region.” Ex. 1007 [Apr. 5, 2007 Response to Office
`
`Action] at 3. I understand that the applicant argued that the amended claim
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`distinguished Usui because the functional metal in Usui is electrically connected to
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`the bond pad. Ex. 1007 [Apr. 5, 2007 Response to Office Action] at 8-9. I further
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`understand that the Examiner allowed claim 1 as amended, Ex. 1008 [May 25,
`
`U.S. Patent 7,247,552
`Declaration of John C. Bravman, Ph.D.
`
`
`2007 Notice of Allowability] at 2, and claim 1 was later corrected to add “to” in
`
`the phrase “defects due to stress,” Ex. 1009 [Certificate of Correction].
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`VI. OVERVIEW OF THE PRIMARY PRIOR ART REFERENCES
`37.
`In my opinion, there is nothing novel or inventive in claims 1 and 2 of
`
`the ’552 patent. The concept claimed by the ’552 patent, such as “adding dummy
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`metal lines to increase the metal density of the interconnect layers,” was well-
`
`known long before the ’552 patent was filed. My opinions are discussed in greater
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`detail below, but I, first, provide brief summaries of the prior art references, Oda,
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`Cwynar, and Owada.
`
`A. Overview of Oda
`38.
`Oda, like the ’552 patent, notes that mechanical damage, such as
`
`cracking, can occur below the bond pad when load is applied to the bond pad. Ex.
`
`1003 [Oda] at [0005] (“As a result, stress that occurs when bonding is exerted upon
`
`passivation insulation film 740 and interlevel dielectric film 750 that underlie
`
`bonding portion 735. The influence of stress upon copper interconnect 700 during
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`bonding can thus be reduced and the exposure of copper interconnects 700 on the
`
`surface can be prevented..”); Ex. 1003 [Oda] at [0008] (“Further, if a low-k film
`
`that has a lower relative dielectric constant than an oxide film is present below the
`
`bonding portion, the load of a needle during probing or bonding depresses the
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`16
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`

`

`bonding pads and may cause cracks in the interlevel dielectric film that underlies
`
`U.S. Patent 7,247,552
`Declaration of John C. Bravman, Ph.D.
`
`
`the bonding pads or may cause film to peel in the bonding pads.”); Ex. 1003 [Oda]
`
`at Abstract.
`
`39.
`
`Oda addresses this issue by adding “dummy” metal patterns below a
`
`bond pad—which improves the mechanical integrity of the area underlying the
`
`bond pad by distributing the shock applied to the bond pad. Ex. 1003 [Oda] at
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`[0055] (“‘[D]ummy patterns’ … function as dummy layers for distributing the
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`shock applied to bonding pad 130.”); Ex. 1003 [Oda] at [0074].
`
`40.
`
`Oda adds “dummy” patterns below a bond pad, as shown in Figure
`
`2A, to improve the mechanical integrity by distributing the shock applied to the
`
`bond pad. Ex. 1003 [Oda] at [0055] (“The patterns of upper copper layer 100 and
`
`lower copper layer 200 are referred to as “dummy patterns” in the following
`
`explanation based on the view that upper copper layer 100 and lower copper layer
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`200, rather than constituting the interconnects of internal circuits, function as
`
`dummy layers for distributing the shock applied to bonding pad 130.”); Ex. 1003
`
`[Oda] at [0074]. I have reproduced below Oda’s Figure 2A and have added colors:
`
`17
`
`

`

`U.S. Patent 7,247,552
`Declaration of John C. Bravman, Ph.D.
`
`
`
`
`Ex. 1003 [Oda] at Fig. 2A. As shown, the dummy patterns 110 and 120 are under
`
`the bond pad 130. These two layers 110 and 120 are collectively called “upper
`
`copper layer 100.” Ex. 1003 [Oda] at [0050]. Further below, the two layers 210
`
`and 220 are collectively called “lower copper layer 200”. Ex. 1003 [Oda] at
`
`[0052].
`
`41.
`
`Oda explains that these ‘dummy patterns’ … [in] upper copper layer
`
`100 and lower copper layer 200, rather than constituting the interconnects of
`
`internal circuits, function as dummy layers for distributing the shock applied to
`
`bonding pad 130.” Ex. 1003 [Oda] at [0055]. In other words, the “dummy
`
`patterns” are added to help avoid mechanical damage resulting from stress during
`
`bonding but are not used as active interconnects.
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`18
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`

`

`U.S. Patent 7,247,552
`Declaration of John C. Bravman, Ph.D.
`
`
`Oda’s Figures 2B and 2C that I have colored below show two
`
`42.
`
`exemplary (among many that are possible) dummy patterns in first upper copper
`
`layer 110 and lower copper layer 210, respectively, viewed from the top. Ex. 1003
`
`[Oda] at [0107] (“[T]he dummy patterns … are not limited to the shapes that are
`
`shown in FIG. 2B and FIG. 2[C], and other patterns may be applied.”).
`
`43.
`
`As shown in these two examples, metal dummy patterns coexists with
`
`dielectric material 14:
`
`
`
`
`
`Ex. 1003 [Oda] at Fig. 2B, 2C, [0057] (“square-shaped patterns of a plurality of
`
`laminated dielectric films 34 are scattered in the dummy pattern of first uppe