OBSOLETE
`
`ADC08131, ADC08134, ADC08138
`
`www.ti.com
`
`SNAS066D –JUNE 1999 –REVISED APRIL 2013
`
`ADC08131/ADC08134/ADC08138 8-Bit High-Speed Serial I/O A/D Converters with
`Multiplexer Options, Voltage Reference, and Track/Hold Function
`
`Check for Samples: ADC08131, ADC08134, ADC08138
`
`DESCRIPTION
`8-bit
`are
`The ADC08131/ADC08134/ADC08138
`successive approximation A/D converters with serial
`I/O and configurable input multiplexers with up to 8
`channels. The serial I/O is configured to comply with
`the MICROWIRE serial data exchange standard for
`easy interface to the COPS™ family of controllers,
`and can easily interface with standard shift registers
`or microprocessors.
`All three devices provide a 2.5V band-gap derived
`reference
`with
`ensured
`performance
`over
`temperature.
`A track/hold function allows the analog voltage at the
`positive input
`to vary during the actual A/D
`conversion.
`The analog inputs can be configured to operate in
`various combinations of single-ended, differential, or
`pseudo-differential modes. In addition, input voltage
`spans as small as 1V can be accommodated.
`
`1FEATURES
`23• Serial Digital Data Link Requires Few I/O Pins
`• Analog Input Track/Hold Function
`•
`4- or 8-Channel Input Multiplexer Options with
`Address Logic
`• On-Chip 2.5V Band-Gap Reference (±2% Over
`Temperature Ensured)
`• No Zero or Full Scale Adjustment Required
`• TTL/CMOS Input/Output Compatible
`•
`0V to 5V Analog Input Range with Single 5V
`Power Supply
`
`APPLICATIONS
`• Digitizing Automotive Sensors
`• Process Control/Monitoring
`• Remote Sensing in Noisy Environments
`• Embedded Diagnostics
`
`KEY SPECIFICATIONS
`• Resolution: 8 Bits
`• Conversion Time (fC = 1 MHz): 8 µs (Max)
`• Power Dissipation: 20 mW (Max)
`• Single Supply: 5 VDC (±5%)
`• Total Unadjusted Error: ±½ LSB and ±1 LSB
`• Linearity Error (VREF = 2.5V): ±½ LSB
`• No Missing Codes (Over Temperature)
`• On-Board Reference: +2.5V ±1.5% (Max)
`
`1
`
`Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
`Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
`2COPS is a trademark of Texas Instruments.
`3All other trademarks are the property of their respective owners.
`
`PRODUCTION DATA information is current as of publication date.
`Products conform to specifications per the terms of
`the Texas
`Instruments standard warranty. Production processing does not
`necessarily include testing of all parameters.
`
`Copyright © 1999–2013, Texas Instruments Incorporated
`
`Curt - Exhibit 1019 - 1
`
`

`

`OBSOLETE
`
`ADC08131, ADC08134, ADC08138
`
`SNAS066D –JUNE 1999 –REVISED APRIL 2013
`
`Connection Diagrams
`
`www.ti.com
`
`Figure 1. ADC08138CIWM Small Outline Packages
`
`Figure 2. ADC08134CIWM Small Outline Packages
`
`Figure 3. ADC08131CIWM Small Outline Package
`
`2
`
`Submit Documentation Feedback
`
`Copyright © 1999–2013, Texas Instruments Incorporated
`
`Product Folder Links: ADC08131 ADC08134 ADC08138
`
`Curt - Exhibit 1019 - 2
`
`

`

`OBSOLETE
`
`ADC08131, ADC08134, ADC08138
`
`www.ti.com
`
`SNAS066D –JUNE 1999 –REVISED APRIL 2013
`
`These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
`during storage or handling to prevent electrostatic damage to the MOS gates.
`
`Absolute Maximum Ratings(1)(2)(3)
`Supply Voltage (VCC)
`Voltage at Inputs and Outputs
`Input Current at Any Pin (4)
`Package Input Current(4)
`Power Dissipation at TA = 25°C (5)
`ESD Susceptibility (6)
`
`Soldering Information
`
`Storage Temperature
`
`N Package (10 sec.)
`
`SOIC Package
`
`Vapor Phase (60 sec.)
`Infrared (15 sec.)
`
`6.5V
`−0.3V to VCC + 0.3V
`±5 mA
`±20 mA
`800 mW
`1500V
`260°C
`215°C
`220°C
`−65°C to +150°C
`
`(1) All voltages are measured with respect to AGND = DGND = 0 VDC, unless otherwise specified.
`(2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
`(3)
`If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
`specifications.
`(4) When the input voltage (VIN) at any pin exceeds the power supplies (VIN < (AGND or DGND) or VIN > AVCC) the current at that pin
`should be limited to 5 mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power
`supplies with an input current of 5 mA to four pins.
`(5) The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA and the ambient temperature,
`TA. The maximum allowable power dissipation at any temperature is PD = (TJMAX − TA)/θJA or the number given in the Absolute
`Maximum Ratings, whichever is lower. For these devices TJMAX = 125°C. The typical thermal resistances (θJA) of these parts when
`board mounted for the ADC 08131 and the ADC08134 is 140°C/W and 91°C/W for the ADC08138.
`(6) Human body model, 100 pF capacitor discharged through a 1.5 kΩ resistor.
`
`Operating Ratings(1)(2)
`Temperature Range (TMIN ≤ TA ≤ TMAX)
`Supply Voltage (VCC)
`
`−40°C ≤ TA ≤ +85°C
`4.5 VDC to 6.3 VDC
`
`(1) Operating Ratings indicate conditions for which the device is functional. These ratings do not ensure specific performance limits. For
`ensured specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test
`conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.
`(2) All voltages are measured with respect to AGND = DGND = 0 VDC, unless otherwise specified.
`
`Copyright © 1999–2013, Texas Instruments Incorporated
`
`Submit Documentation Feedback
`
`3
`
`Product Folder Links: ADC08131 ADC08134 ADC08138
`
`Curt - Exhibit 1019 - 3
`
`

`

`ADC08131, ADC08134, ADC08138
`
`OBSOLETE
`
`SNAS066D –JUNE 1999 –REVISED APRIL 2013
`
`www.ti.com
`
`Electrical Characteristics
`The following specifications apply for VCC = +5 VDC, VREF = +2.5 VDC and fCLK = 1 MHz unless otherwise specified. Boldface
`limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25°C.
`
`Symbol
`
`Parameter
`
`Conditions
`
`Typical(1)
`
`Limits(2)
`
`CONVERTER AND MULTIPLEXER CHARACTERISTICS
`Linearity Error
`VREF = +2.5 VDC
`Full Scale Error
`VREF = +2.5 VDC
`Zero Error
`VREF = +2.5 VDC
`(3)
`Total Unadjusted Error
`VREF = +5 VDC
`Differential Linearity
`VREF = +2.5 VDC
`
`RREF
`
`VIN
`
`Reference Input Resistance
`
`Analog Input Voltage
`
`DC Common-Mode Error
`
`Power Supply Sensitivity
`
`On Channel Leakage Current (6)
`
`Off Channel Leakage Current(6)
`
`DIGITAL AND DC CHARACTERISTICS
`Logical “1” Input Voltage
`VIN(1)
`VIN(0)
`Logical “0” Input Voltage
`IIN(1)
`Logical “1” Input Current
`IIN(0)
`Logical “0” Input Current
`
`VOUT(1)
`
`Logical “1” Output Voltage
`
`VOUT(0)
`
`Logical “0” Output Voltage
`
`See (4)
`
`See (5)
`
`VREF = 2.5 VDC
`VCC = +5V ±5%,
`VREF = +2.5 VDC
`On Channel = 5V,
`Off Channel = 0V
`On Channel = 0V,
`Off Channel = 5V
`On Channel = 5V,
`Off Channel = 0V
`On Channel = 0V,
`Off Channel = 5V
`
`VCC = 5.25V
`VCC = 4.75V
`VIN = 5.0V
`VIN = 0V
`VCC = 4.75V:
`IOUT = −360 µA
`IOUT = −10 µA
`VCC = 4.75V
`IOUT = 1.6 mA
`
`3.5
`
`±1
`±1
`±1
`±1
`8
`
`1.3
`6.0
`(VCC + 0.05)
`(GND − 0.05)
`±½
`
`±¼
`
`0.2
`1
`−0.2
`−1
`−0.2
`−1
`0.2
`1
`
`2.0
`0.8
`1
`−1
`
`2.4
`4.5
`0.4
`
`Units
`(Limits)
`
`LSB (max)
`LSB (max)
`LSB (max)
`LSB (max)
`Bits (min)
`kΩ
`kΩ (min)
`kΩ (max)
`V (max)
`V (min)
`LSB (max)
`
`LSB (max)
`
`µA (max)
`
`µA (max)
`
`µA (max)
`
`µA (max)
`
`V (min)
`V (max)
`µA (max)
`µA (max)
`
`V (min)
`V (min)
`V (max)
`
`(1) Typicals are at TJ = 25°C and represent the most likely parametric norm.
`(2) Ensured to AOQL (Average Outgoing Quality Level).
`(3) Total unadjusted error includes zero, full-scale, linearity, and multiplexer error. Total unadjusted error with VREF = +5V only applies to the
`ADC08134 and ADC08138. See Note 7 on the following page.
`(4) Cannot be tested for the ADC08131.
`(5) For VIN(−) ≥ VIN(+) the digital code will be 0000 0000. Two on-chip diodes are tied to each analog input (see ADC08138 Simplified Block
`Diagram) which will forward-conduct for analog input voltages one diode drop below ground or one diode drop greater than VCC supply.
`During testing at low VCC levels (e.g., 4.5V), high level analog inputs (e.g., 5V) can cause an input diode to conduct, especially at
`elevated temperatures. This will cause errors for analog inputs near full-scale. The specification allows 50 mV forward bias of either
`diode; this means that as long as the analog VIN does not exceed the supply voltage by more than 50 mV, the output code will be
`correct. Exceeding this range on an unselected channel will corrupt the reading of a selected channel. Achievement of an absolute 0
`VDC to 5 VDC input voltage range will therefore require a minimum supply voltage of 4.950 VDC over temperature variations, initial
`tolerance and loading.
`(6) Channel leakage current is measured after a single-ended channel is selected and the clock is turned off. For off channel leakage
`current the following two cases are considered: one, with the selected channel tied high (5 VDC) and the remaining seven off channels
`tied low (0 VDC), total current flow through the off channels is measured; two, with the selected channel tied low and the off channels
`tied high, total current flow through the off channels is again measured. The two cases considered for determining on channel leakage
`current are the same except total current flow through the selected channel is measured.
`
`4
`
`Submit Documentation Feedback
`
`Copyright © 1999–2013, Texas Instruments Incorporated
`
`Product Folder Links: ADC08131 ADC08134 ADC08138
`
`Curt - Exhibit 1019 - 4
`
`

`

`OBSOLETE
`
`ADC08131, ADC08134, ADC08138
`
`www.ti.com
`
`SNAS066D –JUNE 1999 –REVISED APRIL 2013
`
`Electrical Characteristics (continued)
`The following specifications apply for VCC = +5 VDC, VREF = +2.5 VDC and fCLK = 1 MHz unless otherwise specified. Boldface
`limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25°C.
`
`Symbol
`
`Parameter
`
`Conditions
`
`Typical(1)
`
`Limits(2)
`
`IOUT
`
`ISOURCE
`ISINK
`
`ICC
`
`TRI-STATE Output Current
`
`Output Source Current
`Output Sink Current
`Supply Current
`ADC08134, ADC08138
`ADC08131 (7)
`
`VOUT = 0V
`VOUT = 5V
`VOUT = 0V
`VOUT = VCC
`
`CS = HIGH
`
`−3.0
`3.0
`−6.5
`8.0
`
`3.0
`6.0
`
`Units
`(Limits)
`µA (max)
`µA (max)
`mA (min)
`mA (min)
`
`mA (max)
`mA (max)
`
`(7) For the ADC08131 VREFIN is internally tied to the on chip 2.5V band-gap reference output; therefore, the supply current is larger
`because it includes the reference current (700 µA typical, 2 mA maximum).
`
`Electrical Characteristics
`The following specifications apply for VCC = +5 VDC, and fCLK = 1 MHz unless otherwise specified. Boldface limits apply for
`TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25°C.
`
`Symbol
`
`Parameter
`
`Conditions
`
`Typical(1)
`
`Limits(2)
`
`REFERENCE CHARACTERISTICS
`
`VREFOUT
`
`ΔVREF/ΔT
`
`Output Voltage
`
`DC08134, ADC08138
`
`Temperature Coefficient
`
`Sourcing
`(0 ≤ IL ≤ +4 mA)
`ADC08134,
`ADC08138
`Sourcing
`(0 ≤ IL ≤ +2 mA)
`ADC08131
`Sinking
`(−1 ≤ IL ≤ 0 mA)
`ADC08134,
`ADC08138
`Sinking
`(−1 ≤ IL ≤ 0 mA)
`ADC08131
`4.75V ≤ VCC ≤ 5.25V
`VREF = 0V
`ADC08134,
`ADC08138
`VREF = 0V
`ADC08131
`VCC: 0V → 5V
`CL = 100 µF
`
`ΔVREF/ΔIL
`
`Load Regulation (3)
`
`Line Regulation
`
`Short Circuit Current
`
`Start-Up Time
`
`ISC
`
`TSU
`
`ΔVREF/Δt
`
`Long Term Stability
`
`2.5 ±1.5%
`
`0.1
`
`0.1
`
`0.5
`
`0.5
`
`6
`
`25
`
`25
`
`2.5
`±2%
`40
`
`0.003
`
`0.003
`
`0.2
`
`0.2
`
`0.5
`
`8
`
`8
`
`20
`
`200
`
`Units
`(Limits)
`
`V
`
`ppm/°C
`
`%/mA
`(max)
`
`mV (max)
`
`mA
`(max)
`
`ms
`
`ppm/1 kHr
`
`(1) Typicals are at TJ = 25°C and represent the most likely parametric norm.
`(2) Ensured to AOQL (Average Outgoing Quality Level).
`(3) Load regulation test conditions and specifications for the ADC08131 differ from those of the ADC08134 and ADC08138 because the
`ADC08131 has the on-board reference as a permanent load.
`
`Copyright © 1999–2013, Texas Instruments Incorporated
`
`Submit Documentation Feedback
`
`5
`
`Product Folder Links: ADC08131 ADC08134 ADC08138
`
`Curt - Exhibit 1019 - 5
`
`

`

`ADC08131, ADC08134, ADC08138
`
`OBSOLETE
`
`SNAS066D –JUNE 1999 –REVISED APRIL 2013
`
`www.ti.com
`
`Electrical Characteristics
`The following specifications apply for VCC = +5 VDC, VREF = +2.5 VDC and tr = tf = 20 ns unless otherwise specified. Boldface
`limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25°C.
`Symbol
`Parameter
`Conditions
`
`fCLK
`
`Clock Frequency
`
`Clock Duty Cycle (3)
`
`Conversion Time (Not Including
`MUX Addressing Time)
`Acquisition Time
`CLK High while CS is High
`CS Falling Edge or Data Input
`Valid to CLK Rising Edge
`Data Input Valid after CLK Rising Edge
`
`fCLK = 1 MHz
`
`CL = 100 pF:
`CLK Falling Edge to Output Data Valid (4) Data MSB First
`Data LSB First
`CL = 10 pF, RL = 10 kΩ
`(see TRI-STATE Test Circuits
`and Waveforms)
`CL = 100 pF, RL = 2 kΩ
`
`TRI-STATE Delay from Rising Edge of
`CS to Data Output and SARS Hi-Z
`
`Capacitance of Logic Inputs
`Capacitance of Logic Outputs
`
`TC
`
`tCA
`tSELECT
`
`tSET-UP
`
`tHOLD
`
`tpd1, tpd0
`
`t1H, t0H
`
`CIN
`COUT
`
`Typical(1)
`10
`
`Limits(2)
`
`1
`40
`60
`8
`8
`½
`
`25
`
`20
`
`250
`200
`
`180
`
`50
`
`50
`
`5
`5
`
`Units (Limits)
`kHz (min)
`MHz (max)
`% (min)
`% (max)
`1/fCLK (max)
`µs (max)
`1/fCLK (max)
`ns
`
`ns (min)
`
`ns (min)
`
`ns (max)
`ns (max)
`
`ns
`
`ns (max)
`pF
`pF
`
`(1) Typicals are at TJ = 25°C and represent the most likely parametric norm.
`(2) Ensured to AOQL (Average Outgoing Quality Level).
`(3) A 40% to 60% duty cycle range insures proper operation at all clock frequencies. In the case that an available clock has a duty cycle
`outside of these limits the minimum time the clock is high or low must be at least 450 ns. The maximum time the clock can be high or
`low is 100 µs.
`(4) Since data, MSB first, is the output of the comparator used in the successive approximation loop, an additional delay is built in (see
`ADC08138 Simplified Block Diagram) to allow for comparator response time.
`
`6
`
`Submit Documentation Feedback
`
`Copyright © 1999–2013, Texas Instruments Incorporated
`
`Product Folder Links: ADC08131 ADC08134 ADC08138
`
`Curt - Exhibit 1019 - 6
`
`

`

`OBSOLETE
`
`ADC08131, ADC08134, ADC08138
`
`www.ti.com
`
`SNAS066D –JUNE 1999 –REVISED APRIL 2013
`
`ADC08138 Simplified Block Diagram
`
`Copyright © 1999–2013, Texas Instruments Incorporated
`
`Submit Documentation Feedback
`
`7
`
`Product Folder Links: ADC08131 ADC08134 ADC08138
`
`Curt - Exhibit 1019 - 7
`
`

`

`ADC08131, ADC08134, ADC08138
`
`OBSOLETE
`
`SNAS066D –JUNE 1999 –REVISED APRIL 2013
`
`www.ti.com
`
`Typical Converter Performance Characteristics(1)
`Linearity Error vs Reference Voltage
`Linearity Error vs Temperature
`
`Figure 4.
`
`Figure 5.
`
`Linearity Error vs Clock Frequency
`
`Power Supply Current vs Temperature
`(ADC08138, ADC08134)
`
`Figure 6.
`
`Figure 7.
`
`Output Current vs Temperature
`
`Power Supply Current vs Clock Frequency
`
`Figure 8.
`
`Figure 9. (2)
`
`(1) For ADC08131 add IREF
`(2) For the ADC08131 VREFIN is internally tied to the on chip 2.5V band-gap reference output; therefore, the supply current is larger
`because it includes the reference current (700 µA typical, 2 mA maximum).
`
`8
`
`Submit Documentation Feedback
`
`Copyright © 1999–2013, Texas Instruments Incorporated
`
`Product Folder Links: ADC08131 ADC08134 ADC08138
`
`Curt - Exhibit 1019 - 8
`
`

`

`OBSOLETE
`
`ADC08131, ADC08134, ADC08138
`
`www.ti.com
`
`SNAS066D –JUNE 1999 –REVISED APRIL 2013
`
`Typical Reference Performance Characteristics
`Load Regulation(1)
`Line Regulation (3 Typical Parts)
`
`Figure 10.
`
`Figure 11.
`
`Output Drift vs Temperature (3 Typical Parts)
`
`Available Output Current vs Supply Voltage
`
`Figure 12.
`
`Figure 13.
`
`(1) Load regulation test conditions and specifications for the ADC08131 differ from those of the ADC08134 and ADC08138 because the
`ADC08131 has the on-board reference as a permanent load.
`
`Copyright © 1999–2013, Texas Instruments Incorporated
`
`Submit Documentation Feedback
`
`9
`
`Product Folder Links: ADC08131 ADC08134 ADC08138
`
`Curt - Exhibit 1019 - 9
`
`

`

`ADC08131, ADC08134, ADC08138
`
`OBSOLETE
`
`SNAS066D –JUNE 1999 –REVISED APRIL 2013
`
`www.ti.com
`
`TRI-STATE Test Circuits and Waveforms
`
`Figure 14. t1H
`
`Figure 15. t1H
`
`Figure 16. t0H
`
`Figure 17. t0H
`
`Timing Diagrams
`
`*To reset these devices, CLK and CS must be simultaneously high for a period of tSELECT or greater. Otherwise these
`devices are compatible with industry standards ADC0831/4/8.
`Figure 18. Data Input Timing
`
`Figure 19. Data Output Timing
`
`10
`
`Submit Documentation Feedback
`
`Copyright © 1999–2013, Texas Instruments Incorporated
`
`Product Folder Links: ADC08131 ADC08134 ADC08138
`
`Curt - Exhibit 1019 - 10
`
`

`

`www.ti.com
`
`SNAS066D –JUNE 1999 –REVISED APRIL 2013
`
`OBSOLETE
`
`ADC08131, ADC08134, ADC08138
`
`Figure 20. ADC08131 Start Conversion Timing
`
`*LSB first output not available on ADC08131.
`LSB information is maintained for remainder of clock periods until CS goes high.
`Figure 21. ADC08131 Timing
`
`Figure 22. ADC08134 Timing
`
`Copyright © 1999–2013, Texas Instruments Incorporated
`
`Submit Documentation Feedback
`
`11
`
`Product Folder Links: ADC08131 ADC08134 ADC08138
`
`Curt - Exhibit 1019 - 11
`
`

`

`ADC08131, ADC08134, ADC08138
`
`OBSOLETE
`
`SNAS066D –JUNE 1999 –REVISED APRIL 2013
`
`www.ti.com
`
`*Make sure clock edge #18 clocks in the LSB before SE is taken low
`Figure 23. ADC08138 Timing
`
`12
`
`Submit Documentation Feedback
`
`Copyright © 1999–2013, Texas Instruments Incorporated
`
`Product Folder Links: ADC08131 ADC08134 ADC08138
`
`Curt - Exhibit 1019 - 12
`
`

`

`OBSOLETE
`
`ADC08131, ADC08134, ADC08138
`
`www.ti.com
`
`SNAS066D –JUNE 1999 –REVISED APRIL 2013
`
`ADC08138 Functional Block Diagram
`
`*Some of these functions/pins are not available with other options.
`For the ADC08134, the “SEL 1” Flip-Flop is bypassed. For the ADC08131, VREFOUT and VREFIN are internally tied
`together.
`
`Copyright © 1999–2013, Texas Instruments Incorporated
`
`Submit Documentation Feedback
`
`13
`
`Product Folder Links: ADC08131 ADC08134 ADC08138
`
`Curt - Exhibit 1019 - 13
`
`

`

`ADC08131, ADC08134, ADC08138
`
`OBSOLETE
`
`SNAS066D –JUNE 1999 –REVISED APRIL 2013
`
`www.ti.com
`
`Functional Description
`
`MULTIPLEXER ADDRESSING
`The design of these converters utilizes a comparator structure with built-in sample-and-hold which provides for a
`differential analog input to be converted by a successive approximation routine.
`The actual voltage converted is always the difference between an assigned “+” input terminal and a “−” input
`terminal. The polarity of each input terminal of the pair indicates which line the converter expects to be the most
`positive. If the assigned “+” input voltage is less than the “−” input voltage the converter responds with an all
`zeros output code.
`A unique input multiplexing scheme has been utilized to provide multiple analog channels with software-
`configurable single-ended, differential, or pseudo-differential (which will convert
`the difference between the
`voltage at any analog input and a common terminal) operation. The analog signal conditioning required in
`transducer-based data acquisition systems is significantly simplified with this type of
`input
`flexibility. One
`converter package can now handle ground referenced inputs and true differential inputs as well as signals with
`some arbitrary reference voltage.
`A particular input configuration is assigned during the MUX addressing sequence, prior to the start of a
`conversion. The MUX address selects which of the analog inputs are to be enabled and whether this input is
`single-ended or differential. Differential inputs are restricted to adjacent channel pairs. For example, channel 0
`and channel 1 may be selected as a differential pair but channel 0 or 1 cannot act differentially with any other
`channel. In addition to selecting differential mode the polarity may also be selected. Channel 0 may be selected
`as the positive input and channel 1 as the negative input or vice versa. This programmability is best illustrated by
`the MUX addressing codes shown in the following tables for the various product options.
`The MUX address is shifted into the converter via the DI line. Because the ADC08131 contains only one
`differential input channel with a fixed polarity assignment, it does not require addressing.
`The common input line (COM) on the ADC08138 can be used as a pseudo-differential input. In this mode the
`voltage on this pin is treated as the “−” input for any of the other input channels. This voltage does not have to be
`analog ground; it can be any reference potential which is common to all of the inputs. This feature is most useful
`in single-supply applications where the analog circuity may be biased up to a potential other than ground and the
`output signals are all referred to this potential.
`
`Table 1. Multiplexer/Package Options
`Number of Analog Channels
`Number of
`Single-Ended
`Differential
`Package Pins
`1
`1
`8
`4
`2
`14
`8
`4
`20
`
`Part
`Number
`ADC08131
`ADC08134
`ADC08138
`
`Table 2. MUX Addressing: ADC08138
`
`START
`
`Single-Ended MUX Mode
`MUX Address
`SGL/
`ODD/
`DIF
`SIGN
`1
`0
`1
`0
`1
`0
`1
`0
`1
`1
`1
`1
`1
`1
`1
`1
`
`1
`1
`1
`1
`1
`1
`1
`1
`
`0
`
`+
`
`2
`
`+
`
`1
`
`+
`
`SELECT
`1
`0
`0
`0
`0
`1
`1
`0
`1
`1
`0
`0
`0
`1
`1
`0
`1
`1
`
`Analog Single-Ended Channel #
`3
`4
`5
`6
`
`7
`
`COM
`
`+
`
`+
`
`+
`
`+
`
`+
`
`−
`−
`−
`−
`−
`−
`−
`−
`
`14
`
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`
`Copyright © 1999–2013, Texas Instruments Incorporated
`
`Product Folder Links: ADC08131 ADC08134 ADC08138
`
`Curt - Exhibit 1019 - 14
`
`

`

`OBSOLETE
`
`ADC08131, ADC08134, ADC08138
`
`www.ti.com
`
`SNAS066D –JUNE 1999 –REVISED APRIL 2013
`
`Table 3. MUX Addressing: ADC08138
`
`START
`
`Differential MUX Mode
`MUX Address
`SGL/
`ODD/
`DIF
`SIGN
`0
`0
`0
`0
`0
`0
`0
`0
`0
`1
`0
`1
`0
`1
`0
`1
`
`1
`1
`1
`1
`1
`1
`1
`1
`
`SELECT
`1
`0
`0
`0
`0
`1
`1
`0
`1
`1
`0
`0
`0
`1
`1
`0
`1
`1
`
`0
`
`Analog Differential Channel-Pair #
`1
`2
`
`3
`
`0
`+
`
`−
`
`1
`−
`
`+
`
`2
`
`+
`
`−
`
`3
`
`−
`
`+
`
`4
`
`+
`
`−
`
`5
`
`−
`
`+
`
`6
`
`+
`
`−
`
`7
`
`−
`
`+
`
`Table 4. MUX Addressing: ADC08134(1)
`Single-Ended MUX Mode
`MUX Address
`SGL/
`ODD/
`DIF
`SIGN
`1
`0
`1
`0
`1
`1
`1
`1
`
`Channel #
`1
`2
`
`+
`
`+
`
`0
`
`+
`
`SELECT
`1
`0
`1
`0
`1
`
`START
`
`1
`1
`1
`1
`
`3
`
`+
`
`3
`
`−
`
`+
`
`(1) COM is internally tied to AGND
`
`START
`
`Differential MUX Mode
`MUX Address
`SGL/
`ODD/
`DIF
`SIGN
`0
`0
`0
`0
`0
`1
`0
`1
`
`1
`1
`1
`1
`
`SELECT
`1
`0
`1
`0
`1
`
`0
`
`+
`
`−
`
`Channel #
`1
`2
`
`−
`
`+
`
`+
`
`−
`
`Since the input configuration is under software control, it can be modified as required before each conversion. A
`channel can be treated as a single-ended, ground referenced input
`for one conversion;
`then it can be
`reconfigured as part of a differential channel for another conversion. Figure 24 illustrates the input flexibility which
`can be achieved.
`The analog input voltages for each channel can range from 50 mV below ground to 50 mV above VCC (typically
`5V) without degrading conversion accuracy.
`
`Copyright © 1999–2013, Texas Instruments Incorporated
`
`Submit Documentation Feedback
`
`15
`
`Product Folder Links: ADC08131 ADC08134 ADC08138
`
`Curt - Exhibit 1019 - 15
`
`

`

`ADC08131, ADC08134, ADC08138
`
`OBSOLETE
`
`SNAS066D –JUNE 1999 –REVISED APRIL 2013
`
`www.ti.com
`
`THE DIGITAL INTERFACE
`A most important characteristic of these converters is their serial data link with the controlling processor. Using a
`serial communication format offers two very significant system improvements; it allows many functions to be
`included in a small package and it can eliminate the transmission of low level analog signals by locating the
`converter right at the analog sensor; transmitting highly noise immune digital data back to the host processor.
`To understand the operation of these converters it is best to refer to the Timing Diagrams and ADC08138
`Functional Block Diagram and to follow a complete conversion sequence. For clarity a separate timing diagram is
`shown for each device.
`1. A conversion is initiated by pulling the CS (chip select) line low. This line must be held low for the entire
`conversion. The converter is now waiting for a start bit and its MUX assignment word.
`2. On each rising edge of the clock the status of the data in (DI) line is clocked into the MUX address shift
`register. The start bit is the first logic “1” that appears on this line (all leading zeros are ignored). Following
`the start bit the converter expects the next 2 to 4 bits to be the MUX assignment word.
`3. When the start bit has been shifted into the start location of the MUX register, the input channel has been
`assigned and a conversion is about to begin. An interval of ½ clock period is automatically inserted to allow
`for sampling the analog input. The SARS line goes high at the end of this time to signal that a conversion is
`now in progress and the DI line is disabled (it no longer accepts data).
`4. The data out (DO) line now comes out of TRI-STATE and provides a leading zero.
`5. During the conversion the output of the SAR comparator indicates whether the analog input is greater than
`(high) or less than (low) a series of successive voltages generated internally from a ratioed capacitor array
`(first 5 bits) and a resistor ladder (last 3 bits). After each comparison the comparator's output is shipped to
`the DO line on the falling edge of CLK. This data is the result of the conversion being shifted out (with the
`MSB first) and can be read by the processor immediately.
`6. After 8 clock periods the conversion is completed. The SARS line returns low to indicate this ½ clock cycle
`later.
`7. The stored data in the successive approximation register is loaded into an internal shift register. If the
`programmer prefers the data can be provided in an LSB first format [this makes use of the shift enable (SE)
`control line]. On the ADC08138 the SE line is brought out and if held high the value of the LSB remains valid
`on the DO line. When SE is forced low the data is clocked out LSB first. On devices which do not include the
`SE control line, the data, LSB first, is automatically shifted out the DO line after the MSB first data stream.
`The DO line then goes low and stays low until CS is returned high. The ADC08131 is an exception in that its
`data is only output in MSB first format.
`8. All internal registers are cleared when the CS line is high and the tSELECT requirement is met. See Figure 18.
`If another conversion is desired CS must make a high to low transition followed by address information.
`
`16
`
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`
`Copyright © 1999–2013, Texas Instruments Incorporated
`
`Product Folder Links: ADC08131 ADC08134 ADC08138
`
`Curt - Exhibit 1019 - 16
`
`

`

`OBSOLETE
`
`ADC08131, ADC08134, ADC08138
`
`www.ti.com
`
`SNAS066D –JUNE 1999 –REVISED APRIL 2013
`
`The DI and DO lines can be tied together and controlled through a bidirectional processor I/O bit with one wire.
`This is possible because the DI input is only “looked-at” during the MUX addressing interval while the DO line is
`still in a high impedance state.
`8 Single-Ended
`
`4 Differential
`
`8 Psuedo-Differential
`
`Mixed Mode
`
`Figure 24. Analog Input Multiplexer Options for the ADC08138
`
`REFERENCE CONSIDERATIONS
`The VREFIN pin on these converters is the top of a resistor divider string and capacitor array used for the
`successive approximation conversion. The voltage applied to this reference input defines the voltage span of the
`analog input (the difference between VIN(MAX) and VIN(MIN) over which the 256 possible output codes apply). The
`reference source must be capable of driving the reference input resistance, which can be as low as 1.3 kΩ.
`For absolute accuracy, where the analog input varies between specific voltage limits, the reference input must be
`biased with a stable voltage source. The ADC08134 and the ADC08138 provide the output of a 2.5V band-gap
`reference at VREFOUT. This voltage does not vary appreciably with temperature, supply voltage, or load current
`(see Reference Timing under Electrical Characteristics) and can be tied directly to VREFIN for an analog input
`span of 0V to 2.5V. This output can also be used to bias external circuits and can therefore be used as the
`reference in ratiometric applications. Bypassing VREFOUT with a 100 µF capacitor is recommended.
`For the ADC08131, the output of the on-board reference is internally tied to the reference input. Consequently,
`the analog input span for this device is set at 0V to 2.5V. The pin VREFC is provided for bypassing purposes and
`biasing external circuits as suggested above.
`The maximum value of the reference is limited to the VCC supply voltage. The minimum value, however, can be
`quite small (see Typical Converter Performance Characteristics) to allow direct conversions of transducer outputs
`providing less than a 5V output span. Particular care must be taken with regard to noise pickup, circuit layout and
`system error voltage sources when operating with a reduced span due to the increased sensitivity of the
`converter (1 LSB equals VREF/256).
`
`Copyright © 1999–2013, Texas Instruments Incorporated
`
`Submit Documentation Feedback
`
`17
`
`Product Folder Links: ADC08131 ADC08134 ADC08138
`
`Curt - Exhibit 1019 - 17
`
`

`

`OBSOLETE
`
`ADC08131, ADC08134, ADC08138
`
`SNAS066D –JUNE 1999 –REVISED APRIL 2013
`
`Reference Examples
`
`www.ti.com
`
`Figure 25. Ratiometric
`
`Figure 26. Absolute
`
`THE ANALOG INPUTS
`The most important feature of these converters is that they can be located right at the analog signal source and
`through just a few wires can communicate with a controlling processor with a highly noise immune serial bit
`stream. This in itself greatly minimizes circuitry to maintain analog signal accuracy which otherwise is most
`susceptible to noise pickup. However, a few words are in order with regard to the analog inputs should the input
`be noisy to begin with or possibly riding on a large common-mode voltage.
`The differential
`input of these converters actually reduces the effects of common-mode input noise, a signal
`common to both selected “+” and “−” inputs for a conversion (60 Hz is most typical). The time interval between
`sampling the “+” input and then the “−” input is ½ of a clock period. The change in the common-mode voltage
`during this short time interval can cause conversion errors. For a sinusoidal common-mode signal this error is:
`
`where
`fCM is the frequency of the common-mode signal
`•
`• VPEAK is its peak voltage value
`(1)
`•
`fCLK is the A/D clock frequency
`For a 60Hz common-mode signal to generate a ¼ LSB error (≈5 mV) with the converter running at 250kHz, its
`peak value would have to be 6.63V which would be larger than allowed as it exceeds the maximum analog input
`limits.
`Source resistance limitation is important with regard to the DC leakage currents of the input multiplexer. While
`operating near or at maximum speed bypass capacitors should not be used if the source resistance is greater
`than 1kΩ. The worst-case leakage current of ±1µA over temperature will create a 1mV input error with a 1kΩ
`source resistance. An op amp RC active low pass filter can provide both impedance buffering and noise filtering
`should a high impedance signal source be required.
`
`18
`
`Submit Documentation Feedback
`
`Copyright © 1999–2013, Texas Instruments Incorporated
`
`Product Folder Links: ADC08131 ADC08134 ADC08138
`
`Curt - Exhibit 1019 - 18
`
`

`

`www.ti.com
`
`OPTIONAL ADJUSTMENTS
`
`OBSOLETE
`
`ADC08131, ADC08134, ADC08138
`
`SNAS066D –JUNE 1999 –REVISED APRIL 2013
`
`Zero Error
`The zero of the A/D does not require adjustment. If the minimum analog input voltage value, VIN(MIN), is not
`ground a zero offset can be done. The converter can be made to output 0000 0000 digital code for this minimum
`input voltage by biasing any VIN (−) input at this VIN(MIN) value. This utilizes the differential mode operation of the
`A/D.
`The zero error of the A/D converter relates to the location of the first riser of the transfer function and can be
`measured by grounding the VIN (−) input and applying a small magnitude positive voltage to the VIN (+) input.
`Zero error is the difference between the actual DC input voltage which is necessary to just cause an output
`digital code transition from 0000 0000 to 0000 0001 and the ideal ½ LSB value (½ LSB = 9.8mV for VREF =
`5.000VDC).
`
`Full Scale
`A full-scale adjustment can be made by applying a differential input voltage which is 1½ LSB down from the
`desired analog full-scale voltage range and then adjusting the magnitude of the VREFIN input for a digital output
`code which is just changing from 1111 1110 to 1111 1111 (See Figure 31). This is possible only with the
`ADC08134 and ADC08138. (The reference is internally connected to VREFIN of the ADC08131).
`
`Adjusting for an Arbitrary Analog Input
`Voltage Range
`If the analog zero voltage of the A/D is shifted away from ground (for example, to accommodate an analog input
`signal which does not go to ground), this new zero reference should be properly adjusted first. A VIN (+) voltage
`which equals this desired zero reference plus ½ LSB (where the LSB is calculated for the desired analog span,
`using 1 LSB = analog span/256) is applied to selected “+” input and the zero reference voltage at
`the
`corresponding “−” input should then be adjusted to just obtain the 00HEX to 01HEX code transition.
`The full-scale adjustment should be made [with the proper VIN (−) voltage applied] by forcing a voltage to the VIN
`(+) input which is given by:
`
`where
`• VMAX = the high end of the analog input range
`• VMIN = the low end (the offset zero) of the analog range.
`(Both are ground referenced.)
`The VREFIN (or VCC) voltage is then adjusted to provide a c