UNITED STATES PATENT AND TRADEMARK OFFICE
`__________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`__________________
`
`CREE, INC.,
`
`Petitioner
`
`v.
`
`DOCUMENT SECURITY SYSTEMS, INC.,
`Patent Owner
`
`Patent No. 7,256,486
`IPR2019-00506
`
`DECLARATION OF JAMES R. SHEALY, Ph.D IN SUPPORT OF
`PETITION FOR INTER PARTES REVIEW OF U.S. PATENT NO. 7,256,486
`
`Cree Exhibit 1003
`Page 1
`
`
`__________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`__________________
`
`CREE, INC.,
`
`Petitioner
`
`v.
`
`DOCUMENT SECURITY SYSTEMS, INC.,
`Patent Owner
`
`Patent No. 7,256,486
`IPR2019-00506
`
`DECLARATION OF JAMES R. SHEALY, Ph.D IN SUPPORT OF
`PETITION FOR INTER PARTES REVIEW OF U.S. PATENT NO. 7,256,486
`
`Cree Exhibit 1003
`Page 1
`
`
`
`I.
`
`INTRODUCTION
`1.
`2.
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`My name is James Richard Shealy, Ph.D.
`I make this declaration in support of Petitioner Cree, Inc.’s
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`(“Petitioner”) petition for inter partes review of U.S. Patent No. 7,256,486 (“the
`
`’486 patent,” Exhibit 1001), IPR2019-00506.
`
`3.
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`I am over 21 years of age and otherwise competent to make this
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`declaration.
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`4.
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`Although I am being compensated for my time in preparing this
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`declaration, the opinions herein are my own, and I have no stake in the outcome of
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`the inter partes review proceeding.
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`5.
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`I am not an employee of Petitioner or any affiliate or subsidiary
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`thereof.
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`6.
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`This declaration summarizes the opinions I have formed to date. I
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`reserve the right to modify my opinions, if necessary, based on further review and
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`analysis of information that I receive subsequent to the filing of this report,
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`including in response to positions that parties to the inter partes review proceeding,
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`or their experts, may take that I have not yet seen.
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`Cree Exhibit 1003
`Page 2
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`
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`II. MY EXPERIENCE AND QUALIFICATIONS
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`7.
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`I have been involved in the science and engineering of light emitting
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`diodes for almost 40 years, as detailed in my curriculum vitae (attached as
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`Appendix A).
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`8.
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`I received a B.S. degree from North Carolina State in 1978, an M.S.
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`from Rensselaer Polytechnic in 1980, and a Ph.D. from Cornell in 1983.
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`9.
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`I joined the Cornell faculty in 1987 and am currently a professor in
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`the School of Electrical and Computer Engineering.
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`10.
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`I have been deeply involved in the research and design of LEDs over
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`the course of my career. In 1978, I joined the technical staff of General Electric’s
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`Corporate Research and Development Center under an Edison Fellowship. While
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`there, among other work, I developed GaAs epitaxial materials for high voltage
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`electronics. I also researched device fabrication by organometallic vapor phase
`
`epitaxy (“OMVPE”).
`
`11.
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`In 1980, I transferred to General Electric’s Advanced Electronics
`
`Laboratory, where I developed materials and processes for the fabrication of
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`AlGaAs LEDs as well as developing an OMVPE reactor and related processes for
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`the fabrication of AlGaAs quantum well laser diodes. They were the highest
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`power, lowest threshold devices at the time. The AlGaAs LEDs were developed in
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`my group: from materials to device fabrication to a variety of packaging solutions.
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`Cree Exhibit 1003
`Page 3
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`The packages included lead frame packages, hermetically sealed metal and ceramic
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`packages, and packages which combined the LED with a silicon photo transistor
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`(commonly referred to as an opto-coupler). These packages included wire bonds
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`to pads on the LED and on the package, silver epoxy die mounts, eutectic preform
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`die mounts, LED passivation, reflectors, and focusing lenses integrated into the
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`package assembly. In 1985, I was designated Principal Staff Scientist at General
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`Electric in recognition of my research contributions.
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`12.
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`For a portion of my time at General Electric, I was also concurrently
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`working at Cornell. In 1984, my group at Cornell developed the first single
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`quantum well red laser by OMVPE. I then joined the Cornell faculty in 1987 and
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`have continued my research in OMVPE, particularly as it relates to LEDs, laser
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`diodes, and high frequency transistors. During this time, high performance
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`AlGaInP red laser diodes and LEDs were realized. The red LEDs were packaged
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`on metal submounts with an integral reflector and focusing lens to couple the LED
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`emission into plastic optical fiber bundles. I have also researched GaN and related
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`materials for both LEDs and high power transistors.
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`13.
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`In 1997, I was named the Director of Cornell’s Optoelectronics
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`Technology Center. In 1998, I was promoted to full professor at Cornell. I have
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`published in excess of 100 articles, and I am the inventor of over 15 patents, many
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`of which deal with GaN-based materials and devices. Many of the GaN-based
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`Cree Exhibit 1003
`Page 4
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`
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`LEDs on which I worked were realized on defect-free GaN pyramidal p-n
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`junctions with quantum well active regions. I have remained current in the field,
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`as evidenced by my publications listed in my curriculum vitae.
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`14.
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`I have also previously testified in a number of patent infringement
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`proceedings, including relating to LEDs, including materials growth, device
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`fabrication, and their packaging.
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`15.
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`I have used my education and experience researching, publishing and
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`working in the LED field, and my understanding of the knowledge, creativity, and
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`experience of a person having ordinary skill in the art, in forming the opinions
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`expressed in this declaration, as well as any other materials discussed herein.
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`III. MATERIALS CONSIDERED
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`16.
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`In forming my opinions, I read and considered the ’486 patent and its
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`prosecution history, the exhibits listed in the Exhibit List filed with the petition for
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`inter partes review of the ’486 patent, as well as any other material referenced
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`herein.
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`17.
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`For any future testimony I may give in this matter, I may use some or
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`all of the documents and information cited to, referred to, and identified in this
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`declaration, as well as any additional materials that are entered into evidence in
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`this matter.
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`Cree Exhibit 1003
`Page 5
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`
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`IV. LEGAL PRINCIPLES OF OBVIOUSNESS
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`18.
`
`I have been informed and I understand that a patent claim is
`
`unpatentable and invalid if the subject matter of the claim as a whole would have
`
`been obvious to a POSITA in the field of the patent as of the time of the invention
`
`at issue. I have been informed and understand that the following factors must be
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`evaluated to determine whether the claimed subject matter is obvious: (i) the scope
`
`and content of the prior art; (ii) the difference or differences, if any, between each
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`claim of the patent and the prior art; (iii) the level of ordinary skill in the art at the
`
`time the patent was filed; and (iv) any objective indicia of non-obviousness.
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`19.
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`I have been informed and I understand that the objective indicia of
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`non-obviousness (or “secondary considerations”) that should be considered
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`include, for example, the following: (i) commercial success; (ii) long-felt but
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`unresolved needs; (iii) copying of the invention by others in the field; (iv) initial
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`expressions of disbelief by experts in the field; (v) failure of others to solve the
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`problem that the inventor solved; and (vi) unexpected results. I have been
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`informed and understand that evidence of these objective indicia must be
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`commensurate in scope with the claimed subject matter. I am not aware of any
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`objective indicia of non-obviousness relevant to the claims of the ’486 patent.
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`20.
`
`In determining whether the subject matter as a whole would have been
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`obvious at the time that the invention was made to a person having ordinary skill in
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`Cree Exhibit 1003
`Page 6
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`
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`the art, I have been informed of and understand certain principles regarding the
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`combination of elements of the prior art. A combination of familiar elements
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`according to known methods is likely to be obvious when it yields predictable
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`results. Also, if a person of ordinary skill in the art can implement a predictable
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`variation in a prior art device, and would see the benefit from doing so, such a
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`variation would be obvious. In particular, when there is pressure to solve a
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`problem and there are a finite number of identifiable, predictable solutions, it
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`would be reasonable for a person of ordinary skill to pursue those options that fall
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`within his or her technical grasp. If such a process leads to the claimed invention,
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`then the latter is not an innovation, but more the result of ordinary skill and
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`common sense.
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`21.
`
`I have also been informed and understand that a teaching, suggestion
`
`and motivation is a useful guide in establishing a rationale for combining elements
`
`of the prior art. The test poses the question as to whether there is an explicit
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`teaching, suggestion, or motivation in the prior art to combine prior art elements in
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`a way that realizes the claimed invention. Though useful to the obviousness
`
`inquiry, I understand that this test should not be treated as a rigid rule. It is not
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`necessary to seek out precise teachings; it is permissible to consider the inferences
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`and creative steps that a person of ordinary skill in the art (who is considered to
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`have an ordinary level of creativity and is not an “automaton”) would employ.
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`Cree Exhibit 1003
`Page 7
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`
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`V.
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`LEVEL OF ORDINARY SKILL IN THE ART
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`22.
`
`I have been informed and understand that the disclosure of patents and
`
`prior art references are to be viewed from the perspective of a person having
`
`ordinary skill in the art at the time of the alleged invention. I have been told I may
`
`use the short hand “POSITA” to describe this person. I have provided my opinions
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`from this perspective, which is as of June 27, 2003, the filing date of the
`
`application (U.S. Patent Application Serial No. 10/608,605) that led to the ’486
`
`patent.
`
`23.
`
`I have been informed and understand that prior art references can
`
`provide evidence of the level of ordinary skill in the art, and that factors that may
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`be considered in determining this level of skill can include the educational level of
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`the inventors and active workers in the field, the types of problems encountered in
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`the art, the prior art solutions to those problems, the rapidity with which
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`innovations are made, and the sophistication of the technology.
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`24.
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`It is my opinion that those of ordinary skill in the art during the
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`relevant period would have had at least a B.S. in mechanical or electrical
`
`engineering or a related field, and four years’ experience designing LED packages.
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`However, I note that this description is approximate, and a higher level of
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`education or skill might make up for less experience, and additional experience
`
`could make up for a lower education level, for example, an M.S. in any of the
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`Cree Exhibit 1003
`Page 8
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`
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`above fields and two years’ experience would qualify as a person of ordinary skill,
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`in my opinion.
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`VI. SUMMARY OF THE ’486 PATENT
`25. The ’486 patent is generally directed to a substrate packaging
`
`assembly for an LED. Ex. 1001 at Abstract, 2:9-10, 2:33-43. I use the term
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`“LED” in this declaration as short hand for light emitting diode die. The
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`specification discloses that the substrate packaging assembly includes a planar
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`substrate with a mounting pad and a bonding pad on its topside, and two
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`connecting pads on its bottom side. Ex. 1001 at Abstract, 2:33-43. The mounting
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`pad provides a surface to which the bottom of an LED is mechanically and
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`electrically attached. Ex. 1001 at Abstract, 2:33-43. The bonding pad provides a
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`surface to which a bonding wire (the other side of which is attached to the topside
`
`electrode [anode] of the LED) is mechanically and electrically attached. Ex. 1001
`
`at Abstract, 2:33-43. Electrically conductive interconnecting elements run through
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`the substrate to electrically connect the mounting and bonding pads (on the top of
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`the substrate) with the two connecting pads (on the bottom of the substrate). Ex.
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`1001 at Abstract, 2:33-43.
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`26. Figures 1A and 1B, which depict the substrate packaging assembly
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`(i.e., the purported invention without an LED mounted on the mounting pad), are
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`annotated below (substrate 110 colored red; mounting and bonding pads 130, 132
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`Cree Exhibit 1003
`Page 9
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`
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`colored green; connecting pads 140, 142 colored orange (not visible in Fig. 1A);
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`interconnecting elements 120, 122 colored purple).1
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`27.
`
`The ’486 patent discloses that an LED is mounted on the substrate
`
`packaging assembly, and that the LED has metallized top and bottom major
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`surfaces, and that these surfaces comprise an anode and a cathode, respectively.
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`Ex. 1001 at 5:43-62. The ’486 patent itself admits that such an LED was well
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`known in the prior art. Ex. 1001 at 1:20-23, 49-52.
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`28.
`
`In Figure 2A, below, substrate 110 is colored red; mounting and
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`bonding pads 130, 132 are colored green; LED 250 is colored blue; bonding wire
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`254 is colored gold; interconnecting elements 120, 122 are colored purple; and the
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`connecting pads are not shown. I note that the ’486 patent specification uses the
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`broader term “semiconductor die” (which could encompass more than LEDs) but
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`1 Unless otherwise noted, all coloring and descriptions have been added to the
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`figures.
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`Cree Exhibit 1003
`Page 10
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`
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`the claims recite only one type of semiconductor die—“a light emitting diode
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`(LED).”
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`29.
`
`The substrate, mounting pad, LED, first connecting pad, and first
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`interconnecting element are claimed in claim 1. Claim 2 adds the bonding pad,
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`bonding wire, second connecting pad, and second interconnecting element. And,
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`claim 3 specifies that the top and bottom of the LED comprise first and second
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`electrodes (but, as discussed below, this recitation would, in my opinion, have been
`
`implicit in the structure described in claim 2).
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`30.
`
`The ’486 patent discloses three additional details about the first
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`interconnecting element, which are claimed in claims 4, 5, and 6, respectively: (i)
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`that it should provide a low-resistance electrical connection, while being able to
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`withstand an operating temperature when the LED is mounted on the mounting
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`Cree Exhibit 1003
`Page 11
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`
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`pad; (ii) that tungsten should be one of the materials that is used to provide this
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`result; and (iii) that it should comprise a slug of electrically conductive material
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`with a diameter selected such that the slug may be press-fit into a through hole
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`located in the substrate. Ex. 1001 at 4:29-45, claims 4-6.
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`VII. CLAIM CONSTRUCTION
`I have been informed and understand that claim construction is the
`31.
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`process of determining the meaning of words (or terms) within a patent claim. I
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`have also been informed and understand that the proper construction of a claim
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`term is the meaning that a POSITA would have given to that term.
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`32.
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`I have been informed and understand that claims in inter partes
`
`review proceedings are to be given their broadest reasonable interpretation in light
`
`of the specification, so long as they are not set to expire during the course of the
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`proceedings. I have been told to apply, and have applied, the broadest reasonable
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`interpretation in performing my analysis in this declaration.
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`33.
`
`In comparing the claims of the ’486 patent to the prior art, I have
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`carefully considered the ’486 patent and its file history based upon my experience
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`and knowledge in the relevant filed. In my opinion, the broadest reasonable
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`interpretation of the claim terms of the ’486 patent is generally consistent with the
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`terms’ ordinary and customary meaning, as a person of ordinary skill would have
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`Cree Exhibit 1003
`Page 12
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`
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`understood them. That said, for purposes of this proceeding, I have applied the
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`following two particular constructions when analyzing the prior art and the claims.
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`34.
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`The term “major surface” is found in claims 1, 2, and 3. It is my
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`opinion that a POSITA would have understood “major surface” to refer, as a
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`matter of geometric orientation, to “a face that is greater in size than the other faces
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`of the element being described.” For example, with respect to LED 250, the ’486
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`patent describes that it has two opposed major surfaces, indicated by red and
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`purple arrows below, respectively. Ex. 1001 at 5:7-22, 8:23-26, Fig. 2B.
`
`top major surface
`of LED 250
`
`bottom major
`surface of LED 250
`
`35.
`
`In my opinion, a POSITA would have understood the phrase
`
`“metallized … major surface” as recited in claims 1, 2, and 3, to mean “a major
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`surface having metal on at least a portion thereof.”
`
`36.
`
`The phrase “metallized … surface” is not expressly defined in either
`
`the ’486 specification or its prosecution history. However, in my opinion, a
`
`Cree Exhibit 1003
`Page 13
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`
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`POSITA would have found that the use of the phrase in the specification supports
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`the above proposed construction, for example:
`
`•
`
`“A metallization layer of aluminum located on the bottom
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`surface of the semiconductor die is bonded to a conductive
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`surface that forms part of the lead frame to attach and
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`electrically connect the die to the lead frame.” Ex. 1001 at
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`1:19-23 (emphasis added).
`
`•
`
`“In the example shown, semiconductor die 250 embodies a
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`light-emitting diode and has anode and cathode electrodes (not
`
`shown) covering at least parts of its opposed major surfaces.”
`
`Ex. 1001 at 5:7-10, 8:23-26 (emphasis added).
`
`•
`
`•
`
`“Semiconductor die 250 is mounted on packaging device 100
`
`with the metallization on its bottom major surface attached to
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`mounting pad 130.” Ex. 1001 at 5:10-12 (emphasis added).
`
`“The metallization on the bottom major surface of the
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`semiconductor die 250 typically constitutes the cathode
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`electrode of the light-emitting diode.” Ex. 1001 at 5:18-22
`
`(emphasis added); see also 8:26-31.
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`Cree Exhibit 1003
`Page 14
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`
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`•
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`“The top major surface of semiconductor die 250 typically
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`includes a bonding pad that is typically part of or connected to
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`the anode electrode of the light-emitting diode.” Ex. 1001 at
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`8:34-37 (emphasis added).
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`37.
`
`In my opinion, this interpretation is further supported, for example, by
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`various dictionary definitions including:
`
`• Metallization means, in relevant part, “[a] film pattern (single or
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`multilayer) of conductive material deposited onto a substrate to
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`interconnect electronic components, or the metal film on the
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`bonding area of a substrate that becomes part of the bond and
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`performs both electrical and mechanical functions.” Ex. 1013
`
`Modern Dictionary of Electronics, at 467 (7th ed. 1999).
`
`•
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`“[M]etallize … to coat, treat, or combine with metal.” Ex. 1014,
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`Merriam Webster’s Collegiate Dictionary, at 730 (10th ed.).
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`38.
`
`In the context of the ’486 patent, therefore, in my opinion, a POSITA
`
`would have understood the phrase “metallized … major surface” to require that
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`only a portion of the major surface be “metallized”—i.e., to have metal, such as a
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`bonding pad or an electrode, thereon.
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`Cree Exhibit 1003
`Page 15
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`
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`VIII. SUMMARY OF SELECT PRIOR ART AND STATE OF THE ART
`39. All the components of the ’486 patent claims were known in the art,
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`as detailed below.2
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`40. As discussed below, LEDs of numerous configurations were well
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`known; and, the concept of mounting these LEDs on various kinds of substrate
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`packaging assemblies was also well known. It would not be significant or
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`unexpected to one of skill in the art to alter the arrangement of these components
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`or to substitute various LEDs onto various substrate packaging assemblies.
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`41. For these reasons, it is my opinion that, as a general matter, all of the
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`elements of the claims of the ’486 patent were well known in the art and that there
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`is nothing unexpected in the combination of these elements in the ’486 patent. As
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`evidence to support this opinion, I discuss generally below the state of the art (i.e.,
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`prior to the filing date of the claims of the ’486 patent) with respect to several of
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`the elements of the claims. My opinion then addresses the claimed elements more
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`specifically in light of certain references.
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`2 I have been told that the references discussed herein qualify as prior art under the
`
`law.
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`Cree Exhibit 1003
`Page 16
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`
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`The “Substrate Packaging Assembly” Prior Art
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`42.
`
`The following references disclose substrate packaging assemblies that
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`are structurally identical to the one claimed in the ’486 patent. I note that the prior
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`art figures below are annotated with the same color scheme as the above figures of
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`the ’486 patent to show their similarities.
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`1.
`
`Nakajima
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`43. Nakajima discloses that its “invention relates to a package for housing
`
`light emitting elements for accommodating a light emitting element such as a light
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`emitting diode….” Ex. 1004, ¶0001. Nakajima’s touts that its invention “cause[s]
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`the luminous efficacy of the light emitting device to be extremely high.” Ex. 1004,
`
`¶0007. Nakajima explains:
`
`[T]he ceramic base 1 is formed by the deposition of a metallized
`wiring conductor 4a leading from the mounting unit 1a thereof to the
`bottom face and a metallized wiring conductor 4b leading from the
`periphery of the mounting unit 1a to the bottom face. The metallized
`wiring conductors 4a and 4b comprise a metallized metal powder such
`as tungsten, molybdenum, copper, or silver and function as conductive
`paths for electrically connecting the light emitting element 3
`accommodated in the package to the outside. In addition, the light
`emitting element 3, such as a light emitting diode or the like, is fixed
`to a site on the mounting unit 1a of the metallized wiring conductor 4a
`with a conductive bonding material, such as a gold-silicon alloy, a
`silver-epoxy resin, or the like….
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`Cree Exhibit 1003
`Page 17
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`
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`Ex. 1004, ¶0014.
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`44.
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`Figure 1 of Nakajima is annotated below (substrate colored red;
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`mounting and bonding pads colored green; LED colored blue; bonding wire
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`colored gold; interconnecting elements colored purple; connecting pads colored
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`orange).
`
`2.
`
`Rohm
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`45. Rohm discloses a “surface mount type semiconductor light emitting
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`device.” Ex. 1005, ¶0013. Rohm touts that the effect of its invention is that “[t]he
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`packaging density of the surface mount type light emitting devices on the circuit
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`board can be increased more than that of a conventional device.” Ex. 1005
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`[Effect]. Rohm’s device includes a rectangular “substrate 12,” (Ex. 1005, ¶0017,
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`Cree Exhibit 1003
`Page 18
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`
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`Fig. 1(A)), and a “die bonding electrode 18 that is bonded with the LED chip 30.”
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`Ex. 1005, ¶0023, Fig. 1(A). Rohm explains that “LED chip 30 is electrically
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`connected with the bottom electrode and the die bonding electrode 18.” Ex. 1005,
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`¶0016, Fig. 1(A). Rohm discloses an “electrode for first surface mounting 22” and
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`a “first connect electrode 26” and explains that “die bonding electrode 18 and the
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`electrode for first surface mounting 22 are electrically connected by the first
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`connect electrode 26 formed inside the first through hole 14.” Ex. 1005, ¶0019,
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`Fig. 1(A). Rohm also discloses a “wire bonding electrode 20” and explains that
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`“second connect electrode 28 is electrically connected with the wire bonding
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`electrode 20 and the electrode 24 for the second surface mounting.” Ex. 1005,
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`¶¶0014-15, Fig. 1(A). Rohm’s “surface electrode 30a of the LED chip 30 and a
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`wire bonding electrode 20 are wire bonded by wire 32, such as a gold wire, etc.”
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`Ex. 1005, ¶0016, Fig. 1(A). Rohm discloses an “electrode 24 for the second
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`surface mounting” and a “second connect electrode 28” and explains that “second
`
`connect electrode 28 is electrically connected with the wire bonding electrode 20
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`and the electrode 24 for the second surface mounting.” Ex. 1005, ¶0015, Fig.
`
`1(A). Rohm’s “wire bonding electrode 20 and the electrode for the second surface
`
`mounting 24 are electrically connected by the second connect electrode 28 formed
`
`inside the second through hole 16.” Ex. 1005, ¶0021, Fig. 1(A).
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`Cree Exhibit 1003
`Page 19
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`46.
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`Figure 1A of Rohm is annotated below (substrate colored red;
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`mounting and bonding pads colored green; LED die colored blue; bonding wire
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`colored gold; interconnecting elements colored purple; connecting pads colored
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`orange).
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`3. Matsushita
`
`47. Matsushita’s “invention is related to an optical semiconductor device,
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`for example, a surface mount type chip LED (light-emitting diode)….” Ex. 1006,
`
`¶¶0001. Matsushita touts that the effect of its invention is that “the bonding level
`
`of resin package is strengthened, and disconnection of the bonding wire can be
`
`prevented.” Ex. 1006, ¶0006. Matsushita discloses a “substrate 1” and a
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`“semiconductor light emitting element 4” that “is conductively mounted on
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`electrode 3.” Ex. 1006, Abstract, ¶¶0012-13, Fig. 2. Matsushita explains that
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`“electrodes 2 and 3 are formed on these through holes 1a and 1b from the surface
`
`side to the back side of substrate 1.” Ex. 1006, ¶00012, Fig. 2. Matsushita’s
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`Cree Exhibit 1003
`Page 20
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`
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`“electrode 4a on the top side of the semiconductor light emitting element 4 and the
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`other electrode 2 are bonded by a wire 6.” Ex. 1006, ¶0013, Fig. 2.
`
`48.
`
`Figure 2 of Matsushita is annotated below (substrate colored red;
`
`mounting and bonding pads colored green; LED die colored blue; bonding wire
`
`colored gold; interconnecting elements colored purple; connecting pads colored
`
`orange).
`
`The “LED” Prior Art
`
`49.
`
`The following references disclose LEDs that have metallized top and
`
`bottom major surfaces, such as the LED claimed in the ’486 patent.
`
`4. Weeks
`
`50. Weeks discloses an LED with metal contacts located on its top and
`
`bottom major surfaces, each comprising one of an anode and a cathode. Ex. 1007
`
`at 3:39-62, 4:11-22, 5:49-64, 6:7-64, 9:32-52. Weeks discloses that “[a] topside
`
`Cree Exhibit 1003
`Page 21
`
`
`
`electrical contact 16 (on a topside 18 of the device) and a backside electrical
`
`contact 20 (on a backside of the device 22) are provided for connection to an
`
`external power supply that powers the device.” Ex. 1007 at 3:48-51. Weeks
`
`explains that “[t]opside contact 16 is formed of a p-type metal and backside contact
`
`20 is formed of an n-type metal.” Ex. 1007 at 9:45-46. Weeks further explains
`
`that “[b]ackside contact 20 and topside contact 16 may be deposited using known
`
`techniques suitable for depositing conducting materials such as metals,” (Ex. 1007
`
`at 8:43-45), and that “the phrase ‘electrical contact’ or ‘contact’ refers to any
`
`conducting structure on the semiconductor device that may be effectively
`
`contacted by a power source including electrodes, terminals, contact pads, contact
`
`areas, contact regions and the like,” (Ex. 1007 at 6:7-21). Regarding the material
`
`that comprises its contacts, Weeks states:
`
`Backside contact 20 and topside contact 16 are formed of conducting
`materials including certain metals…. For example, contacts 16, 20
`may contact n-type material or p-type material. Suitable metals for n-
`type contacts include titanium, nickel, aluminum, gold, copper, and
`alloys thereof. Suitable metals for p-type contacts include nickel, gold
`and titanium, and alloys thereof.
`
`Ex. 1007 at 6:7-21.
`
`51. Weeks touts certain advantages of its invention, including that it can
`
`be used to produce smaller packaged devices, remove thermal energy generated
`
`Cree Exhibit 1003
`Page 22
`
`
`
`during operation of the device, and enhance optoelectronic output efficiencies. Ex.
`
`1007 at 2:57-3:2.
`
`52. Weeks explains that “the term ‘topside’ refers to the upper surface of
`
`the device and the term ‘backside’ refers to the bottom surface of the device. Thus,
`
`the topside is opposite the backside of the device.” Ex. 1007 at 4:19-22. Topside
`
`contact 16 and backside contact 20 are colored light blue below in Figure 4.
`
`5.
`
`Kish
`
`53. Kish discloses an LED with metal electrodes located on its top and
`
`bottom major surfaces, each comprising one of an anode and a cathode. Kish
`
`Cree Exhibit 1003
`Page 23
`
`
`
`explains that “[e]lectrodes 142 and 144 are … formed on the upper surface of the
`
`patterned wafer 126 and the lower surface of the substrate 136.” Ex. 1008 at
`
`10:53-55, Fig. 14. Kish further explains that the use of “metallized electrodes” for
`
`applying electricity to the active region of LEDs was “standard.” Ex. 1008 at 5:19-
`
`21, 7:48-55, 9:64-66, 10:53-55, 13:30-33, Fig. 7, Fig. 12, Fig. 14. Top electrode
`
`142 and bottom electrode 144 are colored light blue below in Figure 14.
`
`6.
`
`Edmond
`
`54.
`
`Edmond discloses an LED with metal contacts located on its top and
`
`bottom major surfaces, each comprising one of an anode and a cathode. Ex. 1009
`
`at 5:9-12, 5:56-62; 7:67-8:5. Edmond refers to its anode and cathode as “ohmic
`
`contact[s]” and explains that the ohmic contacts should be made of metal, “such as
`
`Cree Exhibit 1003
`Page 24
`
`
`
`aluminum (Al), gold (Au), platinum (Pt), or nickel (Ni),” or other materials known
`
`to a POSITA to function as anode or cathode contacts. Ex. 1009 at 5:9-12, 5:56-
`
`62. Bottom ohmic contact 22 (located on conductive silicon carbide substrate 21)
`
`and top ohmic contact 30 (located on the oppositely facing surface) are colored
`
`light blue below in Figure 1. Ex. 1009 at 4:66-5:12.
`
`
`
`The “Conductive Slug” Prior Art
`
`55. The following reference discloses an electrical interconnect comprised
`
`of a conductive slug that is inserted into a through-hole using a press-fit method,
`
`such as claimed in the ’486 patent.
`
`Jochym
`
`7.
`Jochym discloses forming an electrical interconnect between PCB
`
`56.
`
`layers by “placing a conductive stake, or conductive pin, in [a] through-hole.” Ex.
`
`Cree Exhibit 1003
`Page 25
`
`
`
`1010 at Abstract, 1:54-2:4, 6:19-23. Jochym describes “using a ‘press fit’” to
`
`insert the conductive stake into a via/through-hole. Ex. 1010 at 6:19-23.
`
`57.
`
`Jochym explains that, “[i]n order to connect signal paths from one
`
`conductive layer to another conductive layer, holes (or through-holes) are drilled
`
`through a PCB and are subsequently coated, or plated, with a conductive
`
`substance,” but that this method proves problematic because as the PCB thickens,
`
`“there may be a concomitant increase in the amount of space, i.e., the diameter,
`
`required by through-holes….” Ex. 1010 at 1:22-54. Jochym solves this problem:
`
`[I]n accordance with the invention, instead of coating, or plating a
`through-hole with a conductive material to form a via—the via is
`formed by placing a conductive stake in the through-hole for
`electrically coupling foils disposed on at least two electrically
`conductive layers together. Thus, as the thickness of a PCB increases,
`the diameter of the individual through-holes stay the same and the
`amount of space taken up by the through-holes does not change. In an
`embodiment of the invention, a conductive stake is inserted into a
`through-hole of a PCB for the purpose of forming a via…. The length
`of the conductive stake is at least as long as the distance between two
`conductive layers of the PCB. A diameter of the conductive stake is
`approximately greater than, or equal to, the diameter of the through-
`hole.
`
`Ex. 1010 at 1:55-2:4, Fig. 1. Figure 1 below shows conductive stake 105 being
`
`press-fit into through-hole 125 to electrically interconnect layers of the PCB.
`
`Cree Exhibit 1003
`Page 26
`
`
`
`IX. ANALYSIS OF SPECIFIC PRIOR ART REFERENCES RELATIVE
`TO THE CLAIMS OF THE ’486 PATENT
`
`A.
`
`Nakajima, in view of Weeks, Kish, or Edmond renders obvious
`claims 1-5
`
`58.
`
`In my opinion, a POSITA would have found that Nakajima in view of
`
`Weeks, Kish, or Edmond renders obvious claims 1-5.
`
`1.
`
`Claim 1
`
`1[Preamble] “A semiconductor device, comprising:”
`
`Cree Exhibit 1003
`Page 27
`
`
`
`59.
`
`In my opinion, to the extent that the preamble is found to limit the
`
`claims, a POSITA would have found that Nakajima discloses the claimed
`
`semiconductor device because its “invention relates to a package for housing light
`
`emitting elements for accommodating a light emitting element such as a light
`
`emitting diode or the like.” Ex. 1004, ¶0001. Figure 1 depicts “a cross-sectional
`
`view showing an example of an embodiment of the package for housing light
`
`emitting elements of the present invention.” Ex. 1004, (Brief Description of the
`
`Drawings).
`
`
`
`
`
`1[a] “a substantially planar substrate having opposed major
`surfaces;”
`
`60.
`
`In my opinion, a POSITA would have found that Nakajima discloses
`
`the claimed substantially planar substrate having opposed major surfaces because it
`
`Cree Exhibit 1003
`Page 28
`
`
`
`discloses a “ceramic base 1” that is “a substantially quadrilateral flat shape.” Ex.
`
`1004, ¶0013. Nakajima’s ceramic base substrate has a first major surface (the top),
`
`and a second major surface (the bottom). Nakajima’s ceramic base 1 (which
`
`corresponds to the claimed “substantially planar subst
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