(12)
`
`United States Patent
`Kang et al.
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 7,369,815 B2
`May 6, 2008
`
`USOO7369815B2
`
`6,133,871 A * 10/2000 Krasner ................. 342,357.06
`6,151,681 A 1 1/2000 Roden et al. ............... T13,322
`6.219,564 B1 * 4/2001 Grayson et al. ..
`... 455,574
`29. R. s: t
`l - - -
`- - - 1:57:
`6,715,085 B2 * 3/2004 Foster et al. .................. 726/27
`7,089,344 B1* 8/2006 Rader et al. ...
`... 710,308
`2002fOO25839 A1
`2/2002 USui ................
`... 455,574
`2002fOO9484.0 A1* 7, 2002 Hattori et al. .............. 455,558
`2003/0.133337 A1* 7/2003 Yamada et al. ............. 365,200
`
`OnOgaK1 ......
`
`- - -
`
`wal -
`
`(54) POWER COLLAPSE FOR AWIRELESS
`TERMINAL
`
`(75) Inventors: Inyup Kang, San Diego, CA (US);
`Kyan Ethirajan, San Diego,
`
`(73) Assignee: Qualcomm Incorporated, San Diego,
`CA (US)
`
`(*) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 289 days.
`
`(21) Appl. No.: 10/786,585
`
`(22) Filed:
`(65)
`
`Feb. 24, 2004
`Prior Publication Data
`US 2005/0064829 A1
`Mar. 24, 2005
`
`FOREIGN PATENT DOCUMENTS
`
`EP
`
`1328.066
`
`T 2003
`
`* cited by examiner
`Primary Examiner Simon Nguyen
`(74) Attorney, Agent, or Firm Howard Seo; Eric Ho:
`Th
`R. R.
`OaS
`OUS
`(57)
`
`ABSTRACT
`
`An integrated circuit for a modem processor includes pro
`Related U.S. Application Data
`cessing units that are partitioned into “always-on and
`(60) Provisional application No. 60/504,507, filed on Sep.
`collapsible' power domains. An always-on power domain
`19, 2003
`is powered on at all times. A collapsible power domain can
`s
`be powered off if the processing units in the power domain
`(51) Int. Cl
`are not needed. A power control unit within an always-on
`(2006.01)
`tion iA6
`power domain powers down the collapsible power domains
`(200601)
`H4M I/O
`after going into sleep and powers up these domains after
`.
`(52) U.S. Cl. .................. 455/73; 455/127.5; 45); waking up from sleep. Tasks for powering down the col
`58) Field of Classification S
`h
`455/572 574
`lapsible power domains may include (1) saving pertinent
`(58) Field of Classification Search ........
`-u ( -r,
`hardware registers for these power domains, (2) freezing
`S
`lication file f 455/... i. 127.5
`output pins of the IC to minimally disturb external units, (3)
`ee appl1cauon Ille Ior complete searcn n1story.
`clamping input pins of the collapsed power domains, (4)
`References Cited
`powering down a main oscillator and disabling the oscillator
`clock, and so on. Complementary tasks are performed for
`powering up the collapsed power domains.
`
`U.S. PATENT DOCUMENTS
`
`(56)
`
`5,615,162 A
`5,745,860 A *
`
`3/1997 Houston ..................... 365,226
`4, 1998 Kallin ........................ 455,574
`
`39 Claims, 6 Drawing Sheets
`
`
`
`14
`
`
`
`116
`
`RCVR
`
`100
`
`Non-Volatile
`Memory
`(e.g., Flash)
`
`Volatile
`Memory
`(e.g., SDRAM)
`
`152
`
`154
`
`Main
`Oscillator
`
`Sleep
`Oscillator
`
`Qualcomm, Ex. 1006, Page 1
`
`

`

`U.S. Patent
`
`May 6, 2008
`
`Sheet 1 of 6
`
`US 7,369,815 B2
`
`sy
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`
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`(WWHO’S “6”e)
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`Qualcomm, Ex. 1006, Page 2
`
`

`

`U.S. Patent
`
`May 6, 2008
`
`Sheet 2 of 6
`
`US 7,369,815 B2
`
`
`
`0313
`
`sdoo-1
`
`------------------
`
`as seese -
`
`J?MOCH
`
`Qualcomm, Ex. 1006, Page 3
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`

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`U.S. Patent
`
`May 6, 2008
`
`Sheet 3 of 6
`
`US 7,369,815 B2
`
`120
`
`Collapsible
`POWer Domains
`
`FIG.2B
`
`
`
`as go
`
`212b
`-4------
`POWer
`Connection
`
`
`
`Vs
`
`214b
`
`212e
`-------4------
`Power
`Connection
`
`300
`-1
`
`Always-On
`POWer Domain
`
`Collapsible
`POWer Domain
`
`Collapsible
`POWer Domain
`
`210e
`
`Qualcomm, Ex. 1006, Page 4
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`

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`U.S. Patent
`
`May 6, 2008
`
`Sheet 4 of 6
`
`US 7,369,815 B2
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`
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`019
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`Qualcomm, Ex. 1006, Page 5
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`

`

`U.S. Patent
`
`May 6, 2008
`
`Sheet S of 6
`
`US 7,369,815 B2
`
`
`
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`UuJeNA
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`dn
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`UuJeNW
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`dn
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`9
`
`Qualcomm, Ex. 1006, Page 6
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`

`

`U.S. Patent
`
`May 6, 2008
`
`Sheet 6 of 6
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`US 7,369,815 B2
`
`
`
`
`
`
`
`SDRAM 9
`Program
`
`Flash
`Program
`
`Boot Code
`
`
`
`BOOt
`SRAM
`
`f34
`
`Modem Processor
`
`FIG. 7
`
`810
`essess - - - - - - - - -4----------------
`
`VDD a
`
`V
`
`freeze io
`
`814
`
`Collapsible
`Power
`Domain
`
`Shifter
`
`A
`
`y
`Domain
`
`power down
`ti---------------------------------.
`
`FIG. 8A
`
`VDD x
`
`820
`
`VDD a
`
`
`
`
`
`Collapsible
`Power
`DOmain
`
`X
`
`-
`
`X has to 8X
`
`as a
`
`-
`
`a
`
`as
`
`FIG. 8B
`
`Qualcomm, Ex. 1006, Page 7
`
`

`

`1.
`POWER COLLAPSE FOR AWIRELESS
`TERMINAL
`
`US 7,369,815 B2
`
`RELATED APPLICATIONS
`
`This application claims priority to U.S. Provisional Patent
`Application No. 60/504,507 filed Sep. 19, 2003.
`
`BACKGROUND
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`I. Field
`The present invention relates generally to circuits, and
`more specifically to techniques for conserving power for a
`wireless terminal.
`II. Background
`A wireless terminal (e.g., a cellular phone) in a cellular
`communication system is only sporadically active and
`remains in an "idle' mode for significant periods of time
`when no call is in progress. To ensure that the terminal can
`still receive messages sent to it by the system, the terminal
`periodically monitors a paging channel even while it is in the
`idle mode. These messages may alert the terminal to the
`presence of an incoming call, carry updated system param
`eters for the terminal, and so on.
`The wireless terminal is typically portable and powered
`by an internal battery. To conserve power and extend
`standby time between battery recharges, the system typically
`sends messages on the paging channel to the terminal at
`designated times. The paging channel may be divided into
`'slots, and the terminal may be assigned to specific slots by
`the system. Thereafter, the terminal enters an “active' state
`prior to its assigned slot, monitors the paging channel for
`messages, and transitions to an “inactive' state if additional
`communication is not required. In the time period between
`Successive active states, the terminal is asleep in the inactive
`state and deactivates as much circuitry as possible to con
`serve power. “Sleep’ refers to the time during which the
`terminal is in the inactive state.
`Conventionally, the terminal powers down analog circuit
`blocks (e.g., power amplifiers, oscillators, and so on) and
`disables clocks to digital circuit blocks while in the inactive
`state. A digital circuit that is fabricated in complementary
`metal oxide semiconductor (CMOS) consumes power via
`two mechanisms: (1) by dissipating dynamic current when
`the circuit is active and Switching and (2) by drawing
`45
`leakage current when the circuit is inactive and not switch
`ing. In contemporary CMOS fabrication technology, the
`dynamic current is many times greater than the leakage
`current. In this case, significant power saving may be
`achieved for CMOS digital circuits by simply disabling the
`clocks to these circuits to shut off the dynamic current.
`However, leakage current is not negligible and will
`become a significant portion of the total power consumption
`as CMOS technology scales to smaller geometry. This is
`because leakage current increases at a very high rate with
`respect to the decrease in transistor size. The higher leakage
`current, coupled with long periods of inactivity, consumes
`power and reduces standby time for portable devices that use
`battery power, which is highly undesirable.
`There is therefore a need in the art for techniques to
`conserve power for a wireless terminal.
`
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`SUMMARY
`
`Techniques for performing “power collapse' for a wire
`less terminal are provided herein. Power collapse refers to
`the powering down of circuit blocks/processing units when
`
`65
`
`2
`not needed to reduce leakage current and conserve power. To
`implement power collapse, the circuit blocks/processing
`units within an integrated circuit (IC) used for the wireless
`terminal are partitioned into multiple power domains. Each
`power domain couples to a power Supply via a power
`connection. Each power domain is designated as either
`“always-on' or “collapsible'. An always-on power domain
`is powered on at all times (i.e., while the wireless terminal
`is powered on). A collapsible power domain can be powered
`off if the processing units in the power domain are not
`needed.
`Power collapse is typically performed in conjunction with
`a sleep timeline that indicates when the wireless terminal
`can go to sleep. The sleep timeline may be different for
`different wireless communication systems. A power control
`unit within the always-on power domain powers down the
`collapsible power domains after going into sleep and powers
`up these domains just before waking up from sleep. The
`collapsed power domains may also be powered up based on
`an external interrupt event.
`A set of tasks is typically performed for powering down
`the collapsible power domains. For example, the powering
`down tasks may include Saving pertinent hardware registers
`of the collapsible power domains, freezing output pins of the
`IC to minimally disturb external units coupled to the IC,
`clamping input pins of the collapsed power domains, pow
`ering down a main oscillator and disabling a main clock
`from the oscillator, and so on. A complementary set of tasks
`is typically performed for powering up the collapsed power
`domains. For example, the powering up tasks may include
`powering up the main oscillator and enabling the main
`clock, restoring software, firmware, and hardware states,
`releasing input and output pins, and so on. These various
`tasks are described in further detail below.
`Various aspects, embodiments, and features of the inven
`tion are described in further detail below.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`The features and nature of the present invention will
`become more apparent from the detailed description set
`forth below when taken in conjunction with the drawings in
`which like reference characters identify correspondingly
`throughout and wherein:
`FIG. 1 shows a block diagram of the wireless terminal;
`FIG. 2A shows the partitioning of the modem processor
`into multiple power domains;
`FIG. 2B shows a layout of an integrated circuit for the
`modem processor,
`FIG. 3 shows a configuration for connecting the power
`domains to power Supply bus(es);
`FIG. 4 shows a timeline for processing a paging channel
`for a wireless communication system;
`FIGS. 5A and 5B show a powering down sequence and a
`powering up sequence, respectively, for the collapsible
`power domains;
`FIG. 6 shows timelines for three different systems:
`FIG. 7 illustrates a software boot process for the modem
`processor, and
`FIGS. 8A and 8B show interface and output circuits
`between the power domains and/or modem processor pads.
`
`DETAILED DESCRIPTION
`
`The word “exemplary' is used herein to mean “serving as
`an example, instance, or illustration.” Any embodiment or
`
`Qualcomm, Ex. 1006, Page 8
`
`

`

`3
`design described herein as “exemplary' is not necessarily to
`be construed as preferred or advantageous over other
`embodiments or designs.
`FIG. 1 shows a block diagram of a wireless terminal 100,
`which may be a cellular phone, a handset, a wireless
`communication device, a personal digital assistant (PDA),
`and so on. Terminal 100 may monitor and/or communicate
`with one or more wireless communication systems such as
`a Code Division Multiple Access (CDMA) system, a Global
`System for Mobile Communications (GSM) system, a Blue
`tooth system, a multiple-input multiple-output (MIMO) sys
`tem, an orthogonal frequency division multiple access
`(OFDMA) system, and so on. A CDMA system may imple
`ment one or more CDMA standards such as IS-2000 and
`IS-95 (which are also known as “1x-EV DV), IS-856
`(which is also known as “1x-EV DO), Wideband-CDMA
`(W-CDMA), and so on. A CDMA system that implements
`W-CDMA is also known as a Universal Mobile Telecom
`munications System (UMTS) system. Terminal 100 is
`capable of providing bidirectional communication via a
`receive path and a transmit path.
`For the receive path, signals transmitted by base stations
`in one or more systems are received by an antenna 112,
`routed through a duplexer (D) 114, and provided to a
`receiver unit (RCVR) 116. Receiver unit 116 conditions
`(e.g., filters, amplifies, and frequency downconverts) the
`received signal, digitizes the conditioned signal, and pro
`vides data samples to a modem processor 120 for further
`processing. For the transmit path, modem processor 120
`processes data to be transmitted by terminal 100 and pro
`vides “data chips' to a transmitter unit (TMTR) 118. Each
`data chip is a value to be transmitted in one chip period,
`which is 1/(1.2288x10) for some CDMA systems. Trans
`mitter unit 118 conditions (e.g., converts to analog, filters,
`amplifies, and frequency upconverts) the data chips and
`generates a modulated signal, which is routed through
`duplexer 114 and transmitted from antenna 112.
`Modem processor 120 includes various processing units
`that Support monitoring and/or communication with one or
`more systems. Modem processor 120 further interfaces with
`other units within terminal 100. For the embodiment shown
`in FIG. 1, modem processor 120 includes a modem core 130,
`a controller 132, an internal memory 134, phase locked
`loops (PLLs) 136, and a power control unit 140, all of which
`couple to a bus 128. Modem core 130 performs demodula
`tion and decoding for the receive path and encoding and
`modulation for the transmit path. Controller 132 controls the
`operation of various processing units within modem proces
`sor 120. Internal memory 134 stores data and program code
`used by the processing units within modem processor 120
`and may include a cache, random access memories (RAMS),
`read only memories (ROMs), and so on. PLLs 136 control
`various oscillators within terminal 100 such that these
`oscillators operate at the proper frequencies. Power control
`unit 140 controls power to various processing units within
`modem processor 120, as described below.
`For the embodiment shown in FIG. 1, modem processor
`120 further couples to a main oscillator 152, a sleep oscil
`lator 154, a volatile memory 156, and a non-volatile memory
`158, all of which support modem processor 120. Main
`oscillator 152 provides a high-frequency main/system clock
`used by modem processor 120 for normal operation and may
`be implemented, for example, with a temperature-compen
`sated crystal oscillator (TCXO). Sleep oscillator 154 pro
`vides a low-frequency sleep clock used by an always-on
`power domain within modem processor 120. Volatile
`memory 156 provides bulk storage for data and code used by
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`modem processor 120 and may be implemented with, for
`example, a synchronous dynamic RAM (SDRAM) or some
`other type of memory. Non-volatile memory 158 provides
`bulk non-volatile storage and may be implemented with, for
`example, a NAND Flash, a NOR Flash, or some other type
`of non-volatile memory.
`In general, modem processor 120 may include fewer,
`more and/or different processing units than those shown in
`FIG. 1. The specific processing units included in modem
`processor 120 are typically dependent on the design of
`modem processor 120 and the communication system(s)
`being Supported. Modem processor 120 may also couple to
`fewer, more and/or different external units than those shown
`in FIG. 1.
`Modem processor 120 may be implemented in a single
`CMOS integrated circuit for various benefits such as smaller
`size, lower cost, less power consumption, and so on. As IC
`fabrication technology continually improves and migrates to
`Smaller geometry, the size of transistors continues to shrink.
`A lower power Supply may be used for a smaller geometry
`IC to reduce power consumption. The threshold voltage
`(which is the voltage at which a transistor turns on) for
`Smaller-size transistors is often reduced (i.e., lowered) to
`improve operating speed. However, the lower threshold
`Voltage and Smaller transistor geometry result in higher
`leakage current, which is the current passing through a
`transistor when it is not Switching. Leakage current is more
`problematic as CMOS technology scales down to 90 nm
`(nanometer) and Smaller.
`Power consumption due to leakage current can be reduced
`by powering down as much digital circuitry as possible
`when not needed. Terminal 100 may only be active for a
`small portion of the time while it is idle. In this case, the
`power to many of the processing units can be powered down
`(i.e., “collapsed”) for a large portion of the time to reduce
`power consumption and extend standby time.
`Modem processor 120 is partitioned into multiple power
`domains. Each power domain includes processing units that
`are coupled to a power Supply via a power connection. Each
`power domain is designated as either always-on or collaps
`ible. An always-on power domain is powered on at all times
`while terminal 100 is powered on. A collapsible power
`domain may be powered down if the processing units in the
`power domain are not needed. Each collapsible power
`domain may be powered on or off independently of the other
`collapsible power domains. As used herein, "power up' and
`"power on are synonymous terms that are used inter
`changeably, and “power down and “power off are also
`synonymous terms.
`FIG. 2A shows the partitioning of the processing units
`within modem processor 120 into multiple power domains
`210. In this example, the five processing units 130 through
`140 in modem processor 120 are placed in five different
`power domains 210a through 210e. In general, each power
`domain can include any number of processing units, and
`each processing unit can include any number of circuit
`blocks. Each power domain 210 couples to a power supply
`bus 214 via a power connection 212. For the example shown
`in FIG. 2A, power domain 210a for power control unit 140
`is the only always-on power domain, and all other power
`domains 210b through 210e are collapsible.
`Each of processing units 130 through 140 within modem
`processor 120 may include various circuit blocks. For
`example, modem core 130 includes CDMA processing
`blocks 222, a clock generator 224, a modem digital signal
`processor (DSP) 226, a modem processor 228, a sub-system
`processor 230, RAMs 232, and ROMs 234. Clock generator
`
`Qualcomm, Ex. 1006, Page 9
`
`

`

`5
`224 generates various clocks used by the processing units
`within modem processor 120. CDMA processing blocks 222
`perform (1) encoding, interleaving, and modulation for the
`transmit path and (2) demodulation, deinterleaving, and
`decoding for the receive path. For example, CDMA pro
`cessing blocks 222 may implement a rake receiver with
`multiple searchers and finger processors for the receive path,
`as is known in the art. CDMA processing blocks 222 also
`perform other ancillary functions such as maintaining a real
`time counter (RTC), which provides system time, for each
`system being monitored by terminal 100. Modem DSP 226
`performs modem (modulation/demodulation) functions that
`are not time critical Such as pilot channel processing, traffic
`channel processing (e.g., processing on Soft decisions) and
`so on. Modem processor 228 controls the operation of
`various circuit blocks within modem core 130. Sub-system
`processor 230 controls input/output (I/O) buses and periph
`erals. Processors 228 and 230 may be implemented with
`reduced instructing set computing (RISC) processors.
`RAMs 232 and ROMs 234 store data and code used by
`modem core 130.
`Power control unit 140 controls the power for each of the
`collapsible power domains and is described in further detail
`below.
`FIG. 2B shows an exemplary layout of a CMOS inte
`grated circuit for modem processor 120. FIG. 2A shows the
`processing units for modem processor 120 but does not
`indicate the size of each unit. FIG. 2B shows the size of
`always-on power domain 210a versus the size of collapsible
`power domains 210b through 210e. In a typical implemen
`tation, the always-on power domain occupies only a small
`portion (e.g., two to three percent) of the total die area of the
`integrated circuit, and the collapsible power domains occupy
`most of the die area. Thus, leakage current for the integrated
`circuit may be significantly reduced by powering down the
`collapsible power domains when not needed.
`Power connection 212 for each collapsible power domain
`210 includes appropriate hardware to Supply power to and
`remove power from the processing blocks within the power
`domain. Each collapsible power domain 210 can be powered
`down if none of the processing units in the domain is needed.
`FIG. 3 shows a configuration 300 for connecting power
`domains 210 to power supply buses. Power connection 212a
`couples always-on power domain 210a directly to a power
`Supply bus 214a, which is denoted as Vs. Power connec
`tions 212b through 212e are for collapsible power domains
`210b through 210e, respectively. For the embodiment shown
`in FIG. 3, each of power connections 212b through 212e
`includes a headswitch that can be either enabled to power up
`the domain or disabled to power down the domain. The
`headswitch for each collapsible power domain x (where
`x=b, c, d, or e) may be implemented with a P-channel FET
`312 having a source that couples to a power supply bus 214b
`(which is denoted as Vs), a drain that couples to an internal
`power bus for the power domain (which is denoted as
`V,
`), and a gate that receives apwr_ctrl X control signal
`for the power domain. The pWr ctrl X signal is logic low to
`power up power domain X and logic high to power down
`power domain X. Power supply buses 214a and 214b may
`have the same or different voltages.
`Power for the collapsible power domains may be con
`trolled in other manners, and this is within the scope of the
`invention. For example, a footswitch between the power
`domain and circuit ground may be used to control power to
`the power domain. As another example, both headswitch and
`footswitch may be used for a given collapsible power
`domain. In general, an integrated circuit may include any
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`number of power Supply buses. One power Supply bus may
`be used for input/output (I/O) pads for the integrated circuit
`and this power Supply bus may be powered on at all times
`while terminal 100 is powered on. Always-on power domain
`210a may then be coupled to this power supply bus for the
`I/O pads. Multiple power supply buses may be used to
`provide different supply voltages or for different power
`regimes.
`Power control unit 140 includes various circuit blocks that
`Support powering on and off the collapsible power domains.
`For the embodiment shown in FIG. 2A, power control unit
`140 includes state registers 242, a sleep controller 246, a
`clock controller 248, an interrupt controller 250, and a
`power controller 252. State registers 242 store (1) powered
`down status of the collapsed power domains and (2) perti
`nent hardware states (e.g., finite state machine (FSM) states)
`that cannot be restored by Software upon power up.
`Sleep controller 246 monitors activity and keeps track of
`sleep timeline for each system being monitored. Terminal
`100 may monitor one or multiple systems such as, for
`example, 1x-EV DV. lx-EV DO, and GSM systems, which
`are described below and shown in FIG. 6. In an embodiment,
`sleep controller 246 includes one sleep core for each system.
`Each sleep core includes a sleep counter and a sleep finite
`state machine (FSM). The sleep counter maintains system
`time continuity during sleep. When the sleep counter expires
`at the start of warm-up time (see FIG. 4), sleep controller
`246 interrupts power controller 252 to wake-up. The sleep
`counter continues to count the duration of the warm-up time.
`When the sleep counter expires at the start of on-line time,
`sleep controller 246 interrupts modem processor 120 to
`indicate the start of on-line processing. During the active
`state, a real time counter (RTC) within modem core 130
`maintains system time for each system being monitored.
`Clock controller 248 disables main clock 152 prior to
`powering down and enables main clock 152 after powering
`up. Interrupt controller 250 monitors input signals from
`other units external to modem processor 120. These input
`signals are received via the pads of modem processor 120.
`Interrupt controller 250 detects for interrupts from these
`external units and alerts power controller 252 when it
`receives an external interrupt requiring modem processor
`120 to wake up.
`Power controller 252 generates various control signals
`used to Support powering down and up the collapsible power
`domains. Power controller 252 receives signals from sleep
`controller 246 indicating the start and end of a sleep period
`and external interrupts from interrupt controller 250. Power
`controller 252 may maintain a finite state machine (FSM) for
`each block to be controlled (e.g., main oscillator) and a FSM
`for each power domain to be separately powered on and off.
`Based on these various inputs and the FSMs, power con
`troller 252 generates the control signals to power down and
`up the collapsible power domains at the appropriate time.
`For example, power controller 252 can generate the pwr ctrl
`signals for the Switches in power connections 212, as shown
`in FIG. 3. Power controller 252 can also generate a signal for
`an external power management unit, which can then power
`up or down the power supply bus(es) for the collapsible
`power domains.
`Power control unit 140 stores information for the timeline
`for each system being monitored and determines the time
`periods in which the collapsible power domains may be
`powered down. Power control unit 140 may power down the
`collapsible power domains if the duration of sleep is suffi
`ciently long (e.g., exceeds a predetermined time period).
`Power control unit 140 may forego powering down if the
`
`Qualcomm, Ex. 1006, Page 10
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`US 7,369,815 B2
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`7
`sleep period is too short and powering down would not be
`justified by the overhead associated with powering down
`and up. If the collapsible power domains are not powered
`down because the sleep period is too short, then the main
`clock may still be disabled to cut off dynamic current and
`reduce power consumption.
`Power control unit 140 performs a number of tasks to
`properly power down and power up the collapsible power
`domains within modem processor 120. Table 1 lists some of
`the tasks that may be performed for powering down and up
`the collapsible power domains. Fewer, additional and/or
`different tasks may also be performed, depending on the
`design of modem processor 120.
`
`8
`example, the radio frequency (RF) front end, power ampli
`fiers, oscillators, and so on for the transmit and receive paths
`are often powered down during sleep. Moreover, the cir
`cuitry for the transmit path does not need to be powered up
`to receive messages. For simplicity, only tasks and events
`related to powering down and up modem processor 120 are
`described below.
`Many cellular systems use a paging channel to transmit
`messages to idle terminals. In a 1xEV DV system, the
`paging channel (PCH) is divided into (80 msec) paging
`channel slots. A terminal operating in a slotted mode is
`assigned specific slots on the paging channel. A slot cycle
`index (SCI) determines how often the terminals assigned
`slots appear on the paging channel. An SCI of one indicates
`that the assigned slots appear every 2.56 seconds. Paging
`messages (if any) are sent to the terminal in its assigned
`slots.
`Different cellular systems may use different structures and
`formats for the paging channel. However, the same general
`concept is typically used for all paging channel implemen
`tations. A terminal is assigned to only a small portion of the
`paging channel timeline and only needs to be active for a
`Small portion of the time to process the paging channel. To
`conserve power, the terminal can sleep and most of the
`analog and digital circuits can be powered down.
`FIG. 4 shows a timeline for processing the paging channel
`in the 1xEV DV system. In FIG. 4, a new paging slot cycle
`for terminal 100 starts at time To Terminal 100 sleeps from
`time To until its next assigned slot. Terminal 100 wakes up
`at time T, prior to its next assigned slot, and powers on and
`warms up the necessary circuitry. Terminal 100 receives and
`processes the paging channel starting at time T. Terminal
`100 finishes processing the paging channel at time Ts and
`thereafter goes back to sleep if additional communication is
`not needed. The terminal may sleep for a significant portion
`of the time. As an example, for the 1xEV system with
`SCI-1, the sleep time from To to T. may be 2503 msec, the
`warm-up time from T to T. may be 17 mSec, and the active
`(i.e., on-line) time from T to Ts may be 40 m.sec. In this
`case, terminal 100 can sleep for over 97 percent of the time.
`FIG. 4 also shows an overlay of power collapse over the
`sleep timeline. After completion of the on-line processing at
`time To terminal 100 performs powering down tasks during
`the power-down period from time To to time T. Prior to the
`warm-up time, terminal 100 performs powering up tasks
`during the power-up period from time T to time T.
`FIG. 5A shows a timeline for a powering down sequence
`510 to turn off power to the collapsible power domains
`within modem processor 120. Power control unit 140 per
`forms the tasks listed in Table 1 during the power-down
`period after it has been determined that the terminal can go
`to sleep because no additional communication is required.
`At time T, the pertinent hardware registers are saved. At
`time T, memory 156 is placed in the low power mode
`during sleep. At time T, the state of the output pins for
`modem processor 120 is frozen. At time T, the main clock
`is disabled. At time Ts, power is removed from the col
`lapsible power domains. At time T, main oscillator 152 is
`powered down. The tasks for powering down may be
`performed in other chronological orders than that shown in
`FIG. 5A. These tasks can typically be performed within a
`short period of time (e.g., one msec).
`FIG. 5B shows a timeline for a powering up sequence 520
`to turn on power to the collapsible power domains within
`modem processor 120. Power control unit 140 performs the
`tasks listed in Table 1 during the power-up period prior to the
`warm-up time for the assigned paging slot. At time T, main
`
`10
`
`15
`
`TABLE 1.
`
`Powering Down Tasks
`Save pertinent hardware state 1
`registers from collapsible
`2
`power domains
`Put external memory 156 in
`low power mode
`Freeze IC output pins
`3
`4 Disable main clock to
`collapsible power domains
`Power off collapsible power
`domains
`Power off main oscillator 152
`
`1
`
`2
`
`5
`
`6
`
`3
`
`4
`
`Powering Up Tasks
`
`Power on main oscillator 152
`Power on collapsed power
`domains
`Enable main clock to collapsed
`power domains
`Take external memory 156 out
`of low power mode
`Reboot software
`Re-download firmware image
`Restore hardware registers
`Release IC output pins
`
`25
`
`30
`
`40
`
`45
`
`Some hardware states may need to be saved before
`powering down so that modem processor 120 can properly
`resume operation upon being powered on. The output pins
`for modem processor 120 are maintained at the “latest” logic
`state, which is the logic state right before powering down,
`during the entire time that modem processor 120 is powered
`down so that external units coupled to modem processor 120
`35
`are minimally affected by the modem processor being pow
`ered down. Memory 156 stores code and data used by
`various processing units within modem processor 120 and is
`placed in a low power mode when the modem processor is
`powered down. The main clock is disabled, and main
`oscillator 152 is also powered off during sleep. Power is
`removed from each collapsible power domain by controlling
`the Switch in the power connection for that power domain.
`In general, complementary tasks are performed to power
`down and power up. Each of the tasks in Table 1 is described
`in further detail below.
`Modem processor 120 includes various processing units
`that may be grouped into three different categories—gen
`eral-purpose processors, specialized processors, and hard
`ware blocks. The general-purpose processors (e.g., control
`ler 132, modem processor 228, and Sub-system processor
`230) operate based on software code and may be configured
`to perform various functions. Specialized processors (e.g