UNITED STATES PATENT AND TRADEMARK OFFICE
`
`Paper No.1
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`QUALCOMM INC. AND QUALCOMM TECHNOLOGIES,
`INC.,
`
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`TITLE: HARDWARE AUTOMATIC PERFORMANCESTATE
`TRANSITIONS IN SYSTEM ON PROCESSOR SLEEP AND
`WAKE EVENTS
`
`Petitioners
`
`Vv.
`
`APPLEINC.,
`
`Patent Owner
`
`U.S. PATENT NO.8,271,812
`
`Issue Date: September 18, 2012
`
`PETITION FOR INTER PARTES REVIEW
`UNDER35 U.S.C.§ 312
`
`ÿ
`
`1
`
`APPLE 2002
`QUALCOMMV. APPLE
`IPR2019-00325
`
`1
`
`APPLE 2002
`QUALCOMM V. APPLE
`IPR2019-00325
`
`

`

`TABLE OF CONTENTS
`
`Page
`
`Trntroduction............cceeccesessessessesceseescescescececeseeseeseeseeseeaeeseeseeaeeseeaeeaceaeeaeeaeeaeeaeeas 1
`
`Il.
`
`Mandatory Notices...........ccccsccsccssssssesssesssscessesscesesssecsesaessesseessesseeesessuseseeesesanseaes 3
`
`A.—Real Party in Interest (37 C.F.R. § 42.8(D)(1)) .occec cece eeseceteeeteeeeeees 3
`
`B.—Related Matters (37 C.F.R. § 42.8(b)(2)) .....ccccccceccccsccesssecessseeeeeseeees 4
`
`C.
`
`Lead and Back-Up Counsel and Service Information (37 C.F.R.
`§ 42.8(b)(3) and (b)(4)) occ eeeesessseeeessesseeeeeeseesaeeeeeseeeeeaeeseeeaeeeaeensens 4
`
`D.—Fees (37 C.F.R. § 42.103) .oecceeceececcesceeseceseceneeeseeesaeseaeeeeeeeeeseeeneeeees 5
`
`IIL.
`
`IV.
`
`Grounds for Standing Pursuant to 37 C.F.R. § 104(a).........cccscssecseesesseeseeeeees 5
`
`Statement of Precise Relief Requested for Each Challenged Claim................. 6
`
`A.
`
`B.
`
` 37C.F.R. § 42.104(b)(1): Claims for Which Review Is
`Requested ........ccceccscccecssssecceceesssneeceesessseeceeesessseecesessaeeeecsestsaeeesesesaeeees 6
`
` 37C.F.R. § 42.104(b)(2): Statutory Groundsand Prior Art on
`Whichthe Challenge is Based... eee eeceeeeseeeeseeeeeeeeeeseeeeeeeenneeeeneees 6
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`Reasonsfor the Relief Requested Under 37 C.F.R. §§ 42.22(a)(2) and
`42.104(D(A)... eccecscssescecescescesescesceseseeseesesecseeaesceseeesseeseeeeseeseaeseeaeeaseeaeeaseeaeeaes 7
`
`A.
`
`Overview of the ’812 Patent and its Technology..........cecceeeseeeeseeeeeee 7
`
`B.—The Prosecution History of the °812 Patent ........ cee eceeceeeeeeeeeeees 12
`
`C.
`
`37C.F.R. § 42.104(b)(3): Claim Construction.........0...ccccceeeeseeeeeeeeees 14
`
`1.
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`2.
`
`A Person of Ordinary Skill in the ALt....... ce cccseesseeeeeees 14
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`Construction of Claim Terms............c.cccccsssseessseeseeeeeeeeseeeeeeees 14
`
`D.
`
`E.
`
`F.
`
`Overview of the Prior Art........cee ce ceeeceeeceeeeeeeeeeeeeeeeeeeeeeeeeeaeeeeeeneeees 18
`
`37 C.F.R. § 42.104(b)(4): How the Construed Claims are
`Unpatentable .........cc ccc cece ccceccccesceceeseeeeeseeceeesueeeeesseeeesaeeeeeseeeesaeees 31
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`37C.F.R. § 42.104(b)(5): Supporting Evidence........ eee eeeeeeeeeeeeees 31
`
`Claims 8 and 9 of the ’812 Patent Are Unpatentable ..............ccccsesseeseeeeeeees 32
`
`A.—Ground 1: Claims 8 and 9 are Anticipated by Mandelblat................ 32
`
`1.
`
`2.
`
`Independent Claim 8 ............ccccccssecsscecseecssseeesaeeeseeessaeeesanessaees 32
`
`Dependent Claim 9 ..........cccccccssessscesssesssseeeseeeesesesseeeesaneesaees 42
`
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`2
`
`

`

`TABLE OF CONTENTS
`(continued)
`
`Page
`
`B.
`
`Ground 2: Claims 8 and 9 are Rendered Obvious by Mandelblat
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`C.
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`Ground 3: Claim 9 is Rendered Obvious by Mandelblat in view
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`D.|Ground 4: Claims 8 and 9 Are Rendered Obviousby Kurts in
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`VIE.
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`-ii-
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`3
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`The 812 Patent relates to an integrated circuit, such as a system on chip
`
`(“SoC”), which includes one or more performance domains, with each domain having
`
`one or more components. Ex. 1001 Abstract, 2:31—34, 3:29-47 and Fig. 1. Among
`
`these components are processors, which can have “awake” and “sleep” performance
`
`states.
`
`Id. at 1:35-47, 6:37-50. When a processor is awake, it is supplied with a
`
`voltage and a clock signal, and can process instructions.
`
`Jd.; see also Ex. 1002
`
`(Declaration of Vijay K. Madisetti, Ph.D), | 40. “In the sleep state, the processoris
`
`idle (not executing instructions),” and power is conserved. Ex. 1001, 6:38-39; see
`
`also id. at 1:35—47 (discussing clock and powergating); Ex. 1002,
`
`41.
`
`Components can have performancestates that are related to whether a processor
`
`is awake or asleep. As the ’812 Patent explains:
`
`When the processors are in the sleep state, these other
`
`components need not be operating at
`
`such a high
`
`performance level.
`
`Similarly, when the processors are
`
`awakened from the sleep state, the performance level at
`
`L
`
`Introduction
`
`Pursuant to 35 U.S.C. § 312 and 37 C.F.R. § 42.100 et seg., Qualcomm Inc.
`
`and Qualcomm Technologies, Inc.
`
`(collectively, “Petitioners” or “Qualcomm’’)
`
`No. 8,271,812 (‘the ’812 Patent,” Ex. 1001), which is assigned to Apple,Inc. (“Patent
`
`Owner”or “Apple’”’).
`
`request interpartes review ofclaims8 and 9 (the “Challenged Claims”) ofU.S. Patent
`
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`whichthe processors and other components needto operate
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`
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`
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`
`Ex. 1001, 1:40-47. Accordingly, processors, other non-processor components, and
`
`their performance domains maytransition between “wake” and “sleep” performance
`
`states depending on whethera processor is awakeor asleep. Jd.; Ex. 1002, 9] 42-48.
`
`The ’812 Patent further explains that in the priorart, “[t]he sleep/waketransitions of
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`the processors and other components are changed under software control.” Ex. 1001,
`
`1:48-49. However, software control of power management and sleep/wake
`
`transitions had purported drawbacks that limited the amount of power conserved and
`
`performanceof the device. Jd. at 1:49-58.
`
`The ’812 Patent is directed to “a power management unit (PMU) [that] may
`
`automatically transition (in hardware) the performance states of one or more
`
`performance domainsin a system.” Ex. 1001, Abstract, 1:62—65. According to the
`
`specification, “the power management unit may monitor the processor to detect that
`
`the processor is entering the sleep state or has entered the sleep state,” and transition
`
`performance domainsto their “sleep” performancestates. Jd. at 2:3—-5, 5:44—49, 9:39-
`
`10:2 and Fig. 3 (steps 40, 42, and 44). “[T]he power managementunit may[also] be
`
`programmable with a second set of target performance states to which the
`
`performance domainsareto transition whenthe processorexits the sleep state,” when
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`of record during the prosecution of the ’812 Patent, as well as by the Kang Patent,
`
`which wasofrecord but wasnot previously considered in view of any of Mandelblat,
`
`Kurts, or Lint.
`
`Because the Challenged Claimsare unpatentable overthepriorart, interpartes
`
`review should beinstituted, and the Challenged Claims should be cancelled.
`
`II. Mandatory Notices
`
`A.
`
`Real Party in Interest (37 C.F.R. § 42.8(b)(1))
`
`Qualcomm Inc. and Qualcomm Technologies, Inc. are the real parties-in-
`
`interest.
`
`-3-
`
`the processor awakens, and transition performance domains to their “wake” state
`
`performancestates.
`
`Id. at 2:8-12, 5:4449, 10:13-25 and Fig. 3 (steps 48, 50, and
`
`52).
`
`However, integrated circuits having different performance domains comprised
`
`of processor and non-processor components were already well-known at the time the
`
`application for the ’812 Patent wasfiled in April 2010. Furthermore,there is nothing
`
`patentable about a power management unit configured to transition the performance
`
`state of each performance domain whenaprocessortransitions to or from a sleep or
`
`wakestate. These claimed features were disclosed in the prior art, including by U.S.
`
`Patents and published applications to Mandelblat, Kurts, and Lint, none ofwhich were
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`B.
`
`Related Matters (37 C.F.R. § 42.8(b)(2))
`
`The ’812 Patent and its related continuation patents (U.S. Pat. Nos. 8,443,216
`
`and 8,656,196) are involved in the following pendinglitigation that may affect, or be
`
`affected by, a decision in this proceeding: Qualcomm Inc. v. Apple Inc., Case No.
`
`3:17-cv-1375 (S.D. Cal.) ¢° 1375 Case”).
`
`Petitioners are filing IPR petitions directed to related continuation patents
`
`claiming priority to the *812 patent (U.S. Pat. Nos. 8,443,216 and 8,656,196)
`
`concurrently with the filing ofthis petition.
`
`C.
`
`Lead and Back-Up Counseland Service Information (37 C.F.R.
`§ 42.8(b)(3) and (b)(4))
`
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`Back-up Counsel
`Matthew W.Johnson, Reg. No. 59,108
`JONES DAY
`One Mellon Center
`500 Grant Street
`Pittsburgh, PA 15219
`(412) 394-9524
`mwjohnson@jonesday.com
`John M.Michalik, Reg. No. 56,914
`JONES DAY
`77 W. Wacker Dr.
`Chicago, IL 60601
`(312) 269-4215
`jmichalik@jonesday.com
`Thomas W.Ritchie, Reg. No. 65,505
`JONES DAY
`77 W. Wacker Dr.
`Chicago, IL 60601
`(312) 269-4003
`twritchie@jonesday.com
`
`Lead Counsel
`John A. Marlott, Reg. No. 37,031
`JONES DAY
`77 W. Wacker Dr.
`Chicago, IL 60601
`(312) 269-4236
`jamarlott@jonesday.com
`
`-4-
`
`7
`
`

`

`ÿ ÿ
`
`fees are due for a total of $30,500.
`
`III. Grounds for Standing Pursuant to 37 C.F.R. § 104(a)
`
`Petitioners certify that the ’812 Patent is available for inter partes review, and
`
`that Petitioners are not barred or estopped from requesting inter partes review ofthe
`
`Challenged Claims on the groundsidentified in this Petition. Apple filed and served
`
`its first amended answer and counterclaims in the ’1375 Case, first asserting
`
`infringement of the ’812 Patent by Petitioners, on November 29, 2017.
`
`’1375 Case,
`
`ECF No. 97. This petition is being filed within one year of service of Apple’s first
`
`amended answerand counterclaims, and shortly after the District Court issued a claim
`
`construction order adopting certain of Apple’s positions regarding the breadth of the
`
`°812 Patent’s claims.
`
`-5-
`
`Pursuant to 37 C.F.R. § 42.10(b), a Power of Attorney accompanies this
`
`Petition. Please address all correspondenceto lead and back-up counselat the address
`
`above. Qualcomm also consents to electronic service by email at the email addresses
`
`listed above.
`
`D.
`
`Fees (37 C.F.R.§ 42.103)
`
`The undersigned representative of Petitioners authorizes the Board to charge
`
`the $15,500 Petition Fee, as well as any additional fees, to Deposit Account 501432,
`
`ref: 178774-680003. Two claims are being reviewed, so $15,000 in post institution
`
`
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`earlier-filed U.S. patent application. Accordingly, the earliest date to which the ’812
`
`Patent could claim priority (hereinafter the “earliest effective filing date”) is April 7,
`
`2010.
`
` 
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`Reasons for the Relief Requested Under 37 C.F.R. §§ 42.22(a)(2) and
`42.104(b)(4)
`
`Mandelblat was filed August 22, 2005, published February 22, 2007, and is
`
`prior art under pre-AIA 35 U.S.C. §§ 102(a), (b), and (e).
`
`Kurts wasfiled August 31, 2004, issued April 22, 2008, and is prior art under
`
`pre-AIJA 35 U.S.C. §§ 102(a), (b), and (e).
`
`Lint wasfiled September 30, 2004 and issued September 16, 2008, and is prior
`
`art under pre-AIA 35 U.S.C. §§ 102(a), (b), and (e).
`
`Kang wasfiled February 24, 2004 and issued May 6, 2008, andis prior art
`
`under 35 U.S.C. § 102(a), (b), and (e).
`
`V.
`
`A.
`
`Overview of the ’812 Patent and its Technology
`
`The ’812 Patent
`
`is entitled “Hardware Automatic Performance State
`
`Transitions in System on Processor Sleep and Wake Events.” Ex. 1001. Asits title
`
`suggests,
`
`the *812 Patent
`
`is related to transitioning the performance states of
`
`performance domainsand their componentsin responseto a processor’s going to sleep
`
`or waking up. Jd. at Abstract, 1:33-58.
`
`The ’812 Patentis directed to reducing the amountoftime required for portions
`
`of a system (e.g., an integrated circuit), referred to as “performance domains,” to
`
`10
`
`

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`In Figure 1, “[t]he integrated circuit 10 includes a set of performance domains
`
`14A-14F. Each performance domain 14A-14F includes at least one componentofthe
`
`integrated circuit 10, and a given performance domain may include more than one
`
`-8-
`
`11
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`transition to a different “performancestate” when the processorenters or exits a sleep
`
`state. Id. at Abstract. The ’812 Patent purports to resolve this problem by controlling
`
`these performance state changes using a programmable hardware-based “power
`
`management unit,” or PMU.
`
`Figure 1, reproduced below, discloses “an integrated circuit (IC) 10” that
`
`includes performance domains. Jd. at 3:29-33.
`
`11
`
`

`

`ÿ ÿ
`
`“The integrated circuit 10 also includes a power management unit (PMU)
`
`28....” Ex. 1001, 3:47-48. “The PMU 28 maybe configured to control transitions
`
`between performancestates for the various performance domains 14A-14F.” Jd. at
`
`3:63-65. The PMU 28 maytransition the performance states of one or more of the
`
`performance domains 14A—14F in response to a processor either “entering a sleep
`
`state” and going to sleep, or “exiting the sleep state” and “waking” up. Jd. at 3:65—
`
`4:8. “In one embodiment, the PMU 28 may detect that the processor 16A-16B is
`
`entering/exiting the sleep state, and may cause corresponding transitions in the
`
`performance domains.” Ex. 1001, 5:46—-48. It was already well known in theart in
`
`April 2010 that the performance of components (and performance domains) could be
`
`adjusted corresponding to whether a processor was in a wakeorsleep state. Ex. 1002,
`
`q 55.
`
`“A performance domain may be one or more components that may be
`
`controlled by the PMU 28as a unit for performance configuration purposes.” Ex.
`
`1001, 4:14-16.
`
`“[T]he PMU 28 may be configured to establish a corresponding
`
`-9-
`
`component.” Jd. 3:32—36. Further, certain performance domains may havespecific
`
`functionality and associated components. Jd. at 3:41-47. Dividing components of a
`
`chip into different performance domains, in which the operational characteristics
`
`54.
`
`could be separately adjusted was already well-known as of April 2010. Ex. 1002, 4
`
` 
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`performance state for each performance domain.”
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`Ex. 1001, 4:16-18.
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`“The
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`performancestate may include any combination ofperformancecharacteristics for the
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`components in a corresponding performance domain.”
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`Jd. at 4:31-33.
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`“A
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`performance characteristic may be any configurable setting for a component that
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`affects the performance of that component.”
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`Jd. at 4:33-35. For example, a
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`component’s clock frequency or supply voltage level may be a performance
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`characteristic of that component.
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`Jd. at 4:35-38. When the clock frequency or
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`operating voltage is changed, power consumption and the performancestate of the
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`changes, the PMU 28 may communicate the newsettings to the clock/voltage control
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`unit 32.” Id. at 5:59-61. The ’812 Patent discloses numerousother characteristics of
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`domain also changes. Jd. at 4:63—-66. “In the case of voltage and clock frequency
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`a component that may qualify as a performance characteristic and impact power
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`consumption.
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`Jd. at 4:35-62, 4:67-5:18. For example, the ’812 Patent expressly
`
`discloses that cache memory size may be a performance characteristic. Id. at 4:40-42
`
`(‘For example, cache sizes in various caches maybe a performance characteristic.”).
`
`These features were also known in the prior art in April 2010. Ex. 1002, 4 56.
`
`The PMU mayinclude “one or more performance configuration registers 30.”
`
`Ex. 1001, 3:48—49, Fig. 1 (PMU 28 including “Perf Config”registers). These registers
`
`specify the performance states of different performance domains based upon the
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`“awake” and “sleep” states of a processor. “For example, performance states to be
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`used in the performance domains 14A—14F whenthe processoris in sleep state may
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`be specified in the performance configuration registers 30. Performancestates to be
`
`used when the processor 16A—16B exits the sleep state (awakens) may also be
`
`specified” Ex. 1001, 5:52-57. One embodiment of the PMU’s performance
`
`configuration registers is shown in Figure 2. See Ex. 1001, 7:38-9:24. In Figure 2,
`
`“t]he register set 30B may include a c