Paper No. 1
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`__________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`__________________
`
`
`QUALCOMM INC. AND QUALCOMM TECHNOLOGIES,
`INC.,
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`Petitioners
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`v.
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`APPLE INC.,
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`Patent Owner
`
`
`
`U.S. PATENT NO. 8,656,196
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`TITLE: HARDWARE AUTOMATIC PERFORMANCE STATE
`TRANSITIONS IN SYSTEM ON PROCESSOR SLEEP AND
`WAKE EVENTS
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`Issue Date: February 18, 2014
`
`
`PETITION FOR INTER PARTES REVIEW
`UNDER 35 U.S.C. § 312
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`
`
`
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`__________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`__________________
`
`
`QUALCOMM INC. AND QUALCOMM TECHNOLOGIES,
`INC.,
`
`Petitioners
`
`v.
`
`APPLE INC.,
`
`Patent Owner
`
`
`
`U.S. PATENT NO. 8,656,196
`
`TITLE: HARDWARE AUTOMATIC PERFORMANCE STATE
`TRANSITIONS IN SYSTEM ON PROCESSOR SLEEP AND
`WAKE EVENTS
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`Issue Date: February 18, 2014
`
`
`PETITION FOR INTER PARTES REVIEW
`UNDER 35 U.S.C. § 312
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`
`
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`TABLE OF CONTENTS
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`Page
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`Introduction ........................................................................................................ 1
`I.
`II. Mandatory Notices ............................................................................................. 1
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`III. Grounds for Standing Pursuant to 37 C.F.R. § 104(a) ...................................... 3
`IV.
`Statement of Precise Relief Requested for Each Challenged Claim ................ 3
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`V.
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`Reasons for the Relief Requested Under 37 C.F.R. §§ 42.22(a)(2) and
`42.104(b)(4) ........................................................................................................ 5
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`2.
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`A Person of Ordinary Skill in the Art ...................................... 12
`Construction of Claim Terms ................................................... 12
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`VI. Claims 1, 2, 3, 7 and 8 of the ’196 Patent Are Unpatentable ......................... 25
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`TABLE OF CONTENTS
`(continued)
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`Page
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`Independent Claim 1 ................................................................ 27
`Dependent Claim 2 .................................................................. 38
`Dependent Claim 3 .................................................................. 39
`Independent Claim 7 ................................................................ 40
`Dependent Claim 8 .................................................................. 40
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`Independent Claim 1 ................................................................ 44
`Dependent Claim 2 .................................................................. 53
`Dependent Claim 3 .................................................................. 54
`Independent Claim 7 ................................................................ 54
`Dependent Claim 8 .................................................................. 55
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`1.
`2.
`3.
`4.
`5.
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`1.
`2.
`3.
`4.
`5.
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`1.
`Independent Claim 1 ................................................................ 58
`2.
`Dependent Claim 2 .................................................................. 63
`3.
`Dependent Claim 3 .................................................................. 64
`4.
`Independent Claim 7 ................................................................ 65
`5.
`Dependent Claim 8 .................................................................. 65
`VII. Conclusion ........................................................................................................ 66
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`I.
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`Introduction
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`Pursuant to 35 U.S.C. § 312 and 37 C.F.R. § 42.100 et seq., Qualcomm Inc.
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`and Qualcomm Technologies, Inc. (collectively, “Petitioners” or “Qualcomm”)
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`request inter partes review of claims 1, 2, 3, 7 and 8 (the “Challenged Claims”) of
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`U.S. Patent No. 8,656,196 (“the ’196 Patent,” Ex. 1001), which is assigned to Apple,
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`Inc. (“Patent Owner” or “Apple”). Because the Challenged Claims are unpatentable
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`over the prior art, inter partes review should be instituted, and the Challenged Claims
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`should be cancelled.
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`II. Mandatory Notices
` Real Party in Interest (37 C.F.R. § 42.8(b)(1))
`Qualcomm Inc. and Qualcomm Technologies, Inc. are the real parties-in-
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`interest.
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` Related Matters (37 C.F.R. § 42.8(b)(2))
`The ’196 Patent and its Related Patents (U.S. Pat. No. 8,443,216, the parent of
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`the ’196 Patent, and U.S. Pat. No. 8,271,812, the grandparent of the ’196 patent) are
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`involved in the following pending litigation that may affect, or be affected by, a
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`decision in this proceeding: Qualcomm Inc. v. Apple Inc., Case No. 3:17-cv-1375
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`(S.D. Cal.) (“’1375 Case”).
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`Petitioners are filing IPR petitions directed to the Related Patents (U.S. Pat.
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`Nos. 8,443,216 and 8,271,812) concurrently with the filing of this petition.
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` Lead and Back-Up Counsel and Service Information (37 C.F.R.
`§ 42.8(b)(3) and (b)(4))
`Lead Counsel
`John A. Marlott, Reg. No. 37,031
`JONES DAY
`77 W. Wacker Dr.
`Chicago, IL 60601
`(312) 269-4236
`jamarlott@jonesday.com
`
`Back-up Counsel
`Matthew W. Johnson, Reg. No. 59,108
`JONES DAY
`One Mellon Center
`500 Grant Street
`Pittsburgh, PA 15219
`(412) 394-9524
`mwjohnson@jonesday.com
`John M. Michalik, Reg. No. 56,914
`JONES DAY
`77 W. Wacker Dr.
`Chicago, IL 60601
`(312) 269-4215
`jmichalik@jonesday.com
`Thomas W. Ritchie, Reg. No. 65,505
`JONES DAY
`77 W. Wacker Dr.
`Chicago, IL 60601
`(312) 269-4003
`twritchie@jonesday.com
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`Pursuant to 37 C.F.R. § 42.10(b), a Power of Attorney accompanies this
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`Petition. Please address all correspondence to lead and back-up counsel at the address
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`above. Qualcomm also consents to electronic service by email at the email addresses
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`listed above.
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`Fees (37 C.F.R. § 42.103)
`The undersigned representative of Petitioners authorizes the Board to charge
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`the $15,500 Petition Fee, as well as any additional fees, to Deposit Account 501432,
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`ref: 178774-680003. Five claims are being reviewed, so $15,000 in post institution
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`fees are due for a total of $30,500.
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`III. Grounds for Standing Pursuant to 37 C.F.R. § 104(a)
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`Petitioners certify that the ’196 Patent is available for inter partes review, and
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`that Petitioners are not barred or estopped from requesting inter partes review of the
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`Challenged Claims on the grounds identified in this Petition. Apple filed and served
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`its first amended answer and counterclaims in the ’1375 Case, first asserting
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`infringement of the ’196 Patent by Petitioners, on November 29, 2017. ’1375 Case,
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`ECF No. 97. This petition is being filed within one year of service of Apple’s first
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`amended answer and counterclaims, and shortly after the District Court issued a claim
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`construction order adopting certain of Apple’s positions regarding the breadth of the
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`’196 Patent’s claims.
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`IV. Statement of Precise Relief Requested for Each Challenged Claim
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`37 C.F.R. § 42.104(b)(1): Claims for Which Review Is Requested
`Petitioners request review and cancellation of claims 1, 2, 3, 7 and 8 of the ’196
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`Patent (the “Challenged Claims”).
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`37 C.F.R. § 42.104(b)(2): Statutory Grounds and Prior Art on
`Which the Challenge is Based
`Petitioners request inter partes review of the Challenged Claims on the grounds
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`set forth below and request that each of the Challenged Claims be found unpatentable
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`and cancelled. An explanation of how the Challenged Claims are unpatentable is
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`provided in the form of the detailed description that follows, indicating where each of
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`the claim elements can be found in the prior art. Additional explanation and support
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`for each ground of rejection is set forth in Ex. 1002 (Declaration of Vijay K. Madisetti,
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`Ph.D.), referenced throughout this Petition.
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`Ground
`Ground 1
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`Ground 2
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`Ground 3
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`’196 Patent Claims
`1–3, 7 –8
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`1–3, 7 –8
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`1–3, 7 –8
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`Basis for Rejection
`35 U.S.C. § 102 based on U.S. Patent Pub. No.
`US Patent Pub. No. 2007/0043965 to
`Mandelblat (“Mandelblat”)
`35 U.S.C. § 103(a) based on Mandelblat in view
`of U.S. Patent No. 7,363,523 (“Kurts”)
`35 U.S.C. § 103(a) based on Kurts in view of
`U.S. Patent No. 7,369,815 (“Kang”)
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`The ’196 Patent issued February 18, 2014 from U.S. Application No.
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`13/863,554, which claimed priority to the application filed on April 7, 2010 that
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`matured into U.S. Patent No. 8,271,812. Accordingly, the earliest date to which the
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`’196 Patent could claim priority (hereinafter the “earliest effective filing date”) is
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`April 7, 2010.
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`Mandelblat was filed August 22, 2005, published February 22, 2007, and is
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`prior art under pre-AIA 35 U.S.C. §§ 102(a), (b), and (e).
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`Kurts was filed August 31, 2004, issued April 22, 2008, and is prior art under
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`pre-AIA 35 U.S.C. §§ 102(a), (b), and (e).
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`Kang was filed February 24, 2004 and issued May 6, 2008, and is prior art
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`under 35 U.S.C. § 102(a), (b), and (e).
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`V. Reasons for the Relief Requested Under 37 C.F.R. §§ 42.22(a)(2) and
`42.104(b)(4)
` Overview of the ’196 Patent and its Technology
`The ’196 Patent is related to transitioning the performance states of
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`performance domains and their components in response to a processor’s going to sleep
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`or waking up. Id. at Abstract, 1:37–62. Power management is performed using a
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`programmable power management unit (“PMU”).
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`Figure 1, reproduced below, discloses “an integrated circuit (IC) 10” that
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`includes performance domains. Id. at 3:34–38.
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`In Figure 1, “[t]he integrated circuit 10 includes a set of performance domains
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`14A-14F. Each performance domain 14A-14F includes at least one component of the
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`integrated circuit 10, and a given performance domain may include more than one
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`component.” Id. at 3:37–41. Further, certain performance domains may have specific
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`functionality and associated components. Id. at 3:46–52.
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`“The integrated circuit 10 also includes a power management unit (PMU)
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`28 . . . .” Ex. 1001, 3:52–53. “The PMU 28 may be configured to control transitions
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`between performance states for the various performance domains 14A-14F.” Id. at
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`4:1–5. The PMU 28 may transition the performance states of one or more of the
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`performance domains 14A–14F in response to a processor either “entering a sleep
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`state” and going to sleep, or “exiting the sleep state” and “waking” up. Id. at 4:3–12.
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`“In one embodiment, the PMU 28 may detect that the processor 16A-16B is
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`entering/exiting the sleep state, and may cause corresponding transitions in the
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`performance domains.” Ex. 1001, 5:51–54.
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`“A performance domain may be one or more components that may be
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`controlled by the PMU 28 as a unit for performance configuration purposes.” Ex.
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`1001, 4:19–21. “[T]he PMU 28 may be configured to establish a corresponding
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`performance state for each performance domain.” Ex. 1001, 4:21–23. “The
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`performance state may include any combination of performance characteristics for the
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`components in a corresponding performance domain.” Id. at 4:36–38. “A
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`performance characteristic may be any configurable setting for a component that
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`affects the performance of that component.” Id. at 4:38–43. For example, a
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`component’s clock frequency or supply voltage level may be a performance
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`characteristic of that component. Id. at 4:40–43. When the clock frequency or
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`operating voltage is changed, power consumption and the performance state of the
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`domain also changes. Id. at 5:1–4. “In the case of voltage and clock frequency
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`changes, the PMU 28 may communicate the new settings to the clock/voltage control
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`unit 32.” Id. at 5:64–66. The ’196 Patent discloses other characteristics that qualify
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`as a performance characteristic, id. at 4:40–67, 5:4–23, including memory size, id. at
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`4:45–47.
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`The PMU may include “one or more performance configuration registers 30.”
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`Ex. 1001, 3:53–54, Fig. 1 (PMU 28 including “Perf Config” registers). These registers
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`specify the performance states of different performance domains based upon the
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`“awake” and “sleep” states of a processor. “For example, performance states to be
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`used in the performance domains 14A–14F when the processor is in sleep state may
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`be specified in the performance configuration registers 30. Performance states to be
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`used when the processor 16A–16B exits the sleep state (awakens) may also be
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`specified” Ex. 1001, 5:57–62. One embodiment of the PMU’s performance
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`configuration registers is shown in Figure 2. See Ex. 1001, 7:43–9:29. In Figure 2,
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`“[t]he register set 30B may include a configuration for each performance domain, and
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`for the sleep state and the wake state.” Ex. 1001, 7:46–48.
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`Figure 3 is “a flowchart . . . illustrating operation of one embodiment of the
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`PMU 28 and the clock/voltage control unit 32 to manage performance state transitions
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`in performance domains when a processor is entering or exiting a sleep state.” Ex.
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`1001, 9:30–34. As shown, when “[t]he PMU 28 . . . detect[s] that the processor is
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`entering (or is about to enter) the sleep state” (block 40), it will “load the sleep
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`performance state for each performance domain from the performance configuration
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`registers 30 (block 42).” Id. at 9:44–53. Those performance domains will then
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`“transition . . . to the new performance states (block 44).” Id. at 9:61–64. Similarly,
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`“[t]he PMU 28 may [also] detect that a processor is exiting the sleep state ( or is about
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`to exit the sleep state)” (block 48), after which it will “load the wake performance
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`state for each performance domain from the performance configuration registers 30
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`(block 50).” Ex. 1001, 10:18–25. Those performance domains will then
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`“transition . . . to the new performance states (block 52).” Ex. 1001, 10:28–30.
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`Each of the above features was known in the art as of April 2010, the priority
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`date of the ’196 Patent. See Ex. 1002, ¶¶ 54–58.
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`The Prosecution History of the ’812 Patent to Which the ’196
`Patent Claims Priority
`As filed, Application No. 12/756,006 (“the ’006 Application”) included claims
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`1–20. Independent claim 12 (eventually issued as claim 8) recited an “apparatus”
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`comprising: “a plurality of components, each component included in one of a plurality
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`of performance domains”; and “a power management unit configured to establish a
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`performance state in each of the plurality of performance domains,” and “configured
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`to transition at least a first performance domain … to a first performance state
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`programmed into the power management unit responsive to a processor transitioning
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`to a different performance state.” Ex. 1007, p. 39. Dependent claim 14 depended
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`from original claim 12, and further recited that “the power management unit is
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`configured to transition each of the performance domains into a respective power state
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`programmed into the power management unit responsive to the processor
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`transitioning to the different performance state.” Id. at 40. Dependent claim 15
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`depended from claim 12, and recited that “the different performance state comprises
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`a wakeup state, wherein the processor is transitioning from a sleep state.” Id. at 40.
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`Dependent claim 16 depended from claim 15, and further recited that “the different
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`performance state is different from a prior performance state at which the processor
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`was operating prior to entering the sleep state.” Id. at 40.
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`On February 24, 2012, the Examiner rejected, among others, claims 12 and 14
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`“under [pre-AIA] 35 U.S.C. 102(b) as being anticipated by Kang et al., US Patent
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`Appl. Pub. No. 2005/0064829.” Id. at 52 (citing Ex. 1015, “Kang Application”). The
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`Examiner stated that the Kang Application included “a power management unit
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`(power control unit 140)” configured to transition “each of the performance domains
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`into a respective power state programmed into the power management unit” in
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`response to a processor’s “entry into sleep or exit to wake mode.” Id. at 53 (rejecting
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`claims 12 and 14). The Examiner only objected to dependent claim 16, finding it
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`“would be allowable if rewritten in independent form … .” Id. at 59.
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`On May 16, 2012, the Applicants responded by amending the power
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`management unit of claim 12 as follows:
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`Id. at 114. Applicants stated, “[c]laim 12 has been amended to include the features of
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`claims 15 and 16, and thus is in condition for allowance.” Id. at 117. Original claim
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`12, as amended, was allowed and issued as claim 8. Id. at 127.
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` The Prosecution History of the Parent ’216 Patent
`On August 21, 2012, the Applicants filed Application No. 13/590,217 (“the
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`’217 Application”) as a continuation of the application that issued as U.S. Patent No.
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`8,271,812. Ex. 1016, p. 19.
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`On November 19, 2012, the Examiner allowed claims 1–14. Id. at 58. Claims
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`15–24 were rejected for nonstatutory obviousness double patenting, and claims 20–
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`24 were rejected under 35 U.S.C. § 101. Id. The Examiner did not otherwise reject
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`any claim as anticipated or obvious in view of prior art. Id.
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`On February 4, 2013, Apple filed a Terminal Disclaimer to overcome the
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`double patenting rejection, and amended claims 20–24 to overcome the § 101
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`rejection. Id. at 80, 87.
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`On February 25, 2013, the Examiner allowed the pending claims. Id. at 101.
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`The Prosecution History of the ’196 Patent
`On April 16, 2013, the Applicants filed Application No. 13/863,554 (“the ’554
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`Application”) as a continuation of the application that issued as the ’216 Patent. Ex.
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`1017, p. 44. The ’554 Application originally included claims 1–19.
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`On July 2, 2013, the Examiner allowed claims 1–14. Id. at 53. The applicant
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`withdrew claims 15–19 in response to a restriction requirement. Id.
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`On September 26, 2013, the application was amended to add six new claims.
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`Id. at 69.
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`On October 11, 2013, without ever issuing any prior art rejections under 35
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`U.S.C. §§ 102 or 103, the Examiner allowed all pending claims. Id. at 87.
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`37 C.F.R. § 42.104(b)(3): Claim Construction
`1.
`A Person of Ordinary Skill in the Art
`A person of ordinary skill in the art (“POSITA”) as of April 7, 2010 would have
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`had a bachelor’s degree in electrical engineering or computer engineering and at least
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`two years of experience in the field of integrated circuit design or an equivalent
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`combination of education, work, and/or experience in this field. Ex. 1002 ¶ 22.
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`2.
`Construction of Claim Terms
`The claims of the ’196 Patent “shall be given the broadest reasonable
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`construction in light of the [’196 Patent’s] specification.” 37 C.F.R. § 42.100(b).
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`Because a district court applies a different standard, the claim constructions presented
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`in this petition do not necessarily reflect the constructions that Petitioners believe
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`should be adopted by a district court.
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`In the ’1375 Case, the District Court adopted certain of Apple’s claim
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`construction positions. Ex. 1013, pp. 8–9. Petitioners have submitted the District
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`Court’s claim construction decision for the Board’s consideration. Power
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`Integrations, Inc. v. Lee, 797 F.3d 1318, 1326–27 (Fed. Cir. 2015) (“The fact that the
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`board is not generally bound by a previous judicial interpretation of a disputed claim
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`term does not mean, however, that it has no obligation to acknowledge that
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`interpretation or to assess whether it is consistent with the broadest reasonable
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`construction of the term.”). Although Petitioners reserve the right to appeal or
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`otherwise challenge the District Court’s claim construction order, Petitioners request
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`that the Board in this IPR construe any claim terms at least as broad as the District
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`Court. See, e.g., Cisco Systems, Inc. v. Crossroads Systems, Inc., IPR2014-01463,
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`Final Written Decision, Paper 49 at 11–12 (PTAB, Mar. 16, 2016).
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`(a)
`“performance domain”
`Apple construed “performance domain” to mean “one or more components that
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`may be controlled as a unit or independently for performance configuration purposes.”
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`Ex. 1008, pp. 17–19; Ex. 1009, pp. 6–7; Ex. 1010, pp. 105–110; Ex. 1011 ¶¶ 25–30;
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`Ex. 1012, pp. 41–44, 69–105, 122–129. In particular, Apple argued that components
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`within the claimed “performance domain” can be controlled “independently” by the
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`power management unit (“PMU”) and do not have to transition together from one
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`performance state to another. Ex. 1008, pp. 14–19; Ex. 1009, pp. 6–7; Ex. 1010, pp.
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`104–108; Ex. 1011 ¶¶ 25–28; Ex. 1012, pp. 69–90, 137.
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`The District Court adopted Apple’s construction. Ex. 1013, p. 8. Apple’s
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`construction, as argued to the District Court, should be adopted in this proceeding.
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`(b)
`“power management unit”
`Apple proposed that “power management unit” does not require construction,
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`but that a PMU is any “hardware and/or software that causes a performance domain
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`to transition to a performance state.” Ex. 1008, pp. 19–22; Ex. 1009, pp. 7–9; Ex.
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`1010, pp. 128–135, 144–145, 159; Ex. 1011 ¶¶ 31–37; Ex. 1012, pp. 56–67, 110–135.
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`In particular, Apple argued that a PMU need not be implemented only in hardware.
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`Id. The District Court ultimately construed PMU to be hardware or the combination
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`of hardware and software. Ex. 1013, pp. 8–9. Apple’s construction, as argued to the
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`District Court, should be adopted in this proceeding.
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`(c)
`“establish a . . . performance state”
`Apple proposed that “establish a … performance state” does not require
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`construction or, if construed, should mean “set the . . . one or more performance
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`characteristics to the appropriate values for the performance state.” Ex. 1008, pp. 22–
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`23; Ex. 1009, pp. 9–10; Ex. 1010, pp. 146–149; Ex. 1011 ¶¶ 38–42; Ex. 1012, pp.
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`123–144. In particular, Apple argued that a performance domain need not actually
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`transition from one performance state to another in order for the PMU to “establish
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`a . . . performance state” of that domain. Id. The District Court concluded: (i) that
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`“the word ‘establish’ is . . . consistent with Apple’s use of ‘set,’” (ii) that “the explicit
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`requirement that the PMU be configured to make this transition is separate from the
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`‘establish’ requirement, and (iii) that the term should be construed “according to its
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`plain and ordinary meaning.” Ex. 1013, p. 9. Apple’s construction, as argued to the
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`District Court, should be adopted in this proceeding.
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` Overview of the Prior Art
`(a) Mandelblat
`US Patent Pub. No. 2007/0043965 (“Mandelblat”) is titled “Dynamic memory
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`sizing for power reduction.” Ex. 1003. Mandelblat “relates to integrated circuits
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`and/or computing systems,” including to “power management of memory circuits.”
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`Id. at ¶ 2.
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`Like the ’196 Patent, Mandelblat is directed to the reduction in power
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`consumption in microprocessors. Id. at ¶¶ 4–5, 17. Mandelblat discloses a
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`microprocessor containing multiple processor cores (902, 904), Power Management
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`Logic (PML) (906), containing a “Memory PML” (907), and a Dynamically Sizeable
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`Memory (905).
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`In the Dynamically Sizeable Memory, certain memory cells may be selectively
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`enabled or disabled for purposes of power savings. Id. ¶¶ 17–18. These memory cells
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`are enabled/disabled by way of “sleep devices” that selectively couple/decouple the
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`memory cells to/from their power source. Id. ¶¶ 18–19, Figs. 1–2. The “sleep
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`devices” are controlled by the PML, specifically the Memory PML. Id. Cache size
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`is directly related to power usage—a larger cache uses more power, a smaller cache
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`uses less.
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`Mandelblat’s Dynamically Sizeable Memory may be at a Minimum Cache size,
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`a maximum or Full Cache size, or at some point in between, and may expand or shrink
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`between these sizes. Id. ¶¶ 38, Fig. 12. In this way, the Dynamically Sizeable
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`Memory may be sized based on processor power state, usage, or other factors. Id.
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`¶ 65.
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`-17-
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`Of importance is Mandelblat’s disclosure of cache expansion and contraction
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`operations upon cores entering or exiting the C4 state, which is a sleep state.1 Id. at
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`¶¶ 53, 58, Fig. 12. As cores enter the C4 state, the Dynamically Sizeable Memory
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`shrinks from the Full Cache size to no less than a pre-set “Minimum Cache Size.” Id.
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`at ¶¶ 47–48. This process may be completed for each core until all cores have entered
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`the C4 state and processor as a whole enters the C4 state. Id. at ¶ 50. The cache
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`maintains this Minimum Cache size while the cores are in C4. Id.
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`Upon waking up and exiting the C4 state, Mandelblat discloses that the
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`Dynamically Sizeable Memory may initiate an expand operation responsive to the
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`“one or more of the core(s) transitioning to a different power state.” Id. at ¶¶ 52.
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`1 Mandelblat discloses one embodiment that “includes features and functionality
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`according to the Advanced Configuration and Power Interface (ACPI) Standard.”
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`Ex. 1003, ¶ 34 (referencing ACPI Specification, Rev. 3.0, Sep. 2, 2004 (Ex.
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`1014)). The ACPI Standard specifies power management performance “C states”
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`that may be supported by a processor and its cores. Ex. 1002, ¶ 45. “The C0
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`power state is an active power state where the CPU executes instructions. The C1
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`through Cn power states are processor sleeping states where the processor
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`consumes less power and dissipates less heat than leaving the processor in the C0
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`state.” Ex. 1014 § 8.1; see also id. §§ 2.5, 8; Ex. 1004 (“Kurts”), 1:18–33.
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`-18-
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`Mandelblat further discloses this expansion may be to a revised Minimum Cache size
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`rather than the Full Cache size. Id. at ¶ 58.
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`(b) Kurts
`U.S. Patent No. 7,363,523 (“Kurts”) is titled “Method and apparatus for
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`controlling power management state transitions.” Ex. 1004. Similar to the ’196
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`Patent, Kurts states the objective of power state management in computing devices,
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`including reducing “entry/exit latencies” that may prevent processors from entering
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`deeper sleep and conserving power. Id. at 1:46–2:5.
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`Kurts discloses a processor (205) with cores and an execution unit (210), and
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`Power Management Logic (234) to manage the performance state of the processor,
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`including frequency/voltage levels. Id. at 3:25–44. Within the Power Management
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`Logic is a Voltage ID Table (“VID Table”) (277). Id. at 4:13, 4:20–35. The VID
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`table is a lookup table for voltage/frequency pairs corresponding to various operating
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`points of the processor. The Power Management Logic (234) uses the values in this
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`VID Table to exert control over the processor’s clock generator (211) and voltage
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`regulator (212), thereby controlling the processor’s voltage and frequency. Id. at
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`3:25–33, 4:20–35, Fig. 3.
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`In addition to the Power Management Logic (234), Deeper Sleep Logic (270)
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`controls the processor’s entry into and exit from a deeper sleep state, referred to as
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`C4. Id. at 3:64–4:2. Power Management State Control Logic (242) controls the
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`processor’s power state, or C-state, placing it into various power states, referred to,
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`from most active to deepest sleep as C0, C1, C2, C3, and C4. Id. at 1:15–33, 4:49–
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`63. Working together, the Power Management Logic, the Deeper Sleep Logic, and
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`the Power Management State Control Logic control the performance state of the
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`processor. Id. at 3:63–4:2, 6:30–45, 7:6–43, 11:46–56. The processor enters these
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`low power, or sleep states, C2 through C4 to conserve power and reduce thermal load
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`when the processor is not needed. Id. at 5:43–6:45. For example, in C2, portions of
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`the processor circuitry may be powered down and clocks may be gated to reduce
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`power consumption. Id. at 6:3–8. Kurts further explains that a processor may enter a
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`Low Frequency Mode (LFM), in which the processor transitions to “the minimum or
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`another low operating frequency,” such as the lowest frequency in the VID table. Id.
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`at 6:30–45.
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`Kurts addresses the problem of how to quickly exit a deep sleep to address
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`events such as cache snoops or interrupts, as coming out of a deep sleep state,
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`including the increase of the processor’s operating frequency can be prohibitively
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`slow. Id. at 1:55–2:5. Kurts teaches that the processor may be awakened, and placed
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`into an active C0 state while remaining in Low Frequency Mode. Id. at 6:46–7:20,
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`Fig. 1. This allows the processor to handle an interrupt, and then proceed to either
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`revert back to its pre-sleep frequency and voltage, or to return to a sleep state. Id.
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`(c) Kang
`U.S. Patent No. 7,369,815 (“Kang”) is titled “Power Collapse for a Wireless
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`Terminal.” Ex. 1006. Application No. 10/786,585, which resulted in the Kang Patent,
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`and was published as U.S. 2005/0064829 on March 24, 2005, formed part of the basis
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`for the examiner’s initial rejection of the application that resulted in the ’812 Patent.
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`Ex. 1007, p. 52.
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`Kang states the objective of conserving power. Ex. 1006, 1:11–14. Kang
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`describes a processor (120) partitioned into “power domains” containing various
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`processing units including memory (134), a core (130), a controller (132), phase
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`locked loops (135), and a power control unit (140). Id. at 3:38–56, Figs. 1, 2A.
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`Kang describes “collapsible” power domains—domains that may be powered
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`off if the processing units within them are not needed, as well as “always on” power
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`domains, which never power down. Id. at 4:37–49. Each of these collapsible power
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`-22-
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`domains “may be powered down if the processing units in the power domain are not
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`needed.” Id. Further, each domain “may be powered on or off independently of the
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`other collapsible power domains.” Id.
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`Kang discloses a “power control unit” (140) that controls the power for each
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`collapsible power domain. The power control unit is in the always on domain. Id. at
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`3:54–56. Kang’s power control unit contains “various circuit blocks that support
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`powering on and off the collapsible power domains,” including state registers (242)
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`for storing the power status of the power domains and hardware states (6:14–17); a
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`sleep controller (246) for monitoring and controlling the processor’s sleep state (6:18–
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`34), a clock controller (248) for enabling/disabling the processor’s main clock (6:35–
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`36), an interrupt controller (250) that monitors for external interrupts (6:37–38), and
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`power controller (252) that generates the control signals to power up/down the
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`collapsible power domains (6:44–60).
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`Figures 4, 5A, and 5B and Table 1 of Kang describe exemplary sequences for
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`powering up and powering down collapsible power domains. Id. at 6:7–28, 8:26–
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`9:28, Figs. 4, 5A, 5B. The power control unit (140) manages these tasks for both
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`powering up and powering down the collapsible power domains.
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`37 C.F.R. § 42.104(b)(4): How the Construed Claims are
`Unpatentable
`An explanation of how claims 1–3, and 7–8 are unpatentable, including
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`identification of how each claim feature is found in the prior art, is set forth below in
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`Section VI.
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`37 C.F.R. § 42.104(b)(5): Supporting Evidence
`An Appendix of Exhibits supporting this Petition is attached. Included at
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`Exhibit 1002 is a Declaration of Vijay K. Madisetti, Ph.D. under 37 C.F.R. § 1.68,
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`which includes detailed claim charts comparing the Challenged Claims to the prior
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`-24-
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`art.2 In addition, the relevance of the evidence to the Challenged Claims, including
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`an identification of the specific portions of the evidence supporting the challenge, is
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`included in Section VI.
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`VI. Claims 1, 2, 3, 7 and 8 of the ’196 Patent Are Unpatentable
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`Pursuant to Rule 42.104(b)(4)–(5), the following analysis and evidence
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`demonstrates where each element of the Challenged Claims is found in the prior art
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`for each of the grounds listed above.
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`’196 Claim 1
`a. Preamble
`b. First Element
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`b. Second Element, Part 1
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`d. Second Element, Part 2
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`e. Second Element, Part 3
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`’196 Claim Language
`“An apparatus comprising”
`“a plurality of components, each component
`included in one of a plurality of performance
`domains;”
`“a power management unit comprising a plurality
`of configuration registers, wherein the plurality of
`configuration registers are programmed with data
`identifying performance states for the plurality of
`performance domains”
`“wherein at least two performance states are
`identified for each performance domain of the
`plurality of performance domains, and”
`“wherein the power management unit is
`configured to establish a selected performance
`state of the at least two performance states in each
`of the plurality of performance domains
`responsive to an event that is asynchronous to the
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`
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