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`"Express Mail" Mailing Label No. EV 718871452 US
`
`PATENT APPLICATION
`Attorney Docket No. APL-P2766-C2
`
`IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`UTILITY PATENT
`APPLICATION TRANSMITTAL LETTER
`
`Asst. Commissioner for Patents
`Box Patent Application
`PO Box i450
`Alexandria, VA 22313-1450
`
`Sir:
`
`Enclosed for filing is a continuation patent application of U.S. Patent Application Serial No.
`
`11/103,911, filed 11 April 2005, of Group Art Unit 2116, Examiner Stefan Stoynov, by inventor Lynn
`
`Youngs, entitled, "CONSERVING POWER BY REDUCING VOLTAGE SUPPLIED TO AN
`
`INSTRUCTION-PROCESSING PORTION OF A PROCESSOR". Enclosed is a true copy of serial
`
`number 11/103,911 as originally filed.
`
`No. of pages in Specification: ,li_; No. of Claims: 21 (after considering preliminary amendment).
`Formal: _x.
`
`No. of Sheets of Drawings: _l__;
`
`Informal:_
`
`Also enclosed are:
`
`[X]
`
`[X]
`
`[X]
`
`[ ]
`
`[X]
`
`[X]
`
`[X]
`
`a Preliminary Amendment;
`
`a Recordation cover sheet, an assignment document and form PTO-1595 from a prior
`
`application;
`
`a Declaration of the inventors(s) from a prior application under 37 C.F .R § 1.63(d);
`
`a Power of Attorney and Correspondence Address Form and form PTO/SB 96 from a
`
`prior application;
`
`a filing receipt from a prior application; and
`
`a Return Post Card.
`
`an Information Disclosure Statement with four references
`
`1
`
`Qualcomm, Ex. 1007, Page 1
`
`

`

`•
`
`'t
`
`The fee has been calculated as follows (after considering preliminary amendment):
`.. ••. ,'<
`.
`.
`· .
`
`.:_:.,:•
`
`i
`
`:••
`
`NO.OF
`CLAIMS
`
`.,
`
`'
`. ,.' CLAIMS
`.,.
`'. .\i:t:
`
`'
`
`FEE
`
`$1,000.00
`
`$100.00
`
`$0.00
`
`0
`
`$1,100.00
`
`$0.00
`
`$1,100.00
`
`:,
`1~: ....
`Basic Filing Fee ($300.00), Search Fee ($500.00) and Examination Fee ($200.00)
`
`EXTRA
`CLAIMS
`
`RATE
`
`Total Claims
`
`Independent
`Claims
`
`22
`
`3
`
`MINUS 20
`=
`
`MINUS 3 =
`
`2
`
`0
`
`$50.00=
`
`$200.00=
`
`If multiple dependent claims are presented, add $300.00
`
`Total Application Fee
`
`If verified statement claiming small entity status is enclosed, subtract 50% of
`Total Aoolication Fee
`
`Add Recording Fee of$40.00 if Assignment document is enclosed
`
`TOTAL APPLICATION FEE DUE
`
`[X]
`D
`
`A check in the amount of$ 1,100.00 is enclosed.
`
`Application fee will follow with missing parts.
`
`Please direct all correspondence concerning the above-identified application to the following
`address:
`
`A. Richard Park
`PARK & VAUGHAN LLP
`2820 Fifth Street
`Davis, CA 95616
`Tel: (530) 759-1661
`
`I IIIIII IIIII IIIII IIIII IIIII IIII IIII
`22835
`
`PATENT TRADEMARK OFFICE
`
`Respectfully submitted,
`
`By
`
`A. Richard Park
`Registration No. 41,241
`
`Date: 25 August 2005
`
`2
`
`Qualcomm, Ex. 1007, Page 2
`
`

`

`"Express Mail" Mailing Label No. EV003896431 US
`
`PATENT APPLICATION
`ATTORNEY DOCKET NO. APL-P2766
`
`CONSERVING POWER BY REDUCING
`VOLT AGE SUPPLIED TO AN INSTRUCTION(cid:173)
`
`PROCESSING PORTION OF A PROCESSOR
`
`Inventor: Lynn R. Youngs
`
`BACKGROUND
`
`5
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`10
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`15
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`20
`
`Field of the Invention
`
`[0001] The present invention relates to techniques for conserving power
`
`usage in computer systems. More specifically, the present invention relates to a
`
`method and an apparatus for reducing power consumption in a processor by
`
`reducing voltage supplied to an instruction-processing portion of the processor,
`
`while maintaining voltage to other portions of the processor.
`
`Related Art
`
`[0002) Dramatic advances in integrated circuit technology have led to
`
`30
`
`corresponding increases in processor clock speeds. Unfortunately, these increases
`
`Attorney Docket No. APL-P2766
`EJG W:\APPLE COMPUTER\APL-P:!766\APL-P2766 APPLICATION.DOC
`
`Inventor: Youngs
`
`Qualcomm, Ex. 1007, Page 3
`
`

`

`in processor clock speeds have been accompanied by increased power
`
`consumption. Increased power consumption is undesirable, particularly in
`
`battery-operated devices such as laptop computers, for which there exists a limited
`
`supply of power. Any increase in power consumption decreases the battery life of
`
`5
`
`the computing device.
`
`[0003] Modem processors are typically fabricated using Complementary
`
`Metal Oxide Semicon~uctor (CMOS) circuits. CMOS circuits typically consume
`
`more power while the circuits are switching, and less power while the circuits are
`
`idle. Designers have taken advantage of this fact by reducing the frequency of ( or
`
`10
`
`halting) clock signals to certain portions of a processor when the processor is idle.
`
`Note that some portions of the processor must remain active, however. For
`
`example, a cache memory with its associated snoop circuitry will typically remain
`
`active, as well as interrupt circuitry and real-time clock circuitry.
`(0004] Although reducing the frequency of (or halting) a system clock
`signal can reduce the dynamic power consumption of a processor, static power
`
`15
`
`consumption is not significantly affected. This static power consumption is
`primarily caused by leakage currents through the CMOS devices. As integration
`
`densities of integrated circuits continue to increase, circuit devices are becoming
`
`progressively smaller. This tends to increase leakage current.s, and thereby
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`20
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`increases static power consumption. This increased static power consumption
`
`results in reduced battery life, and increases cooling system requirements for
`
`battery operated computing devices.
`
`[0005] What is needed is a method and an apparatus that reduces static
`power consumption for a processor in a battery operated computing device.
`
`25
`
`Attorney Docket No. APL-P2766
`EJG W \APPLE COMPUTER\APL-P'.;766\APL-P2766 APPLICATION.DOC
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`Inventor: Youngs
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`2
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`Qualcomm, Ex. 1007, Page 4
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`

`

`SUMMARY
`
`[0006] One embodiment of the present invention provides a system that
`
`facilitates reducing static power consumption of a processor. During operation,
`
`the system receives a signal indicating that instruction execution within the
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`5
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`processor is to be temporarily halted. In response to this signal, the system halts
`
`an instruction-processing portion of the processor, and reduces the voltage
`
`supplied to the instruction-processing portion of the processor. Full voltage is
`
`maintained to a remaining portion of the processor, so that the remaining portion
`
`of the processor can-continue to operate while the instruction-processing portion
`
`IO
`
`of the processor is in reduced power mode.
`
`[0007] In one embodiment of the present invention, reducing the voltage
`
`supplied to the instruction-processing portion of the processor involves reducing
`
`the voltage to a minimum value that maintains state information within the
`
`instruction-processing portion of the processor.
`
`15
`
`(0008] In one embodiment of the present invention, reducing the voltage
`
`supplied to the instruction-processing portion of the processor involves reducing
`
`the voltage to zero.
`
`[0009] In one embodiment of the present invention, the system saves state
`
`information from the instruction-processing portion of the processor prior to
`
`20
`
`reducing the voltage supplied to the instruction-processing portion of the
`
`processor. This state information can either be saved in the remaining portion of
`
`the processor or to the main memory of the computer system.
`
`[0010] In one embodiment of the present invention, upon receiving a
`
`wakeup signal, the system: restores full voltage to the instruction-processing
`
`25
`
`portion of the processor; restores state information to the instruction-processing
`
`portion of the processor; and resumes processing of computer instructions.
`
`Attorney Docket No. APL-P2766
`
`Inventor: Youngs
`
`EJG W:\APPLE COMPUTERIAPL-P!766\APL-P2766 APPLICATION.DOC
`
`"' .,
`
`Qualcomm, Ex. 1007, Page 5
`
`

`

`5
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`10
`
`15
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`20
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`25
`
`[0011] In one embodiment of the present invention, maintaining full
`voltage to the remaining portion of the processor involves maintaining full voltage
`to a snoop-logic portion of the processor, so that the processor can continue to
`perform cache snooping operations while the instruction-processing portion of the
`processor is in the reduced power mode.
`[0012) In one embodiment of the present invention, the system also
`reduces the voltage to a cache memory portion of the processor. In this
`embodiment, the system writes cache memory data to main memory prior to
`reducing the voltage.
`
`[0013] In one embodiment of the present invention, the remaining portion
`of the processor includes a control portion of the processor containing interrupt
`circuitry and clock circuitry.
`[0014] In one embodiment of the present invention, the remaining portion
`of the processor includes a cache memory portion of the processor.
`
`BRIEF DESCRIPTION OF THE FIGURES
`[0015] FIG. IA illustrates different power areas within processor 102 in
`accordance with an embodiment of the present invention.
`[0016) FIG. 1B illustrates alternate power areas within processor 102 in
`accordance with an embodiment of the present invention.
`(0017) FIG. 2 is a flowchart illustrating the process of monitoring
`processor load and switching to power saving modes in accordance with an
`embodiment of the present invention.
`
`DETAILED DESCRIPTION
`(0018] The following description is presented to enable any person skilled
`in the art to make and use the invention, and is provided in the context of a
`
`Attorney Docket No. APL-P2766
`EJG W\APPLE COMPUTER\APL-P2766\APL-P2766 APPLICATION.DOC
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`Inventor: Youngs
`
`4
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`Qualcomm, Ex. 1007, Page 6
`
`

`

`particular application and its requirements. Various modifications to the disclosed
`
`embodiments will be readily apparent to those skilled in the art, and the general
`
`principles defined herein may be applied to other embodiments and applications
`
`without departing from the spirit and scope of the present invention. Thus, the
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`5
`
`present invention is not intended to be limited to the embodiments shown, but is
`
`to be accorded the widest scope consistent with the principles and features
`
`disclosed herein.
`
`Processor 102
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`10
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`(0019) FIG. IA illustrates different power areas within processor 102 in
`
`accordance with an embodiment of the present invention. Processor 102 is
`
`divided into a core power area 126, and a non-core power area 124. Core power
`
`area 126 includes the instruction-processing portion of processor 102.
`
`Specifically, core power area 126 includes arithmetic-logic unit 104, register
`
`15
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`files l 06, pipelines l 08, and possibly level one (Ll) caches 110. Note that L 1
`
`caches 110 can alternatively be located in non-core power area 124.
`
`[0020] Arithmetic-logic unit 104 provides computational and logical
`
`operations for processor 102. Register files 106 provide source operands,
`
`intem1ediate storage, and destination locations for instructions being executed by
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`20
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`arithmetic-logic unit 104. Pipelines 108 provides a steady stream of instructions
`
`to arithmetic-logic unit 104. Instructions in pipelines 108 are decoded in transit.
`
`Therefore, pipelines 108 may contain instructions in various stages of decoding
`
`and execution. L l caches 110 include data caches and instruction caches for
`
`arithmetic-logic unit 104. L 1 caches 110 are comprised of very high-speed
`
`25 memory to provide fast access for instructions and data. In one embodiment of
`
`the present invention, L 1 caches 110 includes a write-through data cache.
`
`Attorney Docket No. APL-P2766
`
`Inventor: Youngs
`
`EJG W:IAPPLE COMPUTER\APL-P:?766\APL-?2766 APPLICA TlON.DOC
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`5
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`Qualcomm, Ex. 1007, Page 7
`
`

`

`[0021] Non-core power area 124 comprises the remaining portion of
`
`processor 102 and includes interrupt processor 112, real-time clock 114, clock
`
`distribution circuitry 116, level two (L2) caches 118, cache tags 120, and cache
`
`snoop circuitry 122. In general, non-core power area 124 includes portions of
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`5
`
`processor 102 that are not directly involved in processing instructions, and that
`
`need to operate while instruction processing is halted.
`
`[0022] Interrupt processor 112 monitors interrupts 128 and periodically
`
`interrupts the execution of applications to provide services to external devices
`
`requiring immediate attention. Interrupt processor 1 i 2 can aiso provide a wake-
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`10
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`up signal to core power area 126 as described below. Real-time clock 114
`
`provides time-of-day services to processor l 02. Typically, real-time clock 114 is
`
`set upon startup from a battery operated real-time clock in the computer and
`
`thereafter provides time to the system. Clock distribution circuitry 116 provides
`
`clock signals for processor 102. Distribution of these clock signals can be
`
`15
`
`switched off or reduced for various parts of processor 102. For example, clock
`
`distribution to core power area 126 can be stopped while the clock signals to non(cid:173)
`
`core power area 124 continue. The acts of starting and stopping of these clock
`
`signals are known in the art and will not be described further. Real-time
`
`clock 114 and clock distribution circuitry 116 receive clock signal 130 from the
`
`20
`
`computer system. Clock signal 130 is the master clock signal for the system.
`
`[0023] L2 cache 118 provides a second level cache for processor I 02.
`
`Typically, an L2 cache is larger and slower that an Ll cache, but still provides
`
`faster access to instructions and data than can be provided by main memory.
`
`Cache tags 120 provide an index into data stored in L2 cache 118. Cache snoop
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`25
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`circuitry 122 invalidates cache lines base primarily on other processors accessing
`
`their own cache lines, or I/0 devices doing memory transfers, even when
`
`instruction processing has been halted. L2 cache 118, cache tags 120, and cache
`
`Attorney Docket No. APL-P2766
`
`Inventor: Youngs
`
`EJG W \APPLE COMPUTER\APL-P'.!766\APL-P:!766 APPL!CA TION.DOC
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`6
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`Qualcomm, Ex. 1007, Page 8
`
`

`

`snoop circuitry 122 communicate with the computer system through memory
`signals 132.
`
`[0024] Non-core power area 124 receives non-core power 136 and core
`power area 126 receives core power 134. The voltage applied for non-core
`power 136 remains at a voltage that allows circuitry within non-core power
`area 124 to remain fully active at all times. In contrast, non-core power 13 6 may
`provide different voltages to non-core power area 124 based upon the operating
`mode of processor 102. For example, if processor l 02 is a laptop attached to
`externai eiectrical power, the voltage provided to non-core power 136 (and to core
`power 134 during instruction processing) may be higher than the minimum
`voltage, thus providing faster execution of programs.
`[0025] The voltage applied to core power 134 remains sufficiently high
`during instruction processing so that core power area 126 remains fully active.
`However, when processor 102 receives a signal that processing can be suspended,
`the voltage supplied by core power 134 can be reduced.
`(0026] In one embodiment of the present invention, the voltage in core
`power 134 is reduced to the minimum value that' will maintain state information
`within core power area 126, but this voltage is not sufficient to allow processing
`to continue. In another embodiment of the present invention, the voltage at core
`power 134 is reduced to zero. In this embodiment, the state of core power
`area 126 is first saved before the voltage is reduced to zero. This state can be
`saved in a dedicated portion of L2 cache l l 8, in main memory, or in another
`dedicated storage area. Upon receiving an interrupt or other signal indicating that
`processing is to resume, the voltage in core power 134 is restored to a normal
`level, saved state is restored, and processing is restarted.
`[0027] FIG. 1B illustrates an alternative partitioning of power areas within
`processor 102 in accordance with an embodiment of the present invention. As
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`25
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`Attorney Docket No. APL-P2766
`EJG W:\APPLE COMPUTER\APL-P'.!766\APL-P:!766 APPLICATION.DOC
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`Inventor: Youngs
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`7
`
`Qualcomm, Ex. 1007, Page 9
`
`

`

`shown in FIG. 1B, L2 cache 118, cache tags 120, and cache snoop circuitry 122
`are included in core power area 126 rather than in non-core power area 124. In
`this embodiment, the voltage supplied as core power 134 is reduced or set to zero
`as described above, however, the cache circuitry within processor 102 is also put
`into the reduced power mode. Prior to reducing the voltage supplied to core
`power area 126, data stored in L2 cache 118 is flushed to main memory.
`Additionally, if the voltage at core power 134 is reduced to zero, the state of
`processor 102 is first saved in main memory.
`
`5
`
`10 Monitoring and Switching
`
`15
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`20
`
`[0028] FIG. 2 is a flowchart illustrating the process of monitoring
`processor load and switching to power saving modes in accordance with an
`embodiment of the present invention. The system starts by monitoring the
`processor load (step 202). Next, the system determines if the processor will be
`needed soon (step 204). This determination is made based on the current
`execution pattern and the cost of entering and recovering from nap mode. This
`cost, calculated in power usage, must be less than the power wasted by not going
`into nap mode. If the processor will be needed soon at step 204, the process
`returns to step 202 to continue monitoring the processor load.
`[00291 If the processor will not be needed soon at step 204, the system
`determines if the processor has been taking long naps recently (step 206). If not,
`the system enters a normal nap mode, which involves halting the processor
`without reducing any voltages (step 208). Typically, halting the processor
`involves removing the clock signals to the core power area of the processor. After
`halting the processor, the system waits for an interrupt (step 210). Upon receiving
`an interrupt or other signal requiring a restart, the system restarts instruction
`
`Attorney Docket No. APL-P2766
`EJG W:\APPLE COMPUTER\APL-P:2766\APL-P:!766 APPLICATION.DOC
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`Inventor: Youngs
`
`8
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`Qualcomm, Ex. 1007, Page 10
`
`

`

`processing (step 212). After restarting instruction processing, the process returns
`
`to step 202 to continue monitoring the processor load.
`
`[0030] If the processor has recently been taking long naps at step 206, the
`system enters a deep nap mode, which involves saving the state information from
`
`5
`
`the core power area (step 214), halting the processor (step 216), and then
`
`reducing the voltage supplied to the core power area (step 218). After reducing
`
`the voltage, the system waits for an interrupt (step 220).
`
`(0031] Upon receiving the interrupt or other signal requiring a restart, the
`
`system restores the voltage to the core power area (step 222). Next, the modules
`10 within the core power area are restarted (step 224). The system then restores the
`state information that was saved at step 214 (step 226). After the processor has
`
`been restarted, the process returns to step 202 to continue monitoring the
`
`processor load. Note that the above description applies when the processor is
`used to save and restore the state information. In cases where dedicated hardware
`saves and restores the state information, steps 214 and 216, and steps 224 and 226
`can be reversed. Note also that if the voltage supplied to the core power area 126
`
`15
`
`is reduced but maintained at a level where modules in the core power do not lose
`
`state information, steps 216 and 224 are not required.
`
`[0032] The foregoing descriptions of embodiments of the present
`
`20
`
`invention have been presented for purposes of illustration and description only.
`
`They are not intended to be exhaustive or to limit the present invention to the
`forms disclosed. Accordingly, many modifications and variations will be apparent
`to practitioners skilled in the art. Additionally, the above disclosure is not
`
`intended to limit the present invention. The scope of the present invention is
`
`25
`
`defined by the appended claims.
`
`Attorney Docket No. APL-P2766
`EJG W \APPLE COMPUTER\APL-P'.!766\APL-P'.!766 APPLICATION.DOC
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`Inventor: Youngs
`
`9
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`Qualcomm, Ex. 1007, Page 11
`
`

`

`What Is Claimed Is:
`
`2
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`2
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`4
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`2
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`3
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`2
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`3
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`I.
`
`A method for reducing static power consumption of a processor,
`
`comprising:
`
`receiving a signal indicating that instruction execution within the
`
`processor is to be temporarily halted; and
`
`in response to the signal,
`
`halting an instruction-processing portion of the processor,
`
`and
`
`reducing a voltage supplied to the instruction-processing
`
`portion of the processor, while maintaining full voltage to a second
`
`portion of the processor;
`
`whereby the second portion of the processor can continue to operate while
`
`the instruction-processing portion of the processor is in a reduced power mode.
`
`2.
`
`The method of claim 1, wherein reducing the voltage supplied to
`
`the instruction-processing portion of the processor involves reducing the voltage
`
`to a minimum value that maintains state information within the instruction-
`
`processing portion of the processor.
`
`3.
`
`The method of claim 1, wherein reducing the voltage supplied to
`
`the instruction-processing portion of the processor involves reducing the voltage
`
`to zero.
`
`4.
`
`The method of claim 3, further comprising saving state information
`
`from the instruction-processing portion of the processor prior to reducing the
`
`voltage supplied to the instruction-processing portion of the processor, wherein
`
`Attorney Docket No. APL-P2766
`
`Inventor: Youngs
`
`EJG W:\APPLE COMPUTER\APL-P2766\APL-P2766 APPLICATION.DOC
`
`10
`
`Qualcomm, Ex. 1007, Page 12
`
`

`

`4
`
`5
`
`saving state information includes saving state information to one of, the second
`portion of the processor and a main memory.
`
`5.
`
`The method of claim 4, wherein upon receiving a wakeup signal
`the method further comprises:
`
`restoring full voltage to the instruction-processing portion of the
`processor;
`
`restoring state information to the instruction-processing portion of the
`processor; and
`
`resuming processing of computer instructions.
`
`6.
`
`The method of claim 1, wherein maintaining full voltage to the
`second portion of the processor involves maintaining full voltage to a snoop-logic
`portion of the processor, whereby the processor can continue to perform cache
`snooping operations while the instruction-processing portion of the processor is in
`the reduced power mode.
`
`7.
`
`The method of claim 1, further comprising reducing the voltage to
`a cache memory portion of the processor upon receiving the signal.
`
`8.
`
`The method of claim 7, further comprising writing cache memory
`data to main memory prior to reducing the voltage.
`
`9.
`
`The method of claim 1, wherein the second portion of the
`processor includes a control portion of the processor that includes interrupt and
`clock circuitry.
`
`2
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`3
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`6
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`2
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`2
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`2
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`3
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`Attorney Docket No. APL-P2766
`EJG W:IAPPLE COMPUTER\APL-P27661APL-P2766 APPLICATION.DOC
`
`Inventor: Youngs
`
`11
`
`Qualcomm, Ex. 1007, Page 13
`
`

`

`10.
`
`The method of claim 1, wherein the second portion of the
`
`2
`
`processor includes a cache memory portion of the processor.
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`2
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`3
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`4
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`IO
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`2
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`11.
`
`An apparatus, for reducing static power consumption of a
`
`processor, compnsmg:
`
`a receiving mechanism that is configured to receive a signal indicating that
`
`instruction execution within the processor is to be temporarily halted;
`
`a halting mechanism that is configured to halt an instruction-processing
`
`portion of the processor; and
`
`a voltage reducing mechanism that is configured to reduce a voltage
`
`supplied to the instruction-processing portion of the processor, while maintaining
`
`full voltage to a second portion of the processor;
`
`whereby the second portion of the processor can continue to operate while
`
`the instruction-processing portion of the processor is in a reduced power mode.
`
`12.
`
`The apparatus of claim 11, wherein reducing the voltage supplied
`
`to the instruction-processing portion of the processor involves reducing the
`
`voltage to a minimum value that maintains state information within the
`
`instruction-processing portion of the processor.
`
`13.
`
`The apparatus of claim 11, wherein reducing the voltage supplied
`
`to the instruction-processing portion of the processor involves reducing the
`
`voltage to zero.
`
`14.
`
`The apparatus of claim 13, further comprising a saving mechanism
`
`that is configured to save state information from the instruction-processing portion
`
`of the processor prior to reducing the voltage supplied to the instruction-
`
`Attorm:y Docket No. APL-P2766
`EJG W:\APPLE COMPUTERIAPL-P2766\APL-P2766 APPLICATION DOC
`
`Inventor: Youngs
`
`12
`
`Qualcomm, Ex. 1007, Page 14
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`

`

`4
`
`5
`
`processing portion of the processor, wherein saving state information includes
`
`saving state information to one of, the second portion of the processor and a main
`
`6 memory.
`
`15.
`
`The apparatus of claim 14, further comprising:
`
`a voltage restoring mechanism that is configured to restore full voltage to
`
`the instruction-processing portion of the processor;
`
`a state restoring mechanism that is configured to restore state information
`
`to the instruction-processing portion of the processor; and
`
`a resuming mechanism that is configured to resume processing of
`
`computer instructions.
`
`16.
`
`The apparatus of claim 11, wherein maintaining full voltage to the
`
`second portion of the processor involves maintaining full voltage to a snoop-logic
`
`portion of the processor, whereby the processor can continue to perform cache
`
`snooping operations while the instruction-processing portion of the processor is in
`
`the reduced power mode.
`
`2
`
`3
`
`4
`
`5
`
`6
`
`7
`
`2
`
`3
`
`4
`
`5
`
`17.
`
`The apparatus of claim 11, wherein the voltage reducing
`
`2 mechanism is further configured to reduce the voltage to a cache memory portion
`
`3
`
`of the processor upon receiving the signal.
`
`18.
`
`The apparatus of claim 17, further comprising a writing mechanism
`
`that is configured to write cache memory data to main memory prior to reducing
`
`the voltage.
`
`2
`
`3
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`Attorney Docket No. APL-P2766
`
`Inventor: Youngs
`
`EJG W:\APPLE COMPUTER\APL-P::!766\APL-P::!766 APPLICATION. DOC
`
`13
`
`Qualcomm, Ex. 1007, Page 15
`
`

`

`19.
`The apparatus of claim 11, wherein the second portion of the
`processor includes a control portion of the processor that includes interrupt and
`clock circuitry.
`
`2 0.
`The apparatus of claim 11, wherein the second portion of the
`processor includes a cache memory portion of the processor.
`
`2
`
`3
`
`2
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`Attorney Docket No. APL-P'.2766
`EJG W:\APPLE COMPUTERI.APL-P17661.APL-P2766 APPLICATION.DOC
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`Inventor: Youngs
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`14
`
`Qualcomm, Ex. 1007, Page 16
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`

`

`CONSERVING POWER BY REDUCING
`VOLTAGE SUPPLIED TO AN INSTRUCTION(cid:173)
`PROCESSING PORTION OF A PROCESSOR
`
`ABSTRACT
`One embodiment of the present invention provides a system that facilitates
`reducing static power consumption of a processor. During operation, the system
`receives a signal indicating that instruction execution within the processor is to be
`temporarily halted. In response to this signal, the system halts an instruction(cid:173)
`processing portion of the processor, and reduces the voltage supplied to the
`instruction-processing portion of the processor. Full voltage is maintained to a
`remaining portion of the processor, so that the remaining portion of the processor
`can continue to operate while the instruction-processing portion of the processor
`is in reduced power mode.
`
`Attorney Docket No. APL-P2766
`EJG W:\APPLE COMPUTERIAPL-P27661APL-P2766 APPLICATION.DOC
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`Inventor: Youngs
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`15
`
`Qualcomm, Ex. 1007, Page 17
`
`

`

`-. t
`
`CLOCK SIGNAL 130
`
`INTERRUPTS 128
`
`PROCESSOR 102 ,
`
`: I
`
`REGISTER FILES 106
`
`~ I
`ARITHMETIC-LOGIC UNIT 104 I
`: I
`I
`: I
`I
`i I
`I
`
`PIPELINES 108
`
`L 1 CACHES 110
`
`INTERRUPT PROCESSOR 112
`
`REAL-TIME CLOCK 114
`
`CLOCK DISTRIBUTION
`CIRCUITRY 116
`
`L2 CACHE 118
`
`CACHE TAGS 120
`
`CACHE SNOOP CIRCUITRY 122
`
`'~
`M EMORY
`SIGNALS 132
`
`NON-CORE POWER AREA 124
`..
`
`CORE POWER AREA 126
`""
`
`NON-CORE POWER 136
`
`CORE POWER 134
`
`FIG. 1A
`
`Qualcomm, Ex. 1007, Page 18
`
`

`

`CLOCK SIGNAL 130
`
`INTERRUPTS 128
`
`..I
`·1
`
`REAL-TIME CLOCK 114
`
`CLOCK DISTRIBUTION
`CIRCUITRY 116
`
`I INTERRUPT PROCESSOR 112 I ~
`I ~
`I j
`..I
`. . NON-CORE POWER AREA 124
`·1
`" .............................
`I
`.I
`I
`I
`I
`'I
`
`PROCESSOR 102 ,
`
`ARITHMETIC-LOGIC UNIT 104
`
`REGISTER FILES 106
`
`PIPELINES 108
`
`,
`
`L 1 CACHES 110
`
`L2 CACHE 118
`
`CACHE TAGS 120
`
`: CACHE SNOOP CIRCUITRY 1221
`
`CORE POWER AREA 126
`
`.
`
`MEMORY
`SIGNALS 132
`
`CORE POWER 134
`
`NON-CORE POWER 136
`
`FIG. 18
`
`Qualcomm, Ex. 1007, Page 19
`
`

`

`START
`
`MONITOR PROCESSOR LOAD 202
`
`YES
`
`NO
`
`YES
`
`HALT PROCESSOR 208
`
`SAVE STATE 214
`
`WAIT FOR INTERRUPT 210
`
`HALT PROCESSOR 216
`
`RESTART PROCESSOR 212
`
`REDUCE CORE POWER 218
`
`WAIT FOR INTERRUPT 220
`
`RESTORE CORE POWER 222
`
`RESTART PROCESSOR 224
`
`RESTORE STATE 226
`
`FIG. 2
`
`Qualcomm, Ex. 1007, Page 20
`
`

`

`J .L
`
`Case/Docket No.: APL-P2766
`
`I lll\111111111111111111111111111111
`22835
`
`PA TENT TRADEMARK OFFICE
`
`PATENT
`DECLARA. TION AND PO\VER OF A TTORJ."\IEY FOR UTILITY PATENT APPLICATION
`As a below named inventor, I hereby declare that:
`
`Attorney Docket No. APL-P2766
`
`My residence, post office address and citizenship are as stated below, next to my name,
`I believe I am the original, first and sole inventor or an original, first and joint inventor of the subject matter
`which is claimed and for which a patent is sought on the invention entitled
`CONSERVliVG PQHlER BY REDUCliVG VOLTA.GE SUPPLIED TOAN lNSTRUCT!ON-PROCESSING PORTION OF A. PROCESSOR
`· tne specification of which
`
`~ is anached hereco.
`
`I llllll lllll lllll lllll lllll llll llll
`22835
`
`was filed on as
`Applicncion Serial No.
`and 1,,v::i.s amended on -------
`f hereby state that [ have revie.,ved and understin.d the contents of the above-identified specific;:ition,
`including the cl2.ims. as J.mended by any ;:imendmenc refe::red to above. f do not k.no1,,v and donor beli·1e that
`,he same -.,v;:is e•:er k_:701,,vn or used in the United Sm.res of Americ::1 before my invention thereof, or patented or
`described in anv orinted oublic:uion in anv councr1 before mv invention thereof or more than one vear orior
`to this .1pplic::uion. th2.c the so..me 1,v;:i.s noc in public use or on SJ.le tl;. the Lniced Sto..tes of America more than
`one ye:ir prior co this application, and s;:i.id inve:1cion has not beeri patented or made the subject of an
`inve:icor·s cer.:iri.c:1ce issued before che d:tte of this appiication in any country foreign to the United Sm.res of
`· America on an applic::1tion filed by me or my legal representatives or assigns more than cvvelve months prior
`to this application.
`
`"
`
`"'
`
`"'
`
`"'
`
`J
`
`...
`
`"'
`
`"
`
`f ack,;101,,vledge the duty to disclose infor.-narion 1,vhich is mare:-ia! to the examinacion of this application in
`accordance with Title 37, Code of Feder:::i.l Regulations, Section !.56(a).
`f hereby claim foreign priority benefits under Title 35, United States Codi!, Section I I 9, of any foreign
`applic:ttion(s) for patenc or inventor's certificat listed below and have also identified below any foreign
`application for patent or inventor's certificate having a filing date before that of the application on which
`priority is claimed:
`
`Prior Forei!m Aoolicarion(s)
`
`Prioritv Claimed
`
`(Number)
`
`(Country
`
`(Day/Month/Year Filed)
`
`Yes
`
`No
`
`BEST AVAILABLE COPY
`
`Qualcomm, Ex. 1007, Page 21
`
`

`

`J
`
`Attorney Docket No. APL-P2766
`
`I hereby claim the benefit under Title 35, United States Code, Section 120 of any United States application(s)
`or Section 365 (c) of any PCT international application designating the United States of America, listed
`below and, insofar a? the subject matter of each of the claims of this application is not disclosed in prior
`United States or PCT International application in the manner provided by the first paragraph of Title 35,
`United States Code, Section 112, I acknowledge the duty to disclose infonnation which is material to
`patentability as defined in Title 37, Code of Federal Regulations, Section 1.56 which became available
`between the filing date of the prior application and the national or PCT international filing date of this
`application:
`
`(Application Serial No.)
`(Filing Date)
`(Status - patented, pending, aban.doned)
`I
`l hereby app~int my attorneys, Daniel E. VaughanLReg. No. 42,199; Edward J. Grundler Reg. No. 47,615;
`~
`Hoy1 A. Fleming, Reg. No. 41,752; and A. Richard Park, Reg. No. 41,241 qf