U.S. Patent No. 7,383,453 Corrected Claims
`
`1. An instruction-processing system with minimal minimized static power leakage, the
`instruction-processing system comprising:
`a core with instruction-processing circuitry;
`an area coupled to the core;
`a core voltage provided to the core; and
`an area voltage provided to the area;
`wherein in a normal operation mode:
`a clock signal to the core is active;
`the core voltage is a first value that is sufficient to maintain the state information
`of the instruction-processing circuitry;
`the core is active;
`the area voltage is a second value that is sufficient to maintain the data stored in
`the area; and
`the area is active;
`wherein in a first power-saving mode that is can be exited upon receipt of an interrupt
`signal:
`
`the clock signal to the core is inactive;
`the core voltage is equal to or greater than the first value sufficient to maintain the
`state information of the instruction-processing circuitry; and
`the area voltage is equal to or greater than the second value sufficient to maintain
`the data stored in the area;
`wherein in a second power-saving mode that can be exited upon receipt of a signal that is
`not an interrupt signal:
`the clock signal to the core is inactive;
`the core voltage is less than the first value; and
`the area voltage is equal to or greater than the second value sufficient to maintain
`the data stored in the area.
`
`2. The instruction-processing system of claim 1, wherein the first power-saving mode can
`be exited upon receipt of a signal that is not an interrupt signal.
`
`3. The instruction-processing system of claim 1, wherein the area comprises a cache.
`
`4. The instruction-processing system of claim 3, wherein the area further
`comprises cache tags.
`
`5. The instruction-processing system of claim 1, wherein prior to entering the second
`power-saving mode, the state of the core is saved to a memory.
`
`6. The instruction-processing system of claim 1, wherein upon exiting the second power-
`saving mode, the state of the core is restored.
`
`Qualcomm, Ex. 1002, Page 1
`
`
`
`1. An instruction-processing system with minimal minimized static power leakage, the
`instruction-processing system comprising:
`a core with instruction-processing circuitry;
`an area coupled to the core;
`a core voltage provided to the core; and
`an area voltage provided to the area;
`wherein in a normal operation mode:
`a clock signal to the core is active;
`the core voltage is a first value that is sufficient to maintain the state information
`of the instruction-processing circuitry;
`the core is active;
`the area voltage is a second value that is sufficient to maintain the data stored in
`the area; and
`the area is active;
`wherein in a first power-saving mode that is can be exited upon receipt of an interrupt
`signal:
`
`the clock signal to the core is inactive;
`the core voltage is equal to or greater than the first value sufficient to maintain the
`state information of the instruction-processing circuitry; and
`the area voltage is equal to or greater than the second value sufficient to maintain
`the data stored in the area;
`wherein in a second power-saving mode that can be exited upon receipt of a signal that is
`not an interrupt signal:
`the clock signal to the core is inactive;
`the core voltage is less than the first value; and
`the area voltage is equal to or greater than the second value sufficient to maintain
`the data stored in the area.
`
`2. The instruction-processing system of claim 1, wherein the first power-saving mode can
`be exited upon receipt of a signal that is not an interrupt signal.
`
`3. The instruction-processing system of claim 1, wherein the area comprises a cache.
`
`4. The instruction-processing system of claim 3, wherein the area further
`comprises cache tags.
`
`5. The instruction-processing system of claim 1, wherein prior to entering the second
`power-saving mode, the state of the core is saved to a memory.
`
`6. The instruction-processing system of claim 1, wherein upon exiting the second power-
`saving mode, the state of the core is restored.
`
`Qualcomm, Ex. 1002, Page 1
`
`
`
`7. The instruction-processing system of claim 1, wherein in the second power-saving
`mode, the core voltage is at zero.
`
`8. A method for minimizing static power leakage in an instruction-processing system, wherein
`the instruction-processing system comprises a core with instruction-processing circuitry, an area
`coupled to the core, a core voltage provided to the core, and an area voltage provided to the area,
`the method comprising:
`entering a normal operation mode by:
`providing a clock signal to the core;
`providing the core with a core voltage that is equal to a first value that is sufficient
`to maintain the state information of the instruction-processing circuitry;
`providing the area with an area voltage that is equal to a second value that is
`sufficient to maintain the data stored in the area;
`entering a first power-saving mode by:
`disabling the clock signal to the core;
`providing the core with a core voltage that is equal to sufficient to maintain the
`state information of the instruction-processing circuitry or greater than the first
`value; and
`providing the area with an area voltage that is equal to sufficient to maintain the
`data stored in the area or greater than the second value;
`exiting the first power-saving mode upon receipt of an interrupt signal;
`entering a second power-saving mode by:
`disabling the clock signal to the core;
`setting the core voltage to a value less than the first value; and
`providing the area with an area voltage that is equal to or greater than the second
`value; and
`exiting the second power-saving mode upon receipt of a signal that is not an interrupt
`signal.
`
`9. The method of claim 8, further comprising exiting the first power-saving mode upon
`receipt of a signal that is not an interrupt signal.
`
`10. The instruction-processing system method of claim 8, wherein the area comprises a
`cache.
`
`11. The method of claim 10, wherein the area further comprises cache tags.
`
`12. The method of claim 8, further comprising saving the state of the core to a memory
`prior to entering the second power-saving mode.
`
`13. The method of claim 8, further comprising restoring the state of the core upon exiting
`the second power-saving mode.
`
`14. The method of claim 8, wherein in the second power-saving mode, setting the core
`voltage to the value less than the first value comprises setting the core voltage to zero.
`
`Qualcomm, Ex. 1002, Page 2
`
`
`
`15. A computer-readable medium containing data representing storing code which represents an
`instruction-processing system with minimal minimized static power leakage, the instruction-
`processing system comprising:
`a core with instruction-processing circuitry;
`an area coupled to the core;
`a core voltage provided to the core; and
`an area voltage provided to the area;
`wherein in a normal operation mode:
`a clock signal to the core is active;
`the core voltage is a first value that is sufficient to maintain the state information
`of the instruction-processing circuitry;
`the core is active;
`the area voltage is a second value that is sufficient to maintain the data stored in
`the area; and
`the area is active;
`wherein in a first power-saving mode that is can be exited upon receipt of an interrupt
`signal:
`
`the clock signal to the core is inactive;
`the core voltage is equal to or greater than the first value sufficient to maintain the
`state information of the instruction-processing circuitry; and
`the area voltage is equal to or greater than the second value sufficient to maintain
`the data stored in the area;
`wherein in a second power-saving mode that can be exited upon receipt of a signal that is
`not an interrupt signal:
`the clock signal to the core is inactive;
`the core voltage is less than the first value; and
`the area voltage is equal to or greater than the second value sufficient to maintain
`the data stored in the area.
`
`16. The computer-readable medium of claim 15, wherein the first power-saving mode can
`be exited upon receipt of a signal that is not an interrupt signal.
`
`17. The computer-readable medium of claim 15, wherein the area comprises a cache.
`
`18. The computer-readable medium of claim 17, wherein the area further
`comprises cache tags.
`
`19. The computer-readable medium of claim 15, wherein prior to entering the second
`power-saving mode, the state of the core is saved to a memory.
`
`20. The computer-readable medium of claim 15, wherein upon exiting the second power-
`saving mode, the state of the core is restored.
`
`21. The computer-readable medium stem of claim 15, wherein in the second power-
`saving mode, the core voltage is at zero.
`
`Qualcomm, Ex. 1002, Page 3
`
`
Accessing this document will incur an additional charge of $.
After purchase, you can access this document again without charge.
Accept $ Charge
Still Working On It
This document is taking longer than usual to download. This can happen if we need to contact the court directly to obtain the document and their servers are running slowly.
Give it another minute or two to complete, and then try the refresh button.
A few More Minutes ... Still Working
It can take up to 5 minutes for us to download a document if the court servers are running slowly.
Thank you for your continued patience.
This document could not be displayed.
We could not find this document within its docket. Please go back to the docket page and check the link. If that does not work, go back to the docket and refresh it to pull the newest information.
Your account does not support viewing this document.
You need a Paid Account to view this document. Click here to change your account type.
Your account does not support viewing this document.
Set your membership
status to view this document.
With a Docket Alarm membership, you'll
get a whole lot more, including:
- Up-to-date information for this case.
- Email alerts whenever there is an update.
- Full text search for other cases.
- Get email alerts whenever a new case matches your search.
One Moment Please
The filing “” is large (MB) and is being downloaded.
Please refresh this page in a few minutes to see if the filing has been downloaded. The filing will also be emailed to you when the download completes.
Your document is on its way!
If you do not receive the document in five minutes, contact support at support@docketalarm.com.
Sealed Document
We are unable to display this document, it may be under a court ordered seal.
If you have proper credentials to access the file, you may proceed directly to the court's system using your government issued username and password.
Access Government Site
