Paper No. 1
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`__________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`__________________
`
`
`QUALCOMM INC. AND QUALCOMM TECHNOLOGIES,
`INC.
`
`Petitioners
`
`v.
`
`APPLE INC.
`
`Patent Owner
`
`
`
`U.S. PATENT NO. 7,383,453
`
`TITLE: CONSERVING POWER BY REDUCING VOLTAGE
`SUPPLIED TO AN INSTRUCTION-PROCESSING PORTION
`OF A PROCESSOR
`
`Issue Date: June 3, 2008
`
`
`PETITION FOR INTER PARTES REVIEW
`UNDER 35 U.S.C. § 312
`
`
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`
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`TABLE OF CONTENTS
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`Page
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`B.
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`Introduction ................................................................................................... 1
`I.
`II. Mandatory Notices........................................................................................ 3
`A. Real Party in Interest (37 C.F.R. § 42.8(b)(1)) ................................ 3
`B. Related Matters (37 C.F.R. § 42.8(b)(2)) .......................................... 3
`C.
`Lead and Back-Up Counsel and Service Information (37
`C.F.R. § 42.8(b)(3) and (b)(4)) ........................................................... 4
`Fees (37 C.F.R. § 42.103) ................................................................... 4
`D.
`III. Grounds for Standing (37 C.F.R. § 104(a)) ................................................ 5
`IV. Statement of Precise Relief Requested for Each Challenged Claim ........ 5
`A.
`The Claims for Which Review Is Requested (37 C.F.R.
`§ 42.104(b)(1)) ..................................................................................... 5
`The Specific Statutory Grounds on Which the Challenge Is
`Based and Prior Art Relied Upon for Each Ground (37
`C.F.R. § 42.104(b)(2)) ......................................................................... 5
`V. Reasons for the Relief Requested Under 37 C.F.R. §§ 42.22(a)(2)
`and 42.104(b)(4) ............................................................................................ 7
`A. Overview of the ’453 Patent and its Technology ............................. 7
`B.
`The Prosecution History of the ’453 Patent ..................................... 9
`1.
`Original Prosecution ................................................................ 9
`2.
`Ex parte Reexamination ........................................................ 12
`37 C.F.R. § 42.104(b)(3): Claim Construction .............................. 13
`1.
`A Person of Ordinary Skill in the Art .................................. 13
`2.
`Construction of Claim Terms ............................................... 14
`3.
`“core” and “area” .................................................................. 15
`4.
`“sufficient to maintain the state information of the
`instruction-processing circuitry” .......................................... 17
`D. Overview of the Prior Art ................................................................ 17
`1.
`Ober ......................................................................................... 17
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`C.
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`TABLE OF CONTENTS
`(continued)
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`Page
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`E.
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`DeSchepper ............................................................................. 20
`2.
`Fung ʼ011 ................................................................................ 22
`3.
`37 C.F.R. § 42.104(b)(4): How the Construed Claims are
`Unpatentable ..................................................................................... 25
`37 C.F.R. § 42.104(b)(5): Supporting Evidence ............................ 25
`F.
`VI. Claims 1-4 and 8-11 of the ’453 Patent Are Unpatentable ..................... 25
`A. Ground 1: Claims 1-2 and 8-9 Are Invalid as Anticipated by
`Ober ................................................................................................... 26
`B. Ground 2: Claims 3-4 and 10-11 are Obvious over Ober in
`view of DeSchepper .......................................................................... 40
`C. Ground 3: Claims 1-2 and 8-9 Are Invalid as Anticipated by
`Fung ʼ011 ........................................................................................... 44
`D. Ground 4: Claims 3-4 and 10-11 are Obvious over
`Fung ʼ011 in view of DeSchepper ................................................... 59
`VII. Conclusion ................................................................................................... 64
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`I.
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`Introduction
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`Pursuant to 35 U.S.C. § 312 and 37 C.F.R. § 42.100 et seq., Qualcomm Inc.
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`and Qualcomm Technologies, Inc. (collectively, “Petitioners” or “Qualcomm”)
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`request inter partes review of claims 1-4 and 8-11 (the “Challenged Claims”) of
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`U.S. Patent No. 7,383,453 (“the ʼ453 Patent,” Ex. 1001),1 which issued on June 3,
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`2008 and is assigned to Apple, Inc. (“Patent Owner” or “Apple”).
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`The ’453 Patent is directed to an instruction-processing system with multiple
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`power-saving modes intended to reduce static power leakage. Ex. 1002 at cl. 1. The
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`claims require a separate “core” and “area” within the instruction-processing system.
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`Id. The power consumption of the “core” and the “area” may be controlled
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`independently by modifying the voltage levels and clock frequencies to the
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`components in the “core” and “area” independently. Id.
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`The ’453 Patent purports to improve upon prior art by disclosing an
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`instruction processing-system capable of entering more than one power-saving
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`mode. This gives the system the option of entering a power-saving mode in which
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`the “core” clock is turned off, or alternatively entering a power-saving mode in
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`which the “core” clock is turned off and the voltage in the “core” must be reduced
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`1 Ex. 1002 reproduces the ʼ453 Patent claims as they were modified via Certificates
`
`of Correction. The Certificates of Correction are included with Ex. 1001.
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`from normal operational levels. The former option ensures a shorter latency period
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`when the power-saving mode is exited, while the latter ensures greater power
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`savings.
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`There is nothing patentable, however, about the use of multiple power-saving
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`modes that may (or may not) retain state information in the instruction-processing
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`circuitry. During prosecution, Applicant distinguished prior art cited by the
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`Examiner to reject the claims, arguing that the cited references “disclose only one
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`low-power mode, where the power to a portion of the processor is completely
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`removed while the processor state is lost and must be maintained somewhere else.”
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`Ex. 1007 at 164 (emphasis in original). Yet the use of multiple power-saving modes
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`is disclosed by each of U.S. Patent No. 6,665,802 to Ober (“Ober”) (Exhibit 1004)
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`and U.S. Patent No. 7,134,011 to Fung ʼ011 (“Fung ʼ011”) (Exhibit 1005), neither
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`of which were of record during prosecution of the ʼ453 Patent.
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`Nor is there anything patentable about the other aspects of the Challenged
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`Claims, which recite conventional partitioning of power to portions of the
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`instruction processing system. Indeed, the type of partitioning of conventional
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`elements recited in the Challenged Claims is similarly described in Ober, Fung ʼ011,
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`and U.S. Patent No. 5,721,935 to DeSchepper (“DeSchepper”) (Exhibit 1006).
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`None of these references were of record during prosecution. And the specification
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`of the ʼ453 Patent even acknowledges in the “Background” description of “Related
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`Art” that controlling power consumption in separate power domains was not novel.
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`Ex. 1001 at 1:40-46 (“Designers have taken advantage of this fact by reducing the
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`frequency of (or halting) clock signals to certain portions of a processor when the
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`processor is idle. Note that some portions of the processor must remain active,
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`however. For example, a cache memory with its associated snoop circuitry will
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`typically remain active as well as interrupt circuitry and real-time clock circuitry.”).
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`Because the Challenged Claims are unpatentable in view of Ober, Fung ʼ011,
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`and DeSchepper, inter partes review should be instituted and the Challenged Claims
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`should be cancelled.
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`II. Mandatory Notices
`
` Real Party in Interest (37 C.F.R. § 42.8(b)(1))
`Qualcomm Inc. and Qualcomm Technologies, Inc. are the real parties-in-
`
`interest.
`
` Related Matters (37 C.F.R. § 42.8(b)(2))
`The ’453 Patent and a related continuation patent (U.S. Patent No. 8,433,940)
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`are involved in the following proceeding that may affect or be affected by a decision
`
`in this proceeding: Qualcomm Inc. v. Apple Inc., Case No. 3:17-cv-1375 (S.D. Cal.)
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`(“’1375 Case”). Additionally, Qualcomm is concurrently filing a separate petition
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`challenging claims of the related patent U.S. Patent No. 8,433,940, which is in the
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`same family, and shares a specification with, the ʼ453 Patent.
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` Lead and Back-Up Counsel and Service Information (37 C.F.R.
`§ 42.8(b)(3) and (b)(4))
`Lead Counsel
`John A. Marlott,
`jamarlott@jonesday.com
`Reg. No. 37,031
`JONES DAY
`77 West Wacker Dr.
`Chicago, IL 60601
`(312) 269-4240
`
`
`Back-up Counsel
`John M. Michalik,
`jmichalik@jonesday.com
`Reg. No. 56,914
`Thomas W. Ritchie,
`twritchie@jonesday.com
`Reg. No. 65,505
`JONES DAY
`77 West Wacker Dr.
`Chicago, IL 60601
`(312) 269-4215
`
`Matthew W. Johnson,
`mwjohnson@jonesday.com
`Reg. No. 59,108
`JONES DAY
`One Mellon Center
`500 Grant Street
`Pittsburgh, PA 15219
`(412) 394-9524
`
`Pursuant to 37 C.F.R. § 42.10(b), a Power of Attorney accompanies this
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`Petition. Please address all correspondence to lead and back-up counsel at the
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`address above. Qualcomm also consents to electronic service by email at the email
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`addresses listed above.
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`Fees (37 C.F.R. § 42.103)
`The undersigned representative of Petitioners authorizes the Board to charge
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`the $15,500 Petition Fee, as well as any additional fees, to Deposit Account 501432,
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`ref: 178774-680001. Eight claims are being reviewed, so $15,000 in post institution
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`fees are due for a total of $30,500.
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`III. Grounds for Standing (37 C.F.R. § 104(a))
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`Petitioners certify that the ’453 Patent is available for inter partes review, and
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`that Petitioners are not barred or estopped from requesting inter partes review of the
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`Challenged Claims on the grounds identified in this Petition. Apple filed and served
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`its first amended answer and counterclaims in the ’1375 Case, first asserting
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`infringement of the ’453 Patent by Petitioners, on November 29, 2017. This petition
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`is being filed within one year of service of Apple’s first amended answer and
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`counterclaims, and shortly after the District Court issued a claim construction order
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`adopting certain of Apple’s positions regarding the breadth of the ʼ453 Patent.
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`IV. Statement of Precise Relief Requested for Each Challenged Claim
`
` The Claims for Which Review Is Requested (37 C.F.R.
`§ 42.104(b)(1))
`Petitioners request review and cancellation of claims 1-4 and 8-11 of the ʼ453
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`Patent (the “Challenged Claims”).
`
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`The Specific Statutory Grounds on Which the Challenge Is Based
`and Prior Art Relied Upon for Each Ground (37 C.F.R. § 42.104(b)(2))
`Petitioners request inter partes review of the Challenged Claims on the
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`grounds set forth below and request that each of the Challenged Claims be found
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`unpatentable. An explanation of how the Challenged Claims are unpatentable is
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`provided in the form of the detailed description that follows, indicating where each
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`of the claim elements can be found in the prior art. Additional explanation and
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`support for each ground is set forth in the Declaration of Richard Belgard
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`(Ex. 1003), referenced throughout this Petition.
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`’453 Patent Claims
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`Ground 1
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`Claims 1-2, 8-9
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`35 U.S.C. § 102 in view of US. Patent No.
`6,665,802 “Ober”
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`Claims 3-4, 10-11
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`35 U. s.C § 103(a) over Ober1n View ofU. 5
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`Ground 4
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`Claims 3—4, 10-11
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`35 U. S.C. § 103(a) based on Fung ’011in View
`of DeSche I er
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`The ’453 Patent issued June 3, 2008 from US. Application No. 11/213,215
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`(“’215 App.”), filed August 25, 2005. The ’453 Patent is a continuation of US.
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`Application No. 11/103,911 (filed on April 11, 2005), which was subsequently
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`granted as US. Patent No. 6,973,585 (“the ’585 Patent”). The ’585 Patent is a
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`continuation of US. Application No. 10/135,116 (filed on April 29, 2002), which
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`was subsequently granted as US. Patent No. 6,920,574. Accordingly, the earliest
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`date to which the ’453 Patent could claim priority (hereinafter the “earliest effective
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`filing date”) is April 29, 2002.
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`Ober was filed on February 29, 2000 and issued on December 16, 2003. Ober
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`is prior art under pre-AIA 35 U.S.C. § 102(c).
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`DeSchepper was filed on February 18, 1997 and issued on February 24, 1998.
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`DeSchepper is prior art under pre-AIA 35 U.S.C. §§ 102(a), (b), and (e).
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`Fung ʼ011 was filed on May 18, 2001 and issued on November 7, 2006.
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`Fung ʼ011 and is prior art under 35 U.S.C. § 102(e).
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`V. Reasons for the Relief Requested Under 37 C.F.R. §§ 42.22(a)(2) and
`42.104(b)(4)
` Overview of the ’453 Patent and its Technology
`The ʼ453 Patent relates to a method and architecture for reducing power
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`consumption in an instruction-processing system. Ex. 1001 at Abstract. The ʼ453
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`Patent specification acknowledges that “reducing the frequency of (or halting) a
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`system clock signal can reduce the dynamic power consumption of a processor,” and
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`was commonly used in the prior art as a means of power conservation. Id. at 1:47-
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`50 (emphasis added). At the time of the alleged invention, however, methods and
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`architectures for “reduc[ing] static power consumption for a processor in a battery
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`operated computing device” were allegedly not well understood. Id. at 1:59-61
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`(emphasis added). Therefore, the ʼ453 Patent is directed to “a system that facilitates
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`reducing static power consumption of a processor.” Id. at Abstract (emphasis
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`added).
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`To achieve static power savings, the ʼ453 Patent describes an instruction-
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`processing system divided into two “power areas”: a “core power area 126” and a
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`“non-core power area 124.” Id. Fig. 1A. The “core power area 126 includes the
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`instruction-processing portion of the processor” and the “non-core power area
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`comprises the remaining portion of [the] processor.” Id. at 3:9-10. An exemplary
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`embodiment of the instruction-processing system is provided in Figure 1A:
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`Id. Fig. 1A.
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`According to the embodiments described in the specification, static power
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`savings may be achieved by reducing the voltage in the core power area. Id. at 4:47-
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`5:25; see also id. at 1:65-2:45. In certain embodiments, the clock to the core power
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`area may also be halted as a means of saving dynamic power, thus increasing the
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`overall power savings. See, e.g., id. at 4:59-5:3.
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`The issued claims of the ʼ453 Patent do not use the same terminology as the
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`specification. Specifically, the claims do not refer to a “core power area” or a “non-
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`core power area.” Instead, the claims refer more broadly to a “core” and an “area.”
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`According to the claims, the voltage and clock to the “core” and “area” may be
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`modified in multiple power-saving modes in order to achieve power savings. See
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`Ex. 1002 at claims 1-4, 8-11.
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`
`
`The Prosecution History of the ’453 Patent
`1. Original Prosecution
`The ʼ453 Patent was filed as a continuation application to the ʼ585 Patent on
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`August 25, 2005. The independent claims of the application leading to the ʼ453
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`Patent originally recited a single power-saving method involving “halting an
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`instruction-processing portion of the processor” and “reducing a voltage supplied to
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`the instruction-processing portion of the processor.” Ex. 1007 at 12.
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`In an initial Office Action on December 19, 2006, the Examiner rejected the
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`independent claims, among others, as anticipated by U.S. Patent No. 5,666,537 to
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`Debnath (“Debnath”) (Ex. 1008) or obvious over Debnath in view of U.S. Patent
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`No. 6,795,896 to Hart (“Hart”) (Ex. 1009). Ex. 1007 at 53-59. Applicant’s response
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`dated February 12, 2007 stated that the cited art only referred to “gating” the clock,
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`whereas the claims in the application also referred to reducing the supply voltage.
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`Ex. 1007 at 70-71. The Examiner, however, was not persuaded and maintained the
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`prior art rejection in a final rejection. Ex. 1007 at 82-88.
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`Although Applicant initially responded to the final rejection by restating his
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`arguments and without amending his claims (Ex. 1007 at 97-98), he subsequently
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`filed a Request for Continued Examination and amended the claims on July 9, 2007
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`(Ex. 1007 at 107-18). The amended claims now recited three separate “power
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`modes”: a first power mode in which the clock signals are active and the power is
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`on; a second power mode in which the clock is inactive; and a third power mode in
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`which the clock is inactive and power is off. Ex. 1007 at 111.
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`The Examiner again rejected the amended claims in view of additional prior
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`art on August 20, 2007. Ex. 1007 at 141-51. Specifically, the Examiner issued a
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`non-final rejection based on U.S. Patent Application Publication No. 2003/0056127
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`(“Vaglica”) (Ex. 1010) in view of U.S. Patent No. 6,792,551 to Dai (“Dai”) (Ex.
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`1011). Ex. 1007 at 141-51. The Examiner stated that Vaglica provided all elements
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`of the claims, as amended, other than the final element: “a third power mode in
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`which clock signals are inactive and power is off for the core power area of the
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`processor.” Id. at 145-46. According to the Examiner, however, the final element
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`was disclosed by Dai. Id.
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`In response, Applicant further amended the claims on November 14, 2007 to
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`more explicitly define the power modes. Ex. 1007 at 157. Notably, Applicant’s
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`further amended claims did not recite any mode (e.g., a “normal operation mode”) in
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`which (i) the clock signals are active and (ii) the power is on. Instead, Applicant’s
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`further amended claims recited:
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` A “first power-saving mode” in which the “clock signal to the core
`power area is removed and the core power voltage is sufficiently low to
`prevent the instruction-processing circuitry from processing
`instructions but sufficiently high to maintain states information stored
`in the processor registers within the core power area”; Ex. 1007 at 157;
`and
` A “second power-saving mode” in which the “clock signal to the core
`power area is removed and the core power voltage is substantially
`reduced to zero, thereby reducing static leakage current in the
`processor.” Id.
`Id. Additionally, Applicant’s November 14, 2007 response sought to distinguish
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`Vaglica and Dai by arguing that neither reference disclosed the use of multiple
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`power modes in a single device. Id. at 9-10.
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`In response, the Examiner allowed Applicant’s claims without further
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`rejection on December 19, 2007. Ex. 1007 at 180-85. But Applicant subsequently
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`filed another Request for Continued Examination and further amended the claims on
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`February 26, 2008. Ex. 1007 at 180-201. Although the RCE did not include an
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`explanation, the still-further amended claims now recited a “normal operation mode”
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`in addition to the two power-saving modes. Id. at 194-95. As now amended, the
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`“normal operation mode” recited that the “clock signal to the core is active” and the
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`“core voltage is a first value.” Id. In the first power-saving mode, as now amended,
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`the “clock signal to the core is inactive” and the “core voltage is equal to or greater
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`than the first value.” Id. And, in the second power-saving mode, as now amended,
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`the “clock signal to the core is inactive” and the “core voltage is less than the first
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`value.” Id.
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`The Examiner and Applicant subsequently conducted an interview on March
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`20, 2008. Ex. 1007 at 212. During that interview, the Examiner and Applicant
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`agreed that the claims would be allowed if additional changes were made. Id. The
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`Examiner then allowed the claims on April 8, 2008. Ex. 1007 at 207-16. Although
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`the changes discussed during the March 20 interview were submitted via fax by
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`Applicant, they were not included in the issued claims when the ʼ453 Patent was
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`printed. Applicant therefore filed a series of Requests for Certificate of Correction
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`to ensure that the issued claims matched those that the Examiner and Applicant had
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`agreed upon during the March 20 interview. Ex. 1001 at 11-15. A corrected version
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`of the issued claims is attached as Exhibit 1002.
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`2.
`Ex parte Reexamination
`A third-party requester (not Petitioners) filed a Request for Ex parte
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`Reexamination of the ʼ453 Patent in April 2010. Ex. 1019. The Request asserted
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`that all claims (claims 1-21) of the ʼ453 Patent were not patentable in view of three
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`references: Patent Cooperation Treaty (PCT) Patent Application Publication No.
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`WO 01/27728 A1 to Qureshi et al. (“the Qureshi Application”) (Ex. 1012);
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`Applicant’s Admitted Prior Art in U.S. Patent No. 7,383,453; and Dai (Ex. 1011).
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`Ex. 1019 at 16-20. The Request was granted, and an ex parte reexamination of the
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`ʼ453 Patent was ordered. Ex. 1019 at 355-64. The Examiner found that the prior art
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`cited in the ex parte reexamination request did not “disclose or fairly suggest the
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`combination of all of the elements, steps, and limitations” in the ʼ453 patent claims.
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`Ex. 1019 at 420-22. Specifically, the Examiner found that “the combination of a
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`normal operation mode, a first power saving mode, and a second power saving mode
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`with [the] details as recited in independent claims 1, 8, and 15” were not disclosed in
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`the cited prior art. Id. at 420. Thus, the PTO issued an ex parte reexamination
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`certificate for the ʼ453 Patent on May 31, 2011.
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`The prior art references and grounds relied upon by Petitioners for
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`challenging the patentability of the ʼ453 Patent claims in this Petition were not
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`considered by the Office during the ex parte reexamination.
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`
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`37 C.F.R. § 42.104(b)(3): Claim Construction
`1.
`A Person of Ordinary Skill in the Art
`Petitioners maintain that a person of ordinary skill in the art (“POSITA”) as of
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`April 29, 2002 would have had a bachelor’s degree in electrical engineering or
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`computer science and would have had at least a few years of experience in, or
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`knowledge of, processor design. Additional education could substitute for less work
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`experience. Alternatively, substantial work experience could substitute for some of
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`the educational background. Ex. 1003 ¶¶ 61-64.
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`2.
`Construction of Claim Terms
`In this IPR, the claims of the ’453 Patent “shall be given the broadest
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`reasonable construction in light of the [’453 Patent’s] specification.” 37 C.F.R.
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`§ 42.100(b). Because a district court applies a different standard, however, the claim
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`constructions presented in this petition do not necessarily reflect the constructions
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`that Petitioners believe should be adopted by a district court.
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`In the ’1375 Case, the District Court adopted certain of Apple’s claim
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`construction positions. Ex. 1014 at 8–9. Petitioners have submitted the District
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`Court’s claim construction decision for the Board’s consideration. Power
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`Integrations, Inc. v. Lee, 797 F.3d 1318, 1326-27 (Fed. Cir. 2015) (“The fact that the
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`Board is not generally bound by a previous judicial interpretation of a disputed claim
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`term does not mean, however, that it has no obligation to acknowledge that
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`interpretation or to assess whether it is consistent with the broadest reasonable
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`construction of the term.”). Although Petitioners reserve the right to appeal or
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`otherwise challenge the District Court’s claim construction order, Petitioners request
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`that the Board in this IPR construe any claim terms at least as broad as the District
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`Court. See, e.g., Cisco Systems, Inc. v. Crossroads Systems, Inc., IPR2014-01463,
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`Final Written Decision, Paper 49 at 11-12 (PTAB, Mar. 16, 2016) (“Petitioners
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`argue that the ‘control access’ limitations ‘should be at least as broad as the District
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`Court’s construction-.. We agree with Petitioners”).
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`“core” and “area”2
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`P_p—roosed Construction
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`Plain and ordinary meaning.
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`“ “A portion ofthe processor excluding a core.”
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`The claim terms “core” and “area” are not used as standalone terms in the
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`’453 Patent specification. Nor was a definition of either term specified during
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`prosecution of the ’453 Patent. According to the literal claim language, independent
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`claim 1 of the ’453 Patent recites an “instruction-processing system comprising: a
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`2 Because of the interrelation between the claim terms “core” and “area,”
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`Petitioners address both terms together.
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`core with instruction-processing circuitry; [and] an area coupled to the core.” Ex.
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`1002 at cl. 1.3
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`In the ʼ1375 case, Apple has taken the position that “core” should be
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`construed to have its plain and ordinary meaning or, in the alternative, as “a logical
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`or physical instruction processing mechanism.” Ex. 1015 at 8-11. Apple has also
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`taken the position that “area” should be construed to refer to “a portion of the
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`processor excluding a core.” Id. Apple’s constructions for “core” and “area” do not
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`specify a particular architecture for, or identify any components which must be
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`included in (or excluded from), the “core” or the “area.” See id. at 10-11.
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`As to “core,” the District Court adopted Apple’s claim construction position.
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`For purposes of this inter partes review, Petitioners maintain that the Board should
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`construe this term according to its plain and ordinary meaning as the District Court
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`did and consistent with Apple’s proposed construction.
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`As to “area,” the District Court also adopted Apple’s proposed construction.
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`In this inter partes review, Petitioners maintain that Apple’s proposed construction
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`3 Similarly, Claim 8 recites an “instruction-processing system [which] comprises a
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`core with instruction-processing circuitry [and] an area coupled to the core.” Ex.
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`1002 at Cl. 8.
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`(“a portion of the processor excluding a core”) should be adopted as the broadest
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`reasonable interpretation.
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`4.
`“sufficient to maintain the state information of the
`instruction-processing circuitry”
`In the ʼ1375 Case, Apple has taken the position that “sufficient to maintain
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`the state information of the instruction-processing circuitry” should be construed as
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`“at least a value that maintains the state information of the instruction-processing
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`circuitry.” Ex. 1015 at 11-13. In particular, Apple has argued that “sufficient to
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`maintain the state information of the instruction-processing circuitry” refers to any
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`value greater than or equal to the minimum value that maintains the state
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`information of the instruction-processing circuitry. Ex. 1015 at 11-13. The District
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`Court adopted Apple’s proposed constructions. Ex. 1014 at 6. In this inter partes
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`review, Petitioners submit that Apple’s proposed construction should be adopted as
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`the broadest reasonable interpretation.
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` Overview of the Prior Art
`1. Ober
`Ober is titled “Power Management and Control for a Microcontroller.” Ex.
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`1004 at Title. Ober discloses a “power management architecture [which] includes a
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`power management state machine for controlling the power mode of the central
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`processing unit (CPU) and each of the subsystems within the microcontroller.” Id.
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`at 2:55-59. Although Ober repeatedly refers to a “microcontroller,” the specification
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`makes clear that “the term ‘microcontroller’ is deemed interchangeable with any
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`System-on-Chip (SoC).” Id. at 4:13-15. Ober describes the benefits of the invention
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`as including “increased battery life for portable microcontrolled devices” (Id. at
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`4:38-43), much like the specification of the ʼ453 Patent (Ex. 1001 at 1:59-61).
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`As shown below, the microcontroller in Ober includes a CPU core coupled
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`via a system bus to various components in the area:
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`Ex. 1004 Fig. 1.
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`The area includes an interrupt control unit, among other various subsystems.
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`Id. at 5:50-57; Fig. 1. Many of these components are shown in Figure 1 above.
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`Ober’s design allows for configurable power modes which enable, among
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`other things, “the ability of the system to maintain its state without data loss during
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`battery discharge conditions.” Id. at 5:6-10; see Table 8. Specifically, Ober
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`discloses (i) a normal operation mode in which all units are powered and all clocks
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`are operating; (ii) a first power-saving mode in which the clock to the CPU is turned
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`off without any change in voltage to the CPU; and (iii) a second power-saving mode
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`in which the clock to the CPU is turned off and the CPU is unpowered. Id. at Table
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`8. Both the first power-saving mode and the second power-saving mode may be
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`exited via an interrupt or a reset, among other mechanisms. Id. at Table 8. The
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`Table below describes these power-saving modes:
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`Id. at Table 8.
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`2.
`DeSchepper
`DeSchepper is titled “Apparatus and Method for Entering Low Power Mode
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`In A Computer System.” Ex. 1006 at Title. DeSchepper generally discloses a
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`“power management circuit for managing low power modes in a computer system,
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`which implements four power modes, from highest power consumption to lowest
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`power consumption: RUN mode, SLEEP mode, IDLE mode, and STANDBY
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`mode.” Id. at Abstract.
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`DeSchepper discloses a CPU which serves as a “core.” Id. Fig. 1. The CPU
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`is coupled via a bus to various components in the area. The specification states that
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`the CPU may be “a conventional microprocessor such as an Intel Pentium (P54C or
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`P24) or its equivalent.” Id. at 58-60. Moreover, the area described by DeSchepper
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`may include a cache memory (which may serve as a Level 2 (L2) cache), tag RAMs,
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`snoop circuitry, an interrupt controller and interrupt architecture, a real-time clock,
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`and clock-distribution circuitry. See, e.g., id. Fig. 1. Many of the components of the
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`core and the area are represented in Figure 1, shown below:
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`DeSchepper describes a system in which power consumption may be reduced
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`independently for various components of the core and area. For example, in
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`“SLEEP mode” the “clock to the central processing unit is turned off” and in “IDLE
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`mode” the “internal clocks of the CPU, L2 cache memory, data buffers between the
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`processor bus and the PCI bus, and the CPU-PCI bridge are turned off.” Id. at 2:16-
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`19.
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`3.
`Fung ʼ011
`Fung ʼ011 is titled “Apparatus, Architecture, and Method for Integrated
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`Modular Server System Providing Dynamically Power-managed and Work-load
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`Managed Network Devices.” Ex. 1005 at Title. Fung ʼ011 generally teaches
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`“computer system architectures and structures and methods for operating such
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`computer system architectures in a compact high-performance low-power
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`consumption manner.” Id. at 4:65-5:1. According to Fung ʼ011, “data processing
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`systems” and “all manner of electronic systems and devices may utilize and benefit”
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`from the invention disclosed in Fung ʼ011. Id. at 5:1-4.
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`Fung ʼ011 discloses an instruction-processing system with separate voltages
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`supplied to the CPU core and CPU logic. See, e.g., id. at Table II (describing
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`various power-saving modes in which the voltage to the CPU core and core logic are
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`controlled independently). According to Fung ʼ011, the system described could
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`“utilize any of a number of conventional processors or CPUs, and might for example
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`utilize a CPU of the Intel Pentium, Pentium II, Pentium III, or Pentium IV types
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`made by Intel Corporation of Santa Clara, Calif., various Advanced Micro Device
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`CPUs, CPUs made by Transmeta, as well as other processors and CPUs as are
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`known in the art.” Id. at 23:1-8.
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`Moreover, Fung ʼ011 teaches that the separate voltages and CPU clock may
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`be adjusted to enter different “modes” that achieve different levels of power savings.
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`Certain of the modes disclosed by Fung ʼ011 involve reducing the CPU core voltage
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`to a level that is sufficient to maintain the CPU state. Table II below summarizes the
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`various modes described in Fung ʼ011.
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`Id. at Table II; see id. at 34:18-43:39.
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`Although Fung ʼ011 lists several modes and submodes, the specification
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`clarifies that “the inventive system, method, and computer programs do not require
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`eac