Paper No. 1
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`__________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`__________________
`
`
`QUALCOMM INC. AND QUALCOMM TECHNOLOGIES,
`INC.,
`
`Petitioners,
`
`v.
`
`APPLE INC.,
`
`Patent Owner.
`
`
`
`U.S. PATENT NO. 7,760,559
`
`TITLE: INTEGRATED CIRCUIT WITH SEPARATE SUPPLY
`VOLTAGE FOR MEMORY THAT IS DIFFERENT FROM
`LOGIC CIRCUIT SUPPLY VOLTAGE
`
`Issue Date: July 20, 2010
`
`
`PETITION FOR INTER PARTES REVIEW
`UNDER 35 U.S.C. § 312
`
`
`
`

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`TABLE OF CONTENTS
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`
`Page
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`B.
`
`V.
`
`
`Introduction ..................................................................................................... 1
`I.
`II. Mandatory Notices .......................................................................................... 3
`A.
`Real Party in Interest (37 C.F.R. § 42.8(b)(1)) .................................... 3
`B.
`Related Matters (37 C.F.R. § 42.8(b)(2)) ............................................. 3
`C.
`Lead and Back-Up Counsel and Service Information (37 C.F.R.
`§ 42.8(b)(3) and (b)(4)) ........................................................................ 4
`Fees (37 C.F.R. § 42.103) .................................................................... 5
`D.
`III. Grounds for Standing Pursuant to (37 C.F.R. § 104(a)) ................................. 5
`IV. Statement of Precise Relief Requested for Each Challenged Claim .............. 5
`A.
`The Claims for Which Review is Requested (37 C.F.R. §
`42.104(b)(1)) ........................................................................................ 5
`The Specific Statutory Grounds on Which the Challenge is
`Based and Prior Art Relied Upon for Each Ground (37 C.F.R. §
`42.104(b)(2)) ........................................................................................ 6
`Reasons for the Relief Requested Under 37 C.F.R. §§ 42.22(a)(2) and
`42.104(b)(4) .................................................................................................... 7
`A. Overview of the ’559 Patent and its Technology ................................. 7
`B.
`The Prosecution History ..................................................................... 13
`1.
`The Prosecution History of Predecessor U.S. Patent No.
`7,355,905 .................................................................................. 13
`(a) The Daga Patent ............................................................. 14
`(b) The Claim Amendments to Attempt to Overcome
`Daga ............................................................................... 15
`The Prosecution History of Predecessor U.S. Patent No.
`7,474,571 .................................................................................. 17
`The Prosecution History of U.S. Patent No. 7,760,559 ........... 18
`3.
`37 C.F.R. § 42.104(b)(3): Claim Construction ................................. 18
`1.
`A Person of Ordinary Skill in the Art ...................................... 18
`2.
`Construction of Claim Terms ................................................... 18
`
`2.
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`C.
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`-i-
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`TABLE OF CONTENTS
`(continued)
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`Page
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`
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`(a)
`(b)
`
`E.
`
`“integrated circuit” ........................................................ 19
`“receiving power from at least one first / second
`input to the integrated circuit” ....................................... 20
`“during use” ................................................................... 21
`(c)
`D. Overview of the Prior Art ................................................................... 21
`1.
`Clark ......................................................................................... 21
`2.
`Kawata ..................................................................................... 26
`37 C.F.R. § 42.104(b)(4): How the Construed Claims are
`Unpatentable ....................................................................................... 29
`37 C.F.R. § 42.104(b)(5): Supporting Evidence ............................... 29
`F.
`VI. Claims 1–4 of the ’559 Patent are Unpatentable .......................................... 29
`A. Ground 1: Clark Anticipates Claims 1–4 .......................................... 30
`1.
`Independent Claim 1 ................................................................ 30
`(a)
`Preamble – “An integrated circuit comprising:” ........... 30
`(b) Element 1[a] – “at least one logic circuit operating
`in a first voltage domain during use, the first
`voltage domain receiving power from at least one
`first input to the integrated circuit during use; and” ...... 31
`(c) Element 1[b] – “at least one memory circuit
`coupled to the logic circuit, wherein the at least
`one memory circuit comprises a plurality of static
`random access memory (SRAM) cells operating in
`a second voltage domain during use, the second
`voltage domain receiving power from at least one
`second input to the integrated circuit during use;” ........ 33
`(d) Element 1[c] – “wherein the memory circuit is
`configured to be read and written responsive to the
`logic circuit with the first voltage domain having a
`lower voltage than the second voltage domain.” ........... 37
`Dependent Claim 2 .................................................................. 41
`Dependent Claim 3 .................................................................. 42
`
`2.
`3.
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`TABLE OF CONTENTS
`(continued)
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`Page
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`Dependent Claim 4 .................................................................. 43
`4.
`B. Ground 2: Kawata Anticipates Claims 1 and 2 ................................. 44
`1.
`Independent Claim 1 ................................................................ 44
`(a)
`Preamble – “An integrated circuit comprising:” ........... 44
`(b) Element 1[a] – “at least one logic circuit operating
`in a first voltage domain during use, the first
`voltage domain receiving power from at least one
`first input to the integrated circuit during use; and” ...... 46
`(c) Element 1[b] – “at least one memory circuit
`coupled to the logic circuit, wherein the at least
`one memory circuit comprises a plurality of static
`random access memory (SRAM) cells operating in
`a second voltage domain during use, the second
`voltage domain receiving power from at least one
`second input to the integrated circuit during use;” ........ 49
`(d) Element 1[c] – “wherein the memory circuit is
`configured to be read and written responsive to the
`logic circuit with the first voltage domain having a
`lower voltage than the second voltage domain.” ........... 52
`Dependent Claim 2 .................................................................. 54
`2.
`VII. Conclusion .................................................................................................... 56
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`-iii-
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`I.
`
`Introduction
`Pursuant to 35 U.S.C. § 312 and 37 C.F.R. § 42.100 et seq., Qualcomm Inc.
`
`and Qualcomm Technologies, Inc. (collectively, “Petitioners” or “Qualcomm”)
`
`request inter partes review (“IPR”) of claims 1–4 (the “Challenged Claims”) of U.S.
`
`Patent No. 7,760,559 (“the ’559 Patent,” Ex. 1001), which issued on July 20, 2010,
`
`and is assigned to Apple, Inc. (“Apple”).
`
`The ’559 Patent is directed to an integrated circuit having at least one logic
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`circuit and one memory circuit, each of which is supplied by respective first and
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`second supply voltages. Ex. 1001, [57], 2:8–11, 3:26–40, Fig. 1 (disclosing “Logic
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`Circuits 12” supplied by supply voltage VL and “Memory Circuits 14” supplied by
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`supply voltage VM). According to the ’559 Patent, if a single voltage is used to
`
`supply both the logic and memory circuits, then this common supply voltage can be
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`reduced only so far due to memory reliability issues. Id., 1:20–2:4. “As supply
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`voltage decreases below a certain voltage, the ability to reliably read and write the
`
`memory decreases.” Id., 1:47–50; see also id., 2:1–4. The ’559 Patent supposedly
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`improved upon the prior art by using separate supply voltages for the logic and
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`memory circuits. This allows the logic and memory supply voltages to be different,
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`including allowing the logic supply voltage to be lower than the memory supply
`
`voltage in order to further conserve power. Id., 2:53–61, 3:26–40, Fig. 1; see also
`
`Ex. 1002 ¶¶ 31–34 (Clark Decl.).
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`There is nothing, however, patentable about using different supply voltages to
`
`supply a logic circuit and a memory circuit. This feature is disclosed by each of
`
`U.S. Patent No. 6,650,589 to Clark (“Clark”) (Ex. 1003) and U.S. Patent No.
`
`6,920,071 to Kawata et al. (“Kawata”) (Ex. 1004), neither of which were of record
`
`during prosecution of the ’559 Patent. Nor is there anything patentable about the
`
`other aspects of the Challenged Claims, which recite conventional memory and logic
`
`circuitry known to a person of ordinary skill in the art (“POSITA”) as of the
`
`effective filing date of the ’559 Patent. As explained herein, and as supported by the
`
`Declaration of Lawrence T. Clark, Ph.D. (the inventor of the prior art Clark patent)
`
`(Ex. 1002), the Challenged Claims are unpatentable in view of both Clark and
`
`Kawata. See §§ IV, V, and VI, infra.
`
`Notably, during prosecution of a predecessor application to the ’559 Patent
`
`(ultimately issued as U.S. Patent No. 7,355,905, “the ’905 Patent”), the Examiner
`
`found that using a first supply voltage to supply a logic circuit and a second supply
`
`voltage to supply a memory circuit was met by U.S. Patent No. 7,120,061 to Daga
`
`(“Daga”) (Ex. 1005). See § V.B.1, infra (discussing the prosecution history of U.S.
`
`Patent No. 7,355,905). In response, the applicants amended the patent claims of the
`
`predecessor application to recite that the first supply voltage (i.e., the logic supply
`
`voltage VL) and the second supply voltage (i.e., the memory supply voltage VM) are
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`received on respective first and second inputs to the claimed integrated circuit. Id.
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`Based on these amendments regarding where the supply voltages are input to, and
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`received by, the integrated circuit, the Examiner allowed the claims of the
`
`predecessor ’905 Patent. Id. However, these additional features are met by each of
`
`Clark and Kawata, which were not previously considered by the Office. See §§ IV,
`
`V, and VI, infra. And, in co-pending litigation against Qualcomm, Apple has
`
`asserted as a matter of claim construction that the ’559 Patent claims should be
`
`construed such that any supply voltage to the logic circuit or memory circuit is
`
`received on an input to the integrated circuit, even if the second supply voltage is
`
`generated, supplied, input, and received from within the integrated circuit. See
`
`§ V.C, infra.
`
`Because the Challenged Claims are unpatentable, IPR should be instituted and
`
`the Challenged Claims should be cancelled.
`
`II. Mandatory Notices
` Real Party in Interest (37 C.F.R. § 42.8(b)(1))
`Qualcomm Inc. and Qualcomm Technologies, Inc. are the real parties-in-
`
`interest.
`
` Related Matters (37 C.F.R. § 42.8(b)(2))
`The ’559 Patent is involved in the following proceeding that may affect, or be
`
`affected by, a decision in this proceeding: Qualcomm Inc. v. Apple Inc., No. 3:17-
`
`cv-1375 (S.D. Cal.) (“’1375 Case”). The ’559 Patent was previously involved in the
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`following proceedings: Nokia Corp. v. Apple Inc., No. 3:10-cv-249 (W.D. Wis.);
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`Nokia Corp. v. Apple Inc., No. 1:11-cv-15 (D. Del.). Additionally, Qualcomm is
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`concurrently filing separate petitions challenging claims of U.S. Patent Nos.
`
`7,355,905 and 8,098,534, which are in the same family, and share a specification
`
`with, the ’559 Patent.
`
` Lead and Back-Up Counsel and Service Information (37 C.F.R.
`§ 42.8(b)(3) and (b)(4))
`Lead Counsel
`John A. Marlott
`Reg. No. 37,031
`JONES DAY
`77 West Wacker, Suite 3500
`Chicago, Illinois 60601-1692
`(312) 269-4236
`jamarlott@jonesday.com
`
`Back-up Counsel
`Matthew W. Johnson
`Reg. No. 59,108
`JONES DAY
`500 Grant Street, Suite 4500
`Pittsburgh, Pennsylvania 15219-2514
`(412) 394-9524
`mwjohnson@jonesday.com
`
`John M. Michalik
`Reg. No. 56,914
`JONES DAY
`77 West Wacker, Suite 3500
`Chicago, Illinois 60601-1692
`(312) 269-4215
`jmichalik@jonesday.
`
`Thomas W. Ritchie
`Reg. No. 65,505
`JONES DAY
`77 West Wacker, Suite 3500
`Chicago, Illinois 60601-1692
`(312) 269-4003
`twritchie@jonesday.com
`
`Pursuant to 37 C.F.R. § 42.10(b), a power of attorney accompanies this
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`
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`petition. Please address all correspondence to lead and back-up counsel at the
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`addresses above. Qualcomm consents to electronic service by email at the email
`
`addresses listed above.
`
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`Fees (37 C.F.R. § 42.103)
`The undersigned representative of Qualcomm authorizes the Board to charge
`
`the $15,500 petition fee, as well as any additional fees, to Deposit Account 501432,
`
`ref: 178774-680002. Four claims are being reviewed, so $15,000 in post institution
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`fees are due for a total of $30,500.
`
`III. Grounds for Standing Pursuant to (37 C.F.R. § 104(a))
`Qualcomm certifies that the ’559 Patent is available for IPR and that
`
`Qualcomm is not barred or estopped from requesting IPR of the Challenged Claims
`
`on the grounds identified in this petition. Apple filed and served its first amended
`
`answer and counterclaims in the ’1375 Case, first asserting infringement of the ’559
`
`Patent by Qualcomm, on November 29, 2017. Qualcomm has filed this petition
`
`within one year of service of Apple’s first amended answer and counterclaims, and
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`shortly after the District Court issued a claim construction order adopting certain of
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`Apple’s positions regarding the breadth of the ’559 Patent claims.
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`IV. Statement of Precise Relief Requested for Each Challenged Claim
` The Claims for Which Review is Requested (37 C.F.R. §
`42.104(b)(1))
`Qualcomm requests review and cancellation of claims 1–4 of the ’559 Patent
`
`(the “Challenged Claims”).
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`-5-
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`The Specific Statutory Grounds on Which the Challenge is Based
`and Prior Art Relied Upon for Each Ground (37 C.F.R. §
`42.104(b)(2))
`Qualcomm requests IPR of the Challenged Claims on the grounds set forth
`
`below and requests that each of the Challenged Claims be found unpatentable and
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`cancelled. An explanation of how the Challenged Claims are unpatentable is
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`provided in the form of the detailed description that follows, which indicates where
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`each of the claim elements can be found in, and the relevance of, the prior art.
`
`Additional explanation and support for each ground is set forth in Ex. 1002
`
`(Declaration of Lawrence T. Clark, Ph.D.) referenced throughout this petition.
`
`Ground
`Ground 1
`
`
`Ground 2
`
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`Claims
`1–4
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`1–2
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`
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`Basis
`35 U.S.C. § 102 based on U.S. Patent No.
`6,650,589 to Clark (“Clark”)
`
`35 U.S.C. § 102 based on U.S. Patent No.
`6,920,071 to Kawata et al. (“Kawata”)
`
`
`The ’559 Patent issued on July 20, 2010, from U.S. Application No.
`
`12/325,476, which was filed on December 1, 2008. The ’559 Patent claims priority
`
`as a continuation of U.S. Application No. 12/034,071, which was filed on February
`
`20, 2008, and issued as U.S. Patent No. 7,474,571, which is a divisional of U.S.
`
`Application No. 11/173,565, which was filed on July 1, 2005, and issued as U.S.
`
`Patent No. 7,355,905. Accordingly, the effective filing date of the ’559 Patent is
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`July 1, 2005.
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`Clark was filed on November 29, 2001, issued on November 18, 2003, and is
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`prior art under pre-AIA 35 U.S.C. § 102(a)–(b).
`
`Kawata was filed on May 14, 2004, was published on January 6, 2005, as
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`U.S. Patent Application Publication No. 2005/0002224, issued on July 19, 2005, and
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`is prior art under pre-AIA 35 U.S.C. § 102(a), (e).
`
`V. Reasons for the Relief Requested Under 37 C.F.R. §§ 42.22(a)(2) and
`42.104(b)(4)
` Overview of the ’559 Patent and its Technology
`The ’559 Patent is entitled “Integrated Circuit with Separate Supply Voltage
`
`for Memory that is Different From Logic Circuit Supply Voltage.” Ex. 1001, [54].
`
`The ’559 Patent is related to “an integrated circuit compris[ing] at least one logic
`
`circuit supplied by a first supply voltage and at least one memory circuit coupled to
`
`the logic circuit and supplied by a second supply voltage.” Id., [57]. This
`
`arrangement is shown by the embodiment of Figure 1 (with coloring annotations
`
`added):
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`“A block diagram of . . . an integrated circuit 10 is shown” above, with the
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`boundary of the integrated circuit annotated in blue. Id., 2:53–54. “[T]he integrated
`
`circuit includes a plurality of logic circuits 12 and a plurality of memory circuits 14”
`
`that are coupled together. Id., 2:55–57.
`
`As shown by the yellow annotation, “[t]he logic circuits 12 are powered by a
`
`first supply voltage provided to the integrated circuit 10 (labeled VL in FIG. 1).” Id.,
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`2:57–59. As shown by the green annotation, “[t]he memory circuits 14 are powered
`
`by a second power supply voltage provided to the integrated circuit 10 (labeled VM
`
`in FIG. 1).” Id., 2:59–61. Thus, the second supply voltage (VM) supplied to the
`
`memory circuits 14 is different from the first supply voltage (VL) supplied to the
`
`logic circuits 12. Ex. 1002 ¶¶ 34–35.
`
`In this embodiment, the first supply voltage (VL) is also supplied to the
`
`memory circuits 14, as shown by the yellow annotation extending to memory
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`circuits 14. Ex. 1001, 2:61–64. But the first supply voltage (VL) need not be
`
`supplied to the memory circuits 14 in all embodiments. See Ex. 1002 ¶¶ 159–162,
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`264–269 (dependent claim 2). The ’559 Patent describes this as a feature of “certain
`
`embodiments.” Ex. 1001, 2:61–64. For example, independent claim 1 of the ’559
`
`Patent lacks this element, but it is required by dependent claim 2 (“wherein the
`
`memory circuit further comprises one or more additional circuits operating in the
`
`first voltage domain during use”).
`
`The ’559 Patent states that “logic circuits 12 may generally implement the
`
`operation for which the integrated circuit is designed,” which may involve
`
`“generat[ing] various values during operation,” storing values in the memory
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`circuits, and “read[ing] various values from the memory circuits 14 on which to
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`operate.” Id., 3:1–6.
`
`The ’559 Patent states that memory circuits 14 store data. “For example, . . .
`
`the memory circuits 14 may include memory used for caches, register files,
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`integrated-circuit-specific data structures, etc.” Id., 3:6–9. “The memory circuits 14
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`may implement any type of readable/writable memory,” including, for example,
`
`static random access memory (SRAM). Id., 3:9–12. But the memory circuits of the
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`’559 Patent include more than just memory. Ex. 1002 ¶¶ 37–39, 90, 151, 223, 257.
`
`As shown in the memory circuit of Figure 2, for example, the memory circuit may
`
`include a level shifter circuit 20, word line driver circuits 22, and other circuits in
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`addition to memory array 24 where data is stored. Ex. 1001, 3:48–54, Fig. 2. As
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`shown in Figure 3, the memory circuits (which include the memory array) may
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`include bit line driver circuits 30, memory cells 32A-32N, bit line precharge circuits
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`34, bit line hold circuits 36, and senseamps 38. Id., 6:35–38, Fig. 3.
`
`The circuit elements shown in Figures 2 and 3 as part of the illustrated
`
`embodiment of the memory circuit from Figure 1 were conventional and well-
`
`known at the effective filing date of the ’559 Patent. See Ex. 1002 ¶¶ 86, 91, 99–
`
`100, 117, 119, 125, 152, 246 (citing Ex. 1013, at 384; Ex. 1014, at 604–05; Ex.
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`1016, at 313, 570, 574–79; Ex. 1017, at 83–90, 144–54; Ex. 1018, at 143–47).
`
`Among these conventional circuit elements is a “level shifter circuit 20,” which is
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`“configured to level shift an input signal to produce an output signal” by “changing
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`the high assertion of the signal from one voltage to another.” Ex. 1001, 5:14–17.
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`“Level shifting may be performed in either direction (e.g. the voltage after level
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`shifting may be higher or lower than the voltage before level shifting).” Id., 5:17–
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`20. Two embodiments of level shifter circuit 20 are shown in Figures 4 and 5. Id.,
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`8:37–38, 9:54–58, Figs. 4, 5. However, other embodiments are within the scope of
`
`the ’559 Patent. See Ex. 1002 ¶¶ 125, 185, 246 (discussing related ’905 Patent and
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`related ’534 Patent); Ex. 1001, 5:26–40, 6:2–5, 6:20–22, 8:18–22, 9:34–35, 10:13–
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`17.
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`The word line drivers 22 are a second example of conventional circuit
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`elements that may form part of the memory circuit. Ex. 1002 ¶¶ 52, 99, 117 (citing
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`Ex. 1016, at 563–80; Ex. 1017, at 144–54; Ex. 1018, at 143–55). The word line
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`drivers 22 generate a set of word line signals to memory array 24. Ex. 1001, 3:66–
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`4:1.
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`A third conventional circuit element of memory circuits 14 is memory array
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`24. See Ex. 1002 ¶¶ 52, 91, 152 (discussing related ’905 Patent and the ’559 Patent
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`and citing Ex. 1016, at 563–80; Ex. 1018, at 143–55). Figure 3 of the ’559 Patent
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`shows “a circuit diagram of a portion of one embodiment of the memory array 24”
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`of the memory circuit (as shown in Figure 2), which consists of additional
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`conventional circuit elements. See Ex. 1001, 6:30–8:36, Fig. 3. Among these
`
`conventional circuit elements is a “bit line precharge circuit 34,” which precharges
`
`bit lines in preparation for read operations. See id., 6:35–38, 7:38–55; Ex. 1002 ¶¶
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`7, 52, 101, 117 (discussing related ’905 Patent and citing Ex. 1016, at 563–80; Ex.
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`1017, at 144–51, 164; Ex. 1018, at 143–55). “The memory cells 32A-32N [of
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`memory array 24] are supplied with the [second] VM supply voltage” and can be a
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`“typical CMOS SRAM cell.” Ex. 1001, 6:39–40, 6:59–62.
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`By supplying the memory circuit 14 (and its memory array 24) with a supply
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`voltage (VM) that is different than the supply voltage (VL) supplied to the logic
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`circuit 12, these two supply voltages can differ for each type of circuit. Id., 3:26–40;
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`Ex. 1002 ¶¶ 31–34. The logic circuit supply voltage (VL) can be decreased below
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`that of the memory circuit supply voltage (VM) while ensuring that the memory
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`circuit 14 still has a higher supply voltage (VM) that is sufficient for the memory to
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`remain stable. Ex. 1001, 3:26–40; Ex. 1002 ¶¶ 31–34.
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`As discussed herein, a POSITA would have known at the time of the ’559
`
`Patent’s effective filing date that, all things being equal, a circuit’s power
`
`consumption can be reduced by reducing the supply voltage to that circuit. Ex. 1002
`
`¶¶ 53–56; see also Ex. 1001, 1:33–44. A POSITA would also have known at the
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`time of the ’559 Patent’s effective filing date that memory can become unreliable if
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`it is supplied by a voltage that is too low for the circuit’s design. Ex. 1002 ¶¶ 50–56;
`
`see also Ex. 1001, 1:45–2:4. And, a POSITA would have known before the ’559
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`Patent’s effective filing date that the minimum usable voltage for a common supply
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`voltage shared by logic and memory circuits is dependent on the memory circuit.
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`Ex. 1002 ¶¶ 50–56; see also Ex. 1001, 2:1–4. Thus, in order to reduce the power
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`consumed by logic circuitry through reduction of its supply voltage, it was known to
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`a POSITA, and disclosed in the prior art (including Clark and Kawata), to use two
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`different supply voltages to supply logic circuitry and memory circuitry,
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`respectively. See § VI, infra.
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`The Prosecution History
`
`
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`As reflected above, the ’559 Patent claims priority as a continuation of U.S.
`
`Patent No. 7,474,571, which is a divisional of U.S. Patent No. 7,355,905. See
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`Advanced Cardiovascular Sys., Inc. v. Medtronic, Inc., 265 F.3d 1294, 1305 (Fed.
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`Cir. 2001) (“The prosecution history of a related patent can be relevant if, for
`
`example, it addresses a limitation in common with the patent in suit.”); Elkay Mfg.
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`Co. v. Ebco Mfg. Co., 192 F.3d 973, 980 (Fed. Cir. 1999) (“When multiple patents
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`derive from the same initial application, the prosecution history regarding a claim
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`limitation in any patent that has issued applies with equal force to subsequently
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`issued patents that contain the same claim limitation.”).
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`1.
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`The Prosecution History of Predecessor U.S. Patent No.
`7,355,905
`As originally filed, claim 1 in the application that issued as predecessor U.S.
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`Patent No. 7,355,905 (“the ’905 Patent”) recited an “integrated circuit” comprising
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`“at least one logic circuit supplied by a first supply voltage,” “at least one memory
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`circuit coupled to the logic circuit and supplied by a second supply voltage,” as well
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`-13-
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`as other elements. Ex. 1006, at 25. Claim 13 recited a method comprising a logic
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`circuit and memory cell performing certain steps, with the logic circuit and memory
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`cell similarly supplied by different supply voltages. Id., at 27. The Examiner
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`initially rejected these and all other pending claims as anticipated under pre-AIA 35
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`U.S.C. § 102(e) by U.S. Patent No. 7,120,061 to Daga (“Daga”). Id., at 80–84.
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`(a) The Daga Patent
`Figure 3 of Daga is reproduced below, with coloring annotations added.
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`Figure 3 shows a system-on-a-chip 300 having circuitry supplied by two supply
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`voltages, ExtVDD and RegVDD. Ex. 1005, 3:13–24, Fig. 3. RegVDD is a first supply
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`voltage of “for example 1.8V,” which is generated on system-on-chip 300 by
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`voltage regulator 315 and “applied to . . . advanced logic 335” such as the
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`microcontroller 335 shown in Figure 3. Id., 3:18–23, Fig. 3. ExtVDD is a second
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`supply voltage, “for example 3.3V or 5V,” which is “applied to memory 340.” Id.,
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`3:16–18, 3:23–24, Fig. 3.
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`(b) The Claim Amendments to Attempt to Overcome Daga
`The applicants responded to the Examiner’s rejection based on Daga by
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`amending the claims in two ways. First, they amended independent claims 1 and 13
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`of the ’905 Patent application to require that the first supply voltage be “received on
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`a first input to the integrated circuit” and the second supply voltage be “received on
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`a second input to the integrated circuit.” Ex. 1006, at 97, 99. The applicants relied
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`on these claim amendments in their remarks, explaining that “Daga’s integrated
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`circuit has only one power supply input to the integrated circuit (ExtVDD, see Fig.
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`3).” Id., at 103. The applicants further argued: “Thus, Daga fails to anticipate ‘a
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`first supply voltage received on a first input to the integrated circuit; and . . . a
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`second supply voltage received on a second input to the integrated circuit’ as recited
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`in claim 1.” Id. (emphasis by applicants in original).
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`Second, the applicants amended independent claims 1 and 13 to recite that the
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`memory circuit includes a memory array, and the memory array is “continuously
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`supplied by the second supply voltage during use.” Id., at 97, 99. The applicants
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`relied on this new “continuously supplied” language to distinguish their claims from
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`Daga’s disclosures. Specifically, this language was used to distinguish prior art,
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`such as Daga, which uses non-volatile memory. See id., at 102–03; Ex. 1002 ¶ 105.
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`The applicants noted that “Daga teaches a non-volatile memory such as an
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`EEPROM or Flash memory (see, e.g., Daga, col. 3, lines 20-24)” and argued that
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`“[i]n such memories, the memory array does not include memory cells that are
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`continuously supplied with a supply voltage during use.” Ex. 1006, at 102
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`(emphasis by applicants in original). Instead, “the memory arrays are designed to
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`retain values without any power applied (hence the ‘nonvolatile’ nature of such
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`cells).” Id.
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`The applicants referred to Figure 4 in Daga (reproduced below) to further
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`explain this second argument. Id. Figure 4 “is a schematic illustrating one
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`embodiment of the memory from FIG. 3.” Ex. 1005, 2:62–63. The applicants
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`specifically pointed to memory array 430 and argued there are no power supply
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`inputs to the memory array. Ex. 1006, at 102.
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`In comparison, Figure 3 of the ’559 Patent, which is “a circuit diagram of one
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`embodiment of a memory array shown in FIG. 2,” shows that “[t]he memory cells
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`32A-32N are supplied with the VM supply voltage.” Ex. 1001, 2:30–31, 6:39–40,
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`Fig. 3.
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`Based on these claim amendments and two distinguishing arguments
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`regarding the necessity of: (1) two, distinct power supply inputs to the integrated
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`circuit; and (2) memory cells continuously supplied with a supply voltage during
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`use, the Examiner allowed independent claims 1 and 13 (and the corresponding
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`dependent claims) in the form as issued in the ’905 Patent. See Ex. 1006, at 112.
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`2.
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`The Prosecution History of Predecessor U.S. Patent No.
`7,474,571
`The claims of predecessor U.S. Patent No. 7,474,571 were allowed in a first
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`Office Action; the claims were not subject to any rejection by the Examiner. Ex.
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`1020, at 72–76.
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`3.
`The Prosecution History of U.S. Patent No. 7,760,559
`The claims of the ’559 Patent were primarily rejected based on obviousness-
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`type double patenting in view of the ’905 Patent. See Ex. 1019, at 61–63. Two
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`claims (15, 16) were also rejected under 35 U.S.C. § 102(b) as anticipated by U.S.
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`Patent No. 6,181,606. Id., at 62–63. The claims of the ’559 Patent were not
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`otherwise rejected. The applicants submitted a terminal disclaimer to overcome the
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`double-patenting rejection and amended claims 15 and 16 to include the features of
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`another claim (18) that had been indicated as allowable. Id., at 83–93, 99–109, 117–
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`24, 126–30, 134–35, 149–52.
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`37 C.F.R. § 42.104(b)(3): Claim Construction
`1.
`A Person of Ordinary Skill in the Art
`Qualcomm maintains that a POSITA, as of July 1, 2005, would have had a
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`master’s degree in electrical engineering or computer engineering or at least four
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`years of experience in the field of integrated circuit SRAM design, or an equivalent
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`combination of education and experience in this field. Ex. 1002 ¶¶ 46–49.
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`2.
`Construction of Claim Terms
`In this IPR, the claims of the ’559 Patent “shall be given [their] broadest
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`reasonable construction in light of the [’559 Patent’s] specification.” 37 C.F.R.
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`§ 42.100(b). Because a district court applies a different standard, the claim
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`constructions presented in this petition do not necessarily reflect the constructions
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`that Petitioners believe should be adopted by a district court.
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`In the ’1375 Case, the District Court adopted certain of Apple’s claim
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`construction positions. Ex. 1012 (Order Construing Claims), at 3–5. Petitioners
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`have submitted the District Court’s claim construction decision for the Board’s
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`consideration. Power Integrations, Inc. v. Lee, 797 F.3d 1318, 1326–27 (Fed. Cir.
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`2015) (“The fact that the board is not generally bound by a previous judicial
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`interpretation of a disputed claim term does not mean, however, that it has no
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`obligation to acknowledge that interpretation or to assess whether it is consistent
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`with the broadest reasonable construction of the term.”). Although Petitioners
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`reserve the right to appeal or otherwise challenge the District Court’s claim
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`construction order, Petitioners request that the Board in this IPR construe any claim
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`terms at least as broad as the District Court. See, e.g., Cisco Sys., Inc. v. Crossroads
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`Sys., Inc., IPR2014-01463, Final Written Decision, Paper 49, at 11–12 (PTAB, Mar.
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`16, 2016) (“Petitioners argue that the ‘control access’ limitations ‘should be at least
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`as broad as the District Court’s construction . . . .’ We agree with Petitioners . . . .”).
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`(a) “integrated circuit”
`In the ’1375 Case, Apple construed “integrated circuit” to mean “one or more
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`circuit elements that are integrated onto a single semiconductor substrate,” and
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`argued that the claimed “integrated circuit” is not limited to a “chip” or any
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`particular combination of connected circuit elements on a semiconductor substrate.
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`Ex. 1007, at 3–4; Ex. 1008, at 1–2; Ex. 1009, at 4–13, 25–27; Ex. 1010 ¶¶ 23–35;
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`Ex. 1011, at 59–98, 116–18. Apple’s construction does not exclude from the scope
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`of “integrated circuit” a subset of the circuit elements integrated onto a single
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`semiconductor substrate. Ex. 1002 ¶ 58. The District Court adopted Apple’s
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`proposed construction. Ex. 1012, at 3. For purposes of this IPR, Petitioners
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`maintain that Apple’s construction should be accepted as the broadest reasonable
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`interpretation.
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`(b) “receiving power from at least one fir