ADVANCED
`MICROELECTRONICS
`
`'Springer
`
`Qualcomm, Ex. 1017, Page 1
`
`

`

`Springer Series in
`ADVANCED MICROELECTRONICS
`
`5
`
`Springer
`Berlin
`Heidelberg
`New York
`Barcelona
`Hong Kong
`London
`Milan
`Paris
`Singapore
`Tokyo
`
`Physics and Astronomy
`
`ONLINE LIBRARY
`
`http://www.springer.de/phys/
`
`~-
`
`f';
`
`'
`
`'
`
`Qualcomm, Ex. 1017, Page 2
`
`

`

`Springer Series in
`ADVANCED MICROELECTRONICS
`
`Series editors: K. Itoh, T. Sakurai
`
`The Springer Series in Advanced Microelectronics provides systematic information on
`all the topics relevant for the design, processing, and manufacturing of microelectronic
`devices. The books, each prepared by leading researchers or engineers in their fields,
`cover the basic and advanced aspects of topics such as wafer processing, materials,
`device design, device technologies, circuit design, VLSI implementation, and subsys(cid:173)
`tem technology. The series forms a bridge between physics and engineering and the
`volumes will appeal to practicing engineers as well as research scientists.
`
`1 Cellular Neural Networks
`Chaos, Complexity and VLSI Processing
`By G. Manganaro, P. Arena, and L. Fortuna
`2 Technology of Integrated Circuits
`By D. Widmann, H. Mader, and H. Friedrich
`3 Ferroelectric Memories
`By J. F. Scott
`4 Microwave Resonators and Filters for Wireless Communication
`Theory, Design and Application
`By M. Makimoto and S. Yamashita
`5 VLSI Memory Chip Design
`ByK. Itoh
`
`Series homepage - http://www.springer.de/phys/books/ ssam/
`
`Qualcomm, Ex. 1017, Page 3
`
`

`

`Kiyoo Itoh
`
`VLSI
`Memory Chip Design
`
`With 416 Figures and 26 Tables
`
`..
`
`•
`
`Springer
`
`Qualcomm, Ex. 1017, Page 4
`
`

`

`Dr. Kiyoo Itoh
`Hitachi Ltd., Central Research Laboratory
`1-280, Higashi-Koigakubo
`Kokubunji-shi
`Tokyo185-8601
`Japan·
`e-mail: k-itoh@crl.hitachi.co.jp
`
`Series Editors:
`
`Dr. Kiyoo Itoh
`Hitachi Ltd., Central Research Laboratory
`1-280 Higashi-Koigakubo
`Kokubunji-shi
`Tokyo 185-8601
`Japan
`
`Professor Takayasu Sakurai
`Center for Collaborative Research
`University of Tokyo
`7-22-1 Roppongi, Minato-ku,
`Tokyo 106-8558
`Japan
`
`Library of Congress Cataloging-in-Publication Data
`
`ltoh, Kiyoo, 1941-
`VLSI memory chip design/ Kiyoo Itoh.
`p. cm. -- (Springer series in advanced microelectronics ; 5)
`Includes bibliographical references and index.
`ISBN 3540678204 (alk. paper)
`1. Semiconductor storage devices--Design and construction. 2. Integrated
`circuits--Very large scale integration--Design and construction. I. Title. II. Series.
`
`TK7895.M41876 2001
`62 l .39'732--dc2 l
`
`00-068735
`
`ISSN 1437-0387
`ISBN 3-540-67820-4 Springer-Verlag Berlin Heidelberg New York
`
`This work is subject to copyright. All rights are reserved, whether the whole or part of the material is
`concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting,
`reproduction on microfilm or in any other way, and storage in data banks. Duplication of this publication or
`parts thereof is permitted only under the provisions of the German Copyright Law of September 9, 1965, in its
`current version, and permission for use must always be obtained from Springer-Verlag. Violations are liable
`for prosecution under the German Copyright Law.
`
`Springer-Verlag Berlin Heidelberg New York
`a member of Springer Science+ Business Media
`
`http://www.springer.de
`
`© Springer-Verlag Berlin Heidelberg 2001
`Printed in Germany
`The use of general descriptive names, registered names, trademarks, etc. in this publication does not imply,
`even in the absence of a specific statement, that such names are exempt from the relevant protective laws and
`regulations and therefore free for general use.
`
`Typesetting by the author.
`Data conversion and figure processing by LE-TEX Jelonek, Schmidt & Vocl<ler GbR, 04229 Leipzig.
`
`Cover concept by eStudio Calmar Steinen using a background picture from Photo Studio "SONO". Courtesy
`of Mr. Yukio Sono, 3-18-4 Uchi-Kanda, Chiyoda-ku, Tokyo.
`Cover design: design & production GmbH, Heidelberg
`57/ 3m - 5 4 3
`
`Printed on acid-free paper
`
`SPIN: 11691914
`
`Qualcomm, Ex. 1017, Page 5
`
`

`

`: to be di(cid:173)
`l) as
`
`DD « 1 is
`
`,0% point
`; is about
`
`ents [2.3].
`:1 is given
`)wer (P2)
`at t 1 and
`n VTN to
`1aveform,
`
`2.6 Basic Memory Circuits
`
`83
`
`2.6 Basic Memory Circuits
`
`· 2.6.l The Inverter and the Basic Logic Gate
`
`Figure 2.33 shows cross-sections of basic NMOS and CMOS inverters [2.1] .
`. Figure 2.34 illustrates logic diagrams, truth tables, circuits, and layouts for
`a typical logic gate used in a memory chip [2.1]. A small circle is added at
`the output in the logic diagram if the logic input is inverted at the output.
`The circle is omitted for a non-inverted logic gate, as exemplified by two
`serially-connected inverters.
`
`2.6.2 The Current Mirror
`
`Figure 2.35 shows a current mirror [2.1]. If both Q1 and Q2 are in saturation,
`Ji = (,Bi/2)(Va - VT )2 , 12 = (,B2/2)(Va - VT )2 ;
`:. h/li = ,82/,81 = W2/W1.
`(2.35)
`, Hence, if 11 is supplied from a constant-current generator, a constant current
`h multiplied by W2/W1 is available.
`
`2.6.3 The Differential Amplifier
`
`The differential amplifier is indispensable for detecting a small signal in
`a noisy environment, as discussed in Chap. 3. It can• be categorized as
`a normal differential amplifier or a cross-coupled differential amplifier. The
`former simply amplifies a small signal, with a separated input and output.
`A good example is the current-mirror amplifier, which has been used as a main
`amplifier on common I/0 lines of DRAMs and SRAMs. The latter amplifies
`a small signal to Vnn and latches the amplified signal at the input. It has
`been widely used for DRAMs because of its simple circuit configuration, low
`power, and suitability for rewrite operations.
`
`in out Voe
`
`s in the
`
`.. '
`
`p-sub
`
`p-sub
`
`(a)
`
`(b)
`Fig. 2.33. The NMOS inverter (a) and the CMOS inverter (b) [2.1]
`
`Qualcomm, Ex. 1017, Page 6
`
`

`

`84
`
`2. The Basics of RAM Design and Technology
`
`~yg~cbol
`
`logic diagram
`
`circuit
`
`layout
`
`in~out
`A---v--F
`
`NOT
`
`F=A
`
`Al
`
`f
`I
`
`-
`
`I
`
`Vss
`
`out F
`
`contact
`
`PMOS
`
`L
`
`,,..-
`
`Al
`
`NMOS
`
`~
`
`~ ~1 +
`
`.fl p-:
`
`Voo
`
`,,--
`
`r - - - ,
`
`I
`
`B I
`
`---~
`iJ y-Si
`
`pol
`
`I
`
`- ~ ~
`~ ~1
`I 181
`
`A
`
`B
`
`A
`
`B
`
`NANO
`
`F=A•B
`
`A B F
`1 1 0
`1 0 1
`0 1 1
`0 0 1
`
`NOR
`
`F =A+B
`
`A B F
`1 1 0
`1 0 0
`0 1 0
`0 0 1
`
`Vss
`
`VDD
`
`F
`
`in
`A
`
`I
`
`B I
`
`Vss
`
`1181 ~
`
`-
`Vss
`
`out F
`
`1...-
`Voo
`
`PMOS
`N~OS
`Al
`~ ~
`
`~
`
`I 181 181
`
`~ ~I
`
`181 I
`I~ 181
`
`~
`
`Vss
`
`1~
`
`-
`L
`out F
`
`IL...,_
`
`Voo
`
`ly-Si
`
`~
`
`I
`
`Fig. 2.34. Typical logic gates [2.1]
`
`The Current-Mirror Amplifier. Figure 2.36 shows a basic current-mirror
`amplifier [2.1] with two input terminals for a differential input and one output
`terminal (i.e. a single-ended output). The load MOSFETs Qs and Q4 form
`a current mirror. All MOSFETs are biased to be in saturation. Therefore, Q5
`works as a constant-current (Is) source. If the sizes of the paired MOSFETs
`(Q1 and Q2, and Qs and Q4) are the same and the differential input is O V
`(i.e. the same input voltage), a current of half of Is flows equally to the Q3 -
`
`[
`
`Qualcomm, Ex. 1017, Page 7
`
`

`

`2.6 Basic Memory Circuits
`
`85
`
`p
`'
`
`VG-----,
`
`Fig. 2.35. The current mirror
`
`Voo
`
`out
`
`f--<> in
`
`Is t
`
`f--<> V
`
`Fig. 2.36. A current-mirror differential amplifier [2.1]
`
`I
`I
`
`1~
`
`Q1 path and the Q4-Q2 path. The voltage gain [2.4] for a small differential
`input is given by
`G = rgm,
`where r is a resistance composed of the parallel-connected output resistances
`of Q1 and Q3 or Q2 and Q4, and 9m is the transconductance of Q1 or Q2,
`The resistance r is derived from (2.12) as
`r = [l/r(Q1) + 1/r(Qg)J-1 =[(AN+ Ap)losJ-1
`= [(AN+ Ap )Is/2J-1 ,
`where AN and Ap are the channel-length modulation parameters for the
`NMOSFET and the PMOSFET, respectively. The transconductance 9m is
`derived from (2.11) as
`
`(2.36)
`
`(2.37)
`
`9m = ~Ios/~VGs ~ Jis(Wi/L)f3No
`(2.38)
`where W1 and f3No are the channel width and /30 value of Q1 . The gain G
`is large because both r and 9m are large. For example, G = rgm = 14 kO x
`2.2 mS = 31 for AN = 0.04 v-1, Ap = 0.1 v-1, Is = 1 mA, Wi/ L = 100, and
`f3No = 5 x 10- 5 S/V.
`
`contact
`
`Voo
`
`~urrent-mirror
`µd one output
`~and Q4 form
`', herefore, Q5
`'.·d MOSFETs
`;input is av
`r,
`' .. to the Q3-
`
`Qualcomm, Ex. 1017, Page 8
`
`

`

`86
`
`2. The Basics of RAM Design and Technology
`
`in
`
`in
`
`Voo
`
`out
`
`out
`
`Fig. 2.37. A
`
`0
`
`differential output current-mirror amplifier [2.1]
`
`DL
`,--------(cid:173)
`' ' '
`' ' c~
`' ' ' ' '
`
`. . . . .
`--------,
`=::C . . . . . .
`
`Fig. 2.38. A cross-coupled amplifier [2.1]
`
`DL
`
`N.
`
`0
`
`0
`
`In the design of a differential amplifier, the channel lengths of Q 1 and Q2
`are chosen to be large to reduce the offset voltage, which is the difference in
`VT between the two MOSFETs, since the offset voltage works as a noise. The
`resultant offset voltage is usually 20 m V [2.10]. The current-mirror amplifier
`has the advantages of high speed and an excellent common-mode rejection
`ratio. However, the voltage gain is still small, because the diode connection
`of Q4 prevents the Q4 drain from taking a large voltage swing. The single(cid:173)
`ended output is also a problem. These problems are solved by the use of
`a differential-output current-mirror amplifier [2.1], as shown in Fig. 2.37.
`The amplifier effectively doubles the signal swing at the output and enables
`a differential connection to the succeeding differential circuit.
`The Cross-Coupled Amplifier. Figure 2.38 shows an NMOS cross-coupled
`amplifier [2.1]. A differential small signal v 5 , developed between a pair of data
`lines, on a floating Voo is amplified to Voo by applying an activation pulse
`
`Qualcomm, Ex. 1017, Page 9
`
`

`

`2.6 Basic Memory Circuits
`
`87
`
`¢. Here, the amplification starts when ¢ reaches Vnn - VT and Q2 is turned
`on. Then, DL continues to be discharged, leaving DL at Vnn- In practice,
`a CMOS amplifier consisting of cascaded NMOS and PMOS cross-coupled
`amplifiers has been used exclusively as a sense amplifier on each pair of data
`lines in modern CMOS DRAMs.
`
`2,6.4 The Voltage Booster
`
`Node boosting, by means of a MOS capacitor that easily offers a large ca(cid:173)
`pacitance, eliminates the reduction in VT, as discussed previously, and even
`generates an increased quasi-de power-supply voltage.
`Gate Boosting. Gate boosting is important not only for the bootstrap
`inverter, but also for the DRAM word drivers [2.1] shown in Fig. 2.39. Only
`one of a number of word lines is selectively activated by the decoders. For
`example, the switches are off after applying Vnn only to the selected Q1 gate
`and O V to other non-selected gates such as the Q2 gate. The succeeding
`application of a Vnn pulse to the common terminal RX enables a Vnn pulse
`to be outputed only to WL1, leaving WL2 at O V. The full Vnn pulse at WL1
`is due to a sufficient boosting of the Q1 gate, to about 2Vnn, if the parasitic
`capacitance at the gate is negligible, due to a large gate-drain capacitance
`Can (Fig. 2.9). On the other hand, the small Can of Q2 keeps the gate, and
`thus WL2, at O V despite the application of the RX pulse.
`The Increased Power Supply. An increased quasi-de power supply from
`a voltage up-converter is indispensable in modern DRAMs for the generation
`of a high-speed, well-controlled increased pulse, as discussed in Chap. 4. The
`basic idea for the power-supply generation is to use a charge pump with MOS
`capacitors.
`Figure 2.40 shows the concept of the charge pump [2.1]. Nodes N1 and N2
`are charged to Vnn - VT in the quiescent state. The application of a pulse
`
`VDD o---o/4
`
`v.oo I
`
`: G
`C .J.
`' '
`
`•j•
`
`0
`
`VDD J
`
`.____._____ WL 1
`
`0 o---o/4 __ 0_-l
`
`0
`.____. _____ Wl.2
`
`Fig. 2.39. Word-line selection by
`a MOS capacitor [2.1]
`
`and Q2
`rence in
`ise. The
`mplifier
`ejection
`.nection
`: single(cid:173)
`: use of
`g. 2.37.
`enables
`
`coupled
`of data
`,n pulse
`
`Qualcomm, Ex. 1017, Page 10
`
`

`

`88
`
`2. The Basics of RAM Design and Technology
`
`Voo
`
`N1
`
`Voo
`
`p 0
`
`(1+a)Voo-Vr
`
`N, Voo-Vr
`
`N2 Voo-Vr
`
`6
`I
`.,,, t
`
`6+6'
`
`* t
`
`____ _17__
`
`(1+a)Voo-Vr
`
`____ SL_
`
`s ' I
`
`(1 +a)Voo-2Vr
`
`Fig. 2.40. The charge pump [2.1]
`
`to P increases N1 to (1 + a) Voo - VT where a is the boost ratio, which
`is determined by Cp and the N 1 parasitic capacitance. Thus, Qo is turned
`on and N 1 is charged up. This implies that part of charges (i.e. Cp V00 )
`injected to N 1 by Cp is transferred to N 1 . However, the charging stops when
`the voltage difference between N1 and N2 reaches VT. The resultant voltage
`change 8 at N 1 is small because, usually, CL » Cp. When the pulse is turned
`off, N1 instantaneously drops to below Voo - VT, and then it is charged up
`again to Voo - VT by Q1 . In this manner, successive pulse applications to P
`allow N2 to continue to be charged and raised. When N2 reaches (l+a)V00 -
`2VT, however, N2 stops being charged, thereafter enabling to hold a stable
`raised voltage on CL. If there is a pulsive load current at CL, the increased
`voltage would be degraded. In this case, Q0 would again continue to charge
`up CL until the resultant voltage reached a stable level. The stable level is
`7.5 V for Voo = 5 V, VT= 0.5 V, and a= 0.8. The time necessary to reach
`the stable voltage depends on Cp, CL, and the pulse frequency. The pulse
`can be generated by a ring oscillator.
`
`2.6.5 The Level Shifter
`
`Figure 2.41 shows a level shifter [2.1], to shift from a low-level (Von) pulse to
`a high-level (VoH) pulse. Since either of the cross-coupled PMOSFETs may
`be turned on, depending on the input, there is no ratio operation with an
`NMOSFET. VoH is generated by the charge pump.
`
`2.6.6 The Ring Oscillator
`
`Figure 2.42 shows a ring oscillator comprising odd-stage inverters [2.1]. It
`is used for charge-pumping in a voltage up-converter and in substrate-bias
`
`Qualcomm, Ex. 1017, Page 11
`
`

`

`2.6 Basic Memory Circuits
`
`89
`
`VoH (>Voo)
`
`Fig. 2.41. A level shifter [2.1]
`
`fosc
`
`>1
`
`1•
`
`2n+1 stages
`
`ring oscillator
`
`buffer
`
`(2n+ 1) (tH+tL)
`
`1-E
`>I
`n (tH+tL) + tH
`
`Fig. 2.42. A ring oscilla(cid:173)
`tor [2.1]
`
`generators. In addition, it is indispensable in the control of the DRAM refresh
`time, via µs - ms interval pulses that are generated with the help of counters.
`The oscillation frequency Jose [2.1] is given by [(2n + l)(tH + t1)J- 1 , where
`2n + 1 is the number of inverter stages, and tH and t1 are the delay times of
`each inverter for a high-input and low-input pulse, respectively.
`
`2.6.7 The Counter
`
`The counter monitors the number of pulses. It is well known that an address
`counter counts up the number of refresh operations, to select the refresh word
`lines in order. Another application to DRAMs is the refresh timer, which
`
`I I
`
`1 __
`
`1
`o-VT
`
`L_
`
`, which
`turned
`]pVno)
`>S when
`voltage
`turned
`rged up
`ns to P
`:)Voo (cid:173)
`t stable
`creased
`charge
`level is
`o reach
`"e pulse
`
`mlse to
`rs may
`vith an
`
`2.1]. It
`tte-bias
`
`Qualcomm, Ex. 1017, Page 12
`
`

`

`90
`
`2. The Basics of RAM Design and Technology
`
`counts the number of pulses from a ring oscillator and generates a desired
`pulse frequency corresponding to a refresh interval.
`
`I i
`
`2. 7 The Scaling Law
`
`The performance of the LSI chips is improved by the scaling down of design
`parameters such as the device size, impurity and threshold voltages of the
`MOSFETs, and the operating voltage [2.1, 2.18] . The scaling under a cons(cid:173)
`tant electric field shown in Table 2.4 is well-known as ideal scaling. There
`have been other two scalings that are modifications of ideal scaling; constant
`supply-voltage scaling and the combined scaling of the above two kinds [2.1] .
`
`Table 2.4. The impact of the VDC approach on CMOS chip performance under
`a fixed Voo
`
`Conventional approach VDC approach
`Voo
`I 001
`' f - -~
`
`core circuits
`
`core circuits
`
`chip
`
`Performance
`External voltage, Voo
`Internal voltage, ½NT
`FET dimensions, Li, w i, tox , Xj
`Electric field for FETs, E
`FET current, I8si
`Power dissipation, loo V~o
`On resistance, Roni = ½NT / Josi
`Delay, Tc = Roni CGi
`Circuit area
`a Josi = (Wi / Li) / (½NT - VT )2 / tox(cid:173)
`b loo = ~ Iosi-
`ccGi ex LiWd tox-
`
`1
`1/k (k > 1)
`1/k
`1
`1/k
`1/k
`1
`1/k
`1/k
`
`2. 7.1 Constant Electric-Field Scaling
`
`In this scaling method [2.1, 2.18], the physical size and threshold voltage
`VT of the MOSFET, the wiring (i.e. interconnection) in Fig. 2.43, and the
`power supply Voo are scaled down by a factor k(> 1). The substrate doping
`concentration N of the MOSFET is increased by the same factor. This is due
`
`Qualcomm, Ex. 1017, Page 13
`
`

`

`144
`
`3. DRAM Circuits
`
`3.6.2 The Address Decoder
`
`Major concerns for the address-decoder block are power dissipation, speed,
`and area, because the block includes a huge number of circuits and occupies
`quite a large segment of the chip.
`There are two kinds of decoder; row decoders and column decoders. In
`DRAM design, unlike SRAM designs, the circuit configurations of the two
`are totally different. Each row decoder must be a dynamic circuit, while each
`column decoder can be a static circuit, as explained previously. Note that
`to precharge all the row decoders without any de current path, all of the
`complementary addresses are fixed at a low level during a precharge period,
`as shown in Fig. 3.42.
`Figure 3.44 shows dynamic and static decoders, exemplified by two-bit
`address signals. There are two kinds of dynamic decoder in DRAM appli(cid:173)
`cations; NOR and NANO decoders. First, all of the output nodes (X0-X3 )
`are precharged to Vnn by transistors Qp, while keeping all addresses low.
`Then, according to the succeeding valid address signals, the output nodes
`are discharged or kept high. Obviously, in NOR decoders all output nodes
`except for a selected one are discharged, while in NANO decoders all output ·
`nodes except for a selected one are kept high. Thus, NOR decoders suffer
`from a drawback of the large charging and discharging power. The power
`increases with memory capacity, because an increased number of the nodes
`- for example, a few thousands, for multimegabit DRAMs - is involved. On
`the other hand, in N AND decoders only one node is discharged or charged
`up, independently of memory capacity. NA.ND decoders, however, suffer the
`drawback of a slower speed, because the node is discharged by serially con(cid:173)
`nected (i.e. stacked) transistors. The number of stacked transistors is also
`limited by the body effect of the transistor. Static NANO decoders for the
`column are simple, as shown in Fig. 3.44c.
`Figure 3.45 shows applications of dynamic decoders to the row and static
`decoders to the column. In dynamic decoders, a word line WL is activated by
`an RX pulse that is applied after the decoder output Xi has been settled. In
`the selected decoder, the Qw gate-drain (i.e. RX terminal) capacitance Ceo
`is large, because the Qw gate stays at the high level of Von - VT. Thus, an
`RX pulse positively going from O V to Vnn can boost the Qw gate voltage.
`The boost ratio is large, because a diode Qn isolates the Qw gate from the
`node Xi capacitance. Due to the resulting boosted gate voltage, to higher
`than Vnn + VT, the word line is quickly driven to Vnn, In the non-selected
`decoders, an RX pulse application never raises the Qw gate voltages, since
`the gate voltages are O V and thus their Gen values are almost zero. For
`NOR decoders, even the heavily capacitive Qw gate is quickly discharged
`by at least one transistor of the decoder. For NANO decoders, however, to
`accomplish rapid decoding, Qw is driven with the help of a small CMOS
`inverter, whose input capacitance is small enough to be quickly driven even
`by stacked transistors. Despite the area penalty, the inverter added to each
`
`Qualcomm, Ex. 1017, Page 14
`
`

`

`3.6 Read and Relevant Circuits
`
`145
`
`Xo
`
`X1
`
`X2
`
`X3
`
`(a}
`
`Voo
`
`Xo
`
`X1
`
`X2
`
`X3
`
`,
`
`(b)
`
`Xo
`
`ao
`
`a,
`
`(c)
`
`PR 7
`
`ao, ao
`a,,a,
`
`Xo-X3
`
`PR 7
`ao, ao
`a1,a1
`
`Xo-X3
`
`j
`
`ao a,
`0
`0
`1 0
`0 1
`1 1
`
`j
`
`ao a,
`0
`0
`1 0
`0 1
`1 1
`
`' ~
`
`Xo X1
`1 0
`1
`0
`0
`0
`0 0
`
`X2 X3
`0
`0
`0
`0
`1 0
`1
`0
`
`i
`
`~
`
`Xo X1
`1 1
`1 1
`1 0
`0 1
`
`X2 X3
`1 0
`1
`0
`1 1
`1 1
`
`ao a,
`0 0
`1 0
`0 1
`1 1
`
`Xo X1
`1 1
`1 1
`1 0
`0 1
`
`X2 X3
`1 0
`1
`0
`1 1
`1 1
`
`Fig. 3.44. Decoders and operations, exemplified by two address bits [3.4].
`(a) Dynamic NOR; (b) dynamic NAND; (c) static NAND
`
`decoder never increases the decoder power because it is a CMOS inverter. The
`reason why NMOS NOR decoders have been replaced by CMOS NAND deco(cid:173)
`, ders since the 1 Mb generation is just to reduce the ever-increasing decoder
`
`speed,
`cupies
`
`~rs. In
`ie two
`e each
`e that
`of the
`,eriod,
`
`wo-bit
`appli(cid:173)
`o-X3)
`slow.
`nodes
`nodes
`,utput
`suffer
`power
`nodes
`d. On
`Larged
`er the
`r con(cid:173)
`s also
`)r the
`
`static
`;ed by
`ed. In
`1Can
`us, an
`,ltage.
`m the
`1igher
`lected
`since
`}. For
`arged
`er, to
`:Mos
`, even
`. , each
`
`Qualcomm, Ex. 1017, Page 15
`
`

`

`146
`
`3. DRAM Circuits
`
`Voo
`
`RX
`
`J_ ch
`
`L
`
`(word driver)
`
`PR o---1
`
`X;
`
`rl ~
`
`(a)
`
`Voo
`
`RX
`
`ch
`
`L
`
`(word driver)
`
`PR o---1
`
`a;o---1
`
`ai o--J
`
`(b}
`
`(Y driver)
`
`(c)
`Fig. 3.45. Applications of decoders to word and column drivers [3.4]. (a) Dynamic
`NOR; (b) dynamic NAND; (c) static NAND
`
`power. Even for a small memory capacity chip of 1 Mb, CMOS NAND deco(cid:173)
`ders have reduced the decoder power down to 4% of that needed for NMOS
`NOR decoders (3.7, 3.23] as shown in Fig. 3.17. However, to improve the
`performance of CMOS NAND decoders further, it is essential to reduce the
`number of stacked transistors. This is realized by predecoding schemes [3.21],
`as follows.
`A predecoding scheme achieves a faster decoding and area reduction
`of a decoder while reducing the number of stacked transistor in a CMOS
`NAND decoder. In addition, it reduces the input capacitance and the neces(cid:173)
`sary address input lines of the decoder. Figure 3.46 compares predecoding
`schemes [3.4]. Direct decoding, 2 bit predecoding, and 3 bit predecoding are
`shown in Figs. 3.46a-c, respectively. A circle in the figures denotes a tran(cid:173)
`sistor connection. For example, when a high level is applied to a0 and a1
`in Fig. 3.46a, decoders X0 , X4 , and X8 are selected as a result of NAND
`decoding. Each 2 bit predecoder can select one of four address input lines
`coming to the decoders by using two sets of complementary addresses from
`two address buffers, while each 3 bit predecoder can select one of eight address
`input lines by using three sets of complementary addresses. Here, let us cite
`an example of a total external address bits of 6 bits (Ao-A5 ). The numbers
`of address lines to the decoders for direct decoding, 2 bit decoding, and
`3 bit decoding are 12, 12, and 16, respectively. The numbers of transistors
`
`.,
`
`Qualcomm, Ex. 1017, Page 16
`
`

`

`3.6 Read and Relevant Circuits
`
`147
`
`AB
`
`pre-dee
`
`AB
`
`pre-dee
`
`-----+--tH1-1--ff¼-- Xo
`-----+--tHH-H--+--X1
`---+1+-+--+---+++-- X2
`- - ~ - -+ - - Xa
`-----+1--41'~--+++-- X4
`--+-++<>-+++--+-- Xs
`--+++-+--+--+++-- Xs
`--tt-r-t---ttt-+-- X1
`--t--tr.~-ttt-- Xe
`81 a1 ao ao
`
`-.-..--+--+-4H+--,i---+-+--ff¼-- Xo
`-.-..--+--+-4H+--,i---+---fH--+-- X1
`-.-..-1---+-4H+--,~1--+--+-- X2
`-.-..--+--+-4fR-fiir-+-+--+-- Xa
`-.-..-1---A-¼-+----,i---+-+--f+¼-- X4
`--++1--+--+-+++--+----,>--+--++t---+-- Xs
`--++1--+--+-+++--+----,>-<+,>--+---+-- Xs
`---ttt----t---t--ttt--~ir-+----t---t-- X1
`---ttt----t--ttt--+--+--ii---+----t--ttt-- Xe
`
`-----+--#11-1--+--+--~~--1---+++-- Xo
`-----+--#11-1--+--+--~~~--+-- X1
`-----+--#11-1--+--+--~~~--+-- X2
`-----+~1-1--+--+--~~--1---+-- Xa
`-----+~1-1--1-~-~--1---+-- X4
`--t-til>-t---t-ttt-+--t--+-+-+-- Xs
`--t-til>-t--ttt--+--+--t--+-+-+-- Xs
`--t--ttt--ttt--+--+-+---it--+-+-+-- X1
`---ttt--t->-t--+--+-+---it--+-+-ttt-- Xe
`
`a'e a'1 a's a's a'4 a'a a'2 a'1 a'o
`
`(b)
`
`(c)
`
`Fig. 3.46. Predecoding [3.4]. (a) no predecoding; (b) 2-bit predecoding; (c) 3-bit
`predecoding
`
`connected to each address line are 32, 16, and 8, and the numbers of tran(cid:173)
`sistors consisting of each decoder are six, three, and two, in the same order.
`Hence, the predecoding schemes achieve a higher speed with reduction of
`the address-line capacitance and the number of stacked transistors needed
`for each NAND decoder, given an acceptable number of address lines. They
`also reduce the decoder area. The resulting improvement in speed offsets an
`additional delay caused by the predecoders. Here, predecoding schemes with
`more than 4 bits are not practical because of a rapid increase in the number
`of address lines.
`Figure 3.47 shows a reduction in the delay of an address line [3.24], which
`is an example of the buffer insertions shown in Fig. 3.20. Quite a long de(cid:173)
`lay time is developed, despite the aluminum address line, because the line
`becomes resistive and capacitive due to fine patterning, and is loaded by
`the distributed gate capacitances of the decoder transistors, as shown in
`Fig. 3.47a. However, the delay is reduced by the multidivided decoder shown
`in Fig. 3.47b. The resulting block decoder is driven by a buffer. Each block is
`constructed so as to correspond to a subarray and only one block is selectively
`activated by the subarray activation pulse <Pi.
`
`3.6.3 The Word Driver
`
`A word driver needs to be designed carefully - more so than a column driver -
`because its load has the following unique features:
`
`l. A Boosted Word Voltage. The need for a boosted word voltage, for full
`write and read operations, means that row decoders and word drivers
`
`1 ·
`
`!
`iL
`
`lw
`
`WL
`')
`
`nic
`
`co-
`8S
`;he
`;he
`:1),
`
`on
`)S
`es(cid:173)
`ng
`tre
`m(cid:173)
`a1
`lD
`1es
`>m
`~ss
`ite
`ffS
`nd
`>rs
`
`Qualcomm, Ex. 1017, Page 17
`
`

`

`148
`
`3. DRAM Circuits
`
`Ai
`
`ai
`
`address line
`
`. . . .
`
`n decoders
`
`block select
`<l>o
`
`<I>,
`
`address line
`
`q> 1-1
`
`Ai
`
`ai
`
`block address line
`
`. . . .
`
`decoder block
`Blo
`
`BL1
`
`BL1-1
`
`Fig. 3.47. The delay reduction of an address line running on decoders (upper) by
`insertion of buffers (lower) [3.4, 3.24)
`
`have complicated designs. On the other hand, column-relevant circuits,
`such as column decoders and drivers, do not need any boosting. Even
`without boosting, an amplified signaJ voltage from a data line can be
`transmitted to the I/O line, and a data-input voltage of Vnn can be fully
`transmitted from the I/O line to the data line with the help of the CMOS
`sense amplifier.
`2. A Large Word-Line Capacitance and Resistance. The electrical charac(cid:173)
`teristics of a word line differ from those of column line YL in the sha-
`red Y decoder scheme. Word-line capacitance is quite heavy, because of
`connections with many memory cells. On the other hand, column-line
`capacitance is light, because a small number of transistors, equal to the
`number of data-line divisions (i.e. q in Fig. 3.14), are connected to a YL
`line. Thus, a larger word driver is needed. As for line resistance, there is
`also a large difference between the two. A word line made of poly-Si or
`polycide is resistive for a folded data-line cell, while a column line is made
`of aluminum.
`3. Loss of Stored Information. If the stored charges of a non-selected cell
`are allowed to escape to a data line through the transfer transistor, the
`refresh time or S /N ratio of the cell is degraded, as discussed in Chap. 4.
`Thus, noise suppression is essential on non-selected word lines. Moreover,
`to avoid loss of stored information, data-line precharging must be started
`after completely turning off the word pulse. Such considerations are not
`
`1
`
`Qualcomm, Ex. 1017, Page 18
`
`

`

`3.6 Read and Relevant Circuits
`
`149
`
`needed for the column. Here, an explanation of the column driver is omit(cid:173)
`ted in what follows, because the driver is almost the same as in Fig. 3.45.
`
`A Basic Word Driver. Figure 3.48 shows the basic unit of conventional
`word drivers [3.13, 3.21, 3.23). Each word line is divided into two, to reduce
`word-line delay (see Fig. 3.40), and the resulting divided word line has its
`own word driver, Qw. Since a CMOS NAND decoder cannot be placed at
`a tight word-line pitch, it is shared with two sets (left and right) of four word
`drivers, although only the right section is shown in the figure. Address signals
`Xj and Xk are inputted from 2-bit predecoders to the decoder. Each of the
`four word drivers selected by the decoder is selectively driven by decoded
`row select lines RX (RX0-RX3), enabling the corresponding word line to be
`driven. The RX drivers in Fig. 3.48b provide a boost word voltage to one
`of RXs as a result of two-address bit (ao, a1) decoding, as follows. At first,
`node WDL is precharged almost to Vnn during the precharge period (i.e.
`RP : H) and all address signals and thus all RX lines are fixed at O V. When
`_ the addresses have been valid after starting activation with RP: L, a clock
`4>8 generated by the RAS buffer is applied, so that only one selected RX line
`is driven at a high enough voltage, boosted by CB,
`The latch transistor QL in the word driver suppresses noise on each non(cid:173)
`selected word line while fixing the word line at O V as follows. During pre(cid:173)
`charge period all of the non-selected word lines are fixed at O V because the
`QLs are turned on. When one set of four-• word lines is selected by a decoder,
`the gate voltages of the corresponding four QLs are changed from Vnn to
`0 V and the QLs are thus cut off. At this moment, the "gate voltages of the
`corresponding four word-driver transistors Qw are increased from O V to
`Vnn - VT. During this process, the word lines are not at any floating voltage
`that easily couples noise to the lines, because the four word lines WL0-WL3
`are fixed at the voltages (i.e. 0 V) of RX0- RX3 through the respective Qws.
`After that, for example, RXo is selected and a VnH pulse is sent to WL0, fixing
`the remaining non-selected word lines at O V. Note that all of the word lines
`belonging to the non-selected decoders continue to be fixed at O V, because
`the QLs are turned on. Thus, the noise coupled to each non-selected word line,
`even during signal amplifications performed at a large voltage swing of Vnn
`or a half-Vnn on data lines, can be sufficiently suppressed. To further reduce
`noise on the word lines, another scheme of an additional transistor, which is
`controlled by address signals, on each word line has been proposed [3.25].
`High-speed driving of the RX line is also important, because a long delay is
`developed by the heavy loading of the large Qws and the long RX line running
`along a memory array. An RX driver placed at the end of the subarrays in
`Fig. 3.49a increases the line delay. However, a RX driver for each subarray
`in Fig. 3.49b [3.26], which is similar to the scheme in Fig. 3.47, shortens the
`, delay. In this scheme, only one subarray is selected by the address signals and
`a subarray selection signal 4>i . The node WDL of the RX line in Fig. 3.48
`corresponds to a line WDL that is common to a number of subarrays in
`
`~
`
`by
`
`ts,
`·en
`be
`lly
`)S
`
`l.C-
`1a(cid:173)
`of
`ne
`he
`{L
`is
`or
`de
`
`ell
`he
`4.
`~r,
`ed
`.ot
`
`I
`I I .
`I! ,
`I;
`Ii !
`
`I '
`
`! I ,
`
`r J
`
`'I; ,,
`t
`
`,I'
`I
`
`I
`I 1,,
`111 , ,
`I
`
`Qualcomm, Ex. 1017, Page 19
`
`

`

`150
`
`3. DRAM Circuits
`
`R 1 X2
`RXo RX3
`
`word line
`----WLo
`
`WL,
`
`Wl.2
`
`WL3
`
`common
`RX lines
`
`WDL
`
`..
`
`CMOS
`
`Voo
`
`R~
`
`..
`
`x~
`
`x~
`
`decoder
`
`(a)
`
`Voo
`
`a,
`
`(b)
`
`Fig.
`3.48. The configuration of word drivers and
`[3.4, 3_. 13, 3.21, 3.23]. (a) Word drivers; (b) RX drivers
`
`relevant circuits
`
`Fig. 3.49b. As soon as RAS activation starts, the heavily capacitive WDL
`line is boosted. After that, the addresses are valid and a subarray is thus
`selected so that a VoH pulse is applied to a common RX line belonging to the
`subarray. Consequently, the boosting time of the WDL line can be concealed
`and the RX line that the RX driver must drive is shortened to one subarray.
`Thus, the driving speed is improved.
`
`Qualcomm, Ex. 1017, Page 20
`
`

`

`I
`
`'
`
`i I I
`; Ii
`
`I
`
`I
`
`I '
`
`I I
`
`I
`
`•
`
`3.6 Read and Relevant Circuits
`
`151
`
`array #0
`
`. . .
`
`array #1-1
`
`array #0
`
`array #1-1
`
`Voo
`
`p~
`
`Cs
`<l>so-i)
`
`RX
`driver
`
`WDL
`
`aoa1
`
`<!>1-1
`
`...
`
`Fig. 3.49. Driving schemes of RX lines [3.4, 3.26]. (a) Direct driving of RX lines;
`(b) selective driving of multidivided RX lines
`
`The Voltage-Stress Relaxed Word Driver. This is the word driver that
`must operate at the highest voltage in a DRAM chip. Tnerefore, many circuits
`have been proposed to relax the voltage stress a