DIGITAL
`INTEGRATED
`CIRCUITS
`A DESIGN PERSPECTIVE
`SECOND EDITION
`
`JAN M. RABAEY
`ANANTHA CHANDRAKASAN
`BORIVOJE NIKOLIC
`
`PRENTICE HALL ELECTRONICS AND VLSI SERIES
`CHARLES G. SODINI, SERIES EDITOR
`
`-Pearson Education, Inc.
`
`Upper Saddle River, New Jersey 07458
`
`Qualcomm, Ex. 1014, Page 1
`
`

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`Library of Congress Cataloging-in-Publication Data on file.
`
`Vice President and Editorial Director, ECS: Marcia J. Horton
`Publisher: Tom Robbins
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`About the Cover: Detail of "Wet Orange," by Joan Mitchell (American, 1925-1992). Oil on canvas, 112 x 245 in.
`( 284.5 X 622.3 cm). Carnegie Museum of Art, Pittsburgh, PA. Gift of Kaufmann's Department Store and the
`National Endowment for the Arts, 74.11. Photograph by Peter Harholdt, 1995.
`
`© 2003, 1996 by Pearson Education, Inc.
`Pearson Education, Inc.
`Upper Saddle River, NJ 07458
`
`-
`The author and publisher of this book have used their best efforts in preparing this book. These efforts include the devel(cid:173)
`opment, research, and testing of the theories and progra)IIS to determine their effectiveness. The author and publisher
`shall not be liable in any event for incidental and consequential damages in connection with, or arising out of, the fur(cid:173)
`nishing, performance, or use of these programs.
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`All rights reserved. No part of this book may be reproduced, in any form or by any means,
`without permission in writing from the publisher.
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`Printed in the United States of America
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`1 0 9 8 7 6
`
`ISBN 0-13-090996-3
`
`Pearson Education Ltd., London
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`Pearson Education Inc., Upper Saddle River, New Jersey
`
`Qualcomm, Ex. 1014, Page 2
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`

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`604
`
`Chapter 11 • Designing Arithmetic Building Blocks
`
`This approach, however requires the use of more than one supply voltage. Multiple supply volt(cid:173)
`ages are aiready employed frequently in today's ICs. A separate supply voltage is provided for
`the 1/0 for compatibility reasons, where the 1/0 ring is designed with transistors with thicker
`gate oxides to sustain higher voltages. The logic core is powered from lower voltage supplies
`and uses transistors with thinner oxides. This approach can be extended to lower the power dis(cid:173)
`sipation of a circuit. For instance, every module could select the most appropriate voltage from
`two (or more) supply options. Even more extreme, multiple voltages can be assigned on a gate(cid:173)
`by-gate basis.
`in
`the digital system shown
`instance,
`Me>dule-Level Voltage Selection Consider, for
`Figure 11-45, which consists of a datapath block with a critical path of 10 ns and a control block
`with a much shorter critical path of 4 ns, operating from the same supply voltage of 2.5 V. Also.
`assume that the datapath block has a fixed latency and throughput and that no architectural trans(cid:173)
`formation can be applied to lower its supply. Since the control block finishes early (in other
`wotds, it has timing slack), its supply voltage can be lowered. A reduction to VDDL = 1 V
`increases its critical path delay to 10 ns, and lowers its power dissipation by more than five
`times.6 We effectively exploit the discrepancy in the critical-path length of the various modules
`(called the slack) to selectively lower the power consumption of the modules with the larger
`slack.
`When combining multiple supply voltages on a die, level converters are required when-:
`ever a module at the lower supply has to drive a gate at the higher voltage. If a gate supplied b
`VDDL drives a gate at VDDH• the PM0S transistor never turns off, resulting in static current
`reduced output swing as illustrates in Figure 11 °46. A level conversion performed at the boun ,
`aries of supply voltage domains prevents these problems. Ail asynchronous level conve
`based on the DVSL template (Chapter 6) and similar to the lo~-swing signalling gate
`Figure 9-32, is shown in Figure 11-46. The cross-coupled P:rvi:0S transistors perform the le
`conversion by using positive feedback. The delay of this level converter is quite sensitive to
`sistor-sizing and supply-voltage issues. The NM0S transistors operate with a reduced overdri
`VvvcVTh• compared with the PM0S devices. They have to be made large to be able to ov
`power the positive feedback. For a low value of V DDL> the delay can become very long. Due
`
`data path
`tP = 10 ns
`Vdd= 2.5V
`
`control path
`tP = 4 ns
`Vdd = 2.5V
`
`Figure 11-45 Design with diverging critical-path lengths.
`
`6This uses the ,simplifying assumption_ that the propagation delay is inversely proportional to the supply voltage.
`
`Qualcomm, Ex. 1014, Page 3
`
`I
`
`(
`
`f
`
`C
`a
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`

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`11.7 Power and Speed Trade-Offs in Datapath Structures*
`
`605
`
`Figure 11-46 Level converter.
`
`the reduced overdrive, the circuit is also very sensitive to variations in the supply voltage. Note
`that level converters are not needed for a step-down change in voltage.
`The overhead of the level conversion can be somewhat mitigated by observing that most
`conversions are performed at a register boundary. For instance, the control inputs to the datapath
`block of Figure 11-45 are commonly sampled in a register. A practical way to perform the level
`conversion is, then, to embed it inside the register. A level-converting register is shown in
`Figure 11-47. It is a conventional transmission gate implementation of a master-slave latch pair,
`where a cross-coupled PMOS pair is embedded in the slave latch to perform level conversion.
`Multiple Supplies Inside a Block The same approach can be applied at much smaller. granu(cid:173)
`larity by individually setting the supply voltage for each cell inside a block [Usami.95,
`Hamada0l]. Examining the histogram of the critical-path delays for a typical digital block
`reveals that only a few paths are critical or near critical and that many paths have much shorter
`delays. The shorter paths essentially waste energy, as there is no reward for finishing early. For
`each of these paths, the supply voltage could be lowered to the optimum level. Minimum energy
`consumption would be achieved if all paths become critical. However, this is not easily achiev(cid:173)
`able, as many logic gates are shared between different paths, and it is impractical to generate and
`
`D
`
`Q
`
`ck
`ckb
`elk ~
`
`Figure 11-47 Level-converting register. Shaded gates are
`supplied from V00L [Usami95].
`
`Qualcomm, Ex. 1014, Page 4
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`