Paper No. 1
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`__________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`__________________
`
`
`QUALCOMM INC. AND QUALCOMM TECHNOLOGIES,
`INC.,
`
`Petitioners,
`
`v.
`
`APPLE INC.,
`
`Patent Owner.
`
`
`
`U.S. PATENT NO. 8,098,534
`
`TITLE: INTEGRATED CIRCUIT WITH SEPARATE SUPPLY
`VOLTAGE FOR MEMORY THAT IS DIFFERENT FROM
`LOGIC CIRCUIT SUPPLY VOLTAGE
`
`Issue Date: January 17, 2012
`
`
`PETITION FOR INTER PARTES REVIEW
`UNDER 35 U.S.C. § 312
`
`
`
`
`
`

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`TABLE OF CONTENTS
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`
`B.
`
`V.
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`Page
`Introduction ..................................................................................................... 1
`I.
`II. Mandatory Notices .......................................................................................... 3
`A.
`Real Party in Interest (37 C.F.R. § 42.8(b)(1)) .................................... 3
`B.
`Related Matters (37 C.F.R. § 42.8(b)(2)) ............................................. 3
`C.
`Lead and Back-Up Counsel and Service Information (37 C.F.R.
`§ 42.8(b)(3) and (b)(4)) ........................................................................ 4
`Fees (37 C.F.R. § 42.103) .................................................................... 5
`D.
`III. Grounds for Standing Pursuant to (37 C.F.R. § 104(a)) ................................. 5
`IV. Statement of Precise Relief Requested for Each Challenged Claim .............. 5
`A.
`The Claims for Which Review is Requested (37 C.F.R. §
`42.104(b)(1)) ........................................................................................ 5
`The Specific Statutory Grounds on Which the Challenge is
`Based and Prior Art Relied Upon for Each Ground (37 C.F.R. §
`42.104(b)(2)) ........................................................................................ 6
`Reasons for the Relief Requested Under 37 C.F.R. §§ 42.22(a)(2) and
`42.104(b)(4) .................................................................................................... 7
`A. Overview of the ’534 Patent and its Technology ................................. 7
`B.
`The Prosecution History ..................................................................... 13
`1.
`The Prosecution History of Predecessor U.S. Patent No.
`7,355,905 .................................................................................. 13
`(a) The Daga Patent ............................................................. 14
`(b) The Claim Amendments to Attempt to Overcome
`Daga ............................................................................... 15
`The Prosecution History of Predecessor U.S. Patent No.
`7,474,571 .................................................................................. 17
`The Prosecution History of Predecessor U.S. Patent No.
`7,760,559 .................................................................................. 18
`The Prosecution History of the ’534 Patent ............................. 18
`4.
`37 C.F.R. § 42.104(b)(3): Claim Construction ................................. 18
`1.
`A Person of Ordinary Skill in the Art ...................................... 18
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`2.
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`3.
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`C.
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`TABLE OF CONTENTS
`(continued)
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`Page
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`1.
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`Construction of Claim Terms ................................................... 19
`(a)
`“integrated circuit” ........................................................ 20
`(b)
`“during use” ................................................................... 20
`D. Overview of the Prior Art ................................................................... 21
`1.
`Clark ......................................................................................... 21
`2.
`Kawata ..................................................................................... 26
`37 C.F.R. § 42.104(b)(4): How the Construed Claims are
`Unpatentable ....................................................................................... 28
`37 C.F.R. § 42.104(b)(5): Supporting Evidence ............................... 28
`F.
`VI. Claims 1–4 of the ’534 Patent are Unpatentable .......................................... 29
`A. Ground 1: Clark Anticipates Claims 1–4 .......................................... 29
`1.
`Independent Claim 1 ................................................................ 29
`(a)
`Preamble – “An integrated circuit comprising:” ........... 29
`(b) Element 1[a] – “at least one logic circuit supplied
`by a first supply voltage during use, wherein a first
`voltage domain corresponds to the first supply
`voltage; and” .................................................................. 30
`(c) Element 1[b] – “at least one memory circuit
`coupled to the logic circuit and supplied by a
`second supply voltage during use, wherein a
`second voltage domain corresponds to the second
`supply voltage” .............................................................. 31
`(d) Element 1[c] – “wherein the memory circuit
`comprises one or more circuits that interface with
`the logic circuit, and wherein the one or more
`circuits are configured to level shift at least one
`signal between the first voltage domain and the
`second voltage domain, and” ......................................... 34
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`E.
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`TABLE OF CONTENTS
`(continued)
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`Page
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`(e) Element 1 [d] – “wherein a magnitude of the first
`supply voltage is less than a magnitude of the
`second supply voltage at least a portion of the time
`during use, and wherein the logic circuit is
`configured to read and write the memory circuit.” ....... 39
`Dependent Claim 2 .................................................................. 41
`2.
`Dependent Claim 3 .................................................................. 42
`3.
`Dependent Claim 4 .................................................................. 45
`4.
`B. Ground 2: Kawata Anticipates Claims 1–4 ....................................... 47
`1.
`Independent Claim 1 ................................................................ 47
`(a)
`Preamble – “An integrated circuit comprising:” ........... 47
`(b) Element 1[a] – “at least one logic circuit supplied
`by a first supply voltage during use, wherein a first
`voltage domain corresponds to the first supply
`voltage; and” .................................................................. 48
`(c) Element 1[b] – “at least one memory circuit
`coupled to the logic circuit and supplied by a
`second supply voltage during use, wherein a
`second voltage domain corresponds to the second
`supply voltage, and” ...................................................... 50
`(d) Element 1[c] – “wherein the memory circuit
`comprises one or more circuits that interface with
`the logic circuit, and wherein the one or more
`circuits are configured to level shift at least one
`signal between the first voltage domain and the
`second voltage domain, and” ......................................... 52
`(e) Element 1[d] – “wherein a magnitude of the first
`supply voltage is less than a magnitude of the
`second supply voltage at least a portion of the time
`during use, and wherein the logic circuit is
`configured to read and write the memory circuit. ” ...... 53
`Dependent Claim 2 .................................................................. 56
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`2.
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`-iii-
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`TABLE OF CONTENTS
`(continued)
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`Page
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`Dependent Claim 3 .................................................................. 56
`3.
`Dependent Claim 4 .................................................................. 58
`4.
`VII. Conclusion .................................................................................................... 60
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`I.
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`Introduction
`Pursuant to 35 U.S.C. § 312 and 37 C.F.R. § 42.100 et seq., Qualcomm Inc.
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`and Qualcomm Technologies, Inc. (collectively, “Petitioners” or “Qualcomm”)
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`request inter partes review (“IPR”) of claims 1–4 (the “Challenged Claims”) of U.S.
`
`Patent No. 8,098,534 (“the ’534 Patent,” Ex. 1001), which issued on January 17,
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`2012, and is assigned to Apple, Inc. (“Apple”).
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`The ’534 Patent is directed to an integrated circuit having at least one logic
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`circuit and one memory circuit, each of which is supplied by respective first and
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`second supply voltages. Ex. 1001, [57], 2:10–13, 3:29–43, Fig. 1 (disclosing “Logic
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`Circuits 12” supplied by supply voltage VL and “Memory Circuits 14” supplied by
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`supply voltage VM). According to the ’534 Patent, if a single voltage is used to
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`supply both the logic and memory circuits, then this common supply voltage can be
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`reduced only so far due to memory reliability issues. Id., 1:22–2:6. “As supply
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`voltage decreases below a certain voltage, the ability to reliably read and write the
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`memory decreases.” Id., 1:49–51; see also id., 2:3–6. The ’534 Patent supposedly
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`improved upon the prior art by using separate supply voltages for the logic and
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`memory circuits. This allows the logic and memory supply voltages to be different,
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`including allowing the logic supply voltage to be lower than the memory supply
`
`voltage in order to further conserve power. Id., 2:56–64; 3:29–43, Fig. 1; see also
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`Ex. 1002 ¶¶ 31–34 (Clark Decl.).
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`There is nothing, however, patentable about using different supply voltages to
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`supply a logic circuit and a memory circuit. This feature is disclosed by each of
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`U.S. Patent No. 6,650,589 to Clark (“Clark”) (Ex. 1003) and U.S. Patent No.
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`6,920,071 to Kawata et al. (“Kawata”) (Ex. 1004). Clark was not of record during
`
`prosecution of the ’534 Patent. Kawata was made of record during the ’534 Patent
`
`prosecution, but it was not relied upon in any rejection by the Examiner or otherwise
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`cited or addressed in any substantive way in any Office Action.
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`There is also nothing patentable about the other aspects of the Challenged
`
`Claims, which recite conventional memory and logic circuitry known to a person of
`
`ordinary skill in the art (“POSITA”) as of the effective filing date of the ’534 Patent.
`
`As explained herein, and as supported by the Declaration of Lawrence T. Clark,
`
`Ph.D. (Ex. 1002), the Challenged Claims are unpatentable in view of both Clark and
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`Kawata. See §§ IV, V, VI, infra.
`
`Notably, during prosecution of a predecessor application to the ’534 Patent
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`(ultimately issued as U.S. Patent No. 7,355,905, “’905 Patent”), the Examiner found
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`that using a first supply voltage to supply a logic circuit and a second supply voltage
`
`to supply a memory circuit was met by U.S. Patent No. 7,120,061 to Daga (“Daga”)
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`(Ex. 1005). See § V.B.1, infra (discussing prosecution history of the ’905 Patent).
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`In response, the applicants amended the patent claims of the predecessor application
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`to recite that the first supply voltage (i.e., the logic supply voltage VL) and the
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`second supply voltage (i.e., the memory supply voltage VM) are received on
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`respective first and second inputs to the claimed integrated circuit. Id. Based on
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`these amendments regarding where the supply voltages are input to, and received by,
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`the integrated circuit, the Examiner allowed the claims of the predecessor ’905
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`Patent. Id. These additional features, however, which allegedly distinguished over
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`the prior art Daga patent, are not present in the Challenged Claims of the ’534
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`Patent.
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`Because the Challenged Claims are unpatentable, IPR should be instituted and
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`the Challenged Claims should be cancelled.
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`II. Mandatory Notices
` Real Party in Interest (37 C.F.R. § 42.8(b)(1))
`Qualcomm Inc. and Qualcomm Technologies, Inc. are the real parties-in-
`
`interest.
`
` Related Matters (37 C.F.R. § 42.8(b)(2))
`The ’534 Patent is involved in the following proceeding that may affect, or be
`
`affected by, a decision in this proceeding: Qualcomm Inc. v. Apple Inc., No. 3:17-
`
`cv-1375 (S.D. Cal.) (“’1375 Case”). Additionally, Qualcomm is concurrently filing
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`separate petitions challenging claims of U.S. Patent Nos. 7,355,905 and 7,760,559,
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`which are in the same family, and share a specification with, the ’534 Patent.
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` Lead and Back-Up Counsel and Service Information (37 C.F.R.
`§ 42.8(b)(3) and (b)(4))
`Lead Counsel
`John A. Marlott
`Reg. No. 37,031
`JONES DAY
`77 West Wacker, Suite 3500
`Chicago, Illinois 60601-1692
`(312) 269-4236
`jamarlott@jonesday.com
`
`Back-up Counsel
`Matthew W. Johnson
`Reg. No. 59,108
`JONES DAY
`500 Grant Street, Suite 4500
`Pittsburgh, Pennsylvania 15219-2514
`(412) 394-9524
`mwjohnson@jonesday.com
`
`John M. Michalik
`Reg. No. 56,914
`JONES DAY
`77 West Wacker, Suite 3500
`Chicago, Illinois 60601-1692
`(312) 269-4215
`jmichalik@jonesday.
`
`Thomas W. Ritchie
`Reg. No. 65,505
`JONES DAY
`77 West Wacker, Suite 3500
`Chicago, Illinois 60601-1692
`(312) 269-4003
`twritchie@jonesday.com
`
`Pursuant to 37 C.F.R. § 42.10(b), a power of attorney accompanies this
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`petition. Please address all correspondence to lead and back-up counsel at the
`
`addresses above. Qualcomm consents to electronic service by email at the email
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`addresses listed above.
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`Fees (37 C.F.R. § 42.103)
`The undersigned representative of Qualcomm authorizes the Board to charge
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`the $15,500 petition fee, as well as any additional fees, to Deposit Account 501432,
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`ref: 178774-680002. Four claims are being reviewed, so $15,000 in post institution
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`fees are due for a total of $30,500.
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`III. Grounds for Standing Pursuant to (37 C.F.R. § 104(a))
`Qualcomm certifies that the ’534 Patent is available for IPR and that
`
`Qualcomm is not barred or estopped from requesting IPR of the Challenged Claims
`
`on the grounds identified in this petition. Apple filed and served its first amended
`
`answer and counterclaims in the ’1375 Case, first asserting infringement of the ’534
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`Patent by Qualcomm, on November 29, 2017. Qualcomm has filed this petition
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`within one year of service of Apple’s first amended answer and counterclaims, and
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`shortly after the District Court issued a claim construction order adopting certain of
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`Apple’s positions regarding the breadth of the ’534 Patent claims.
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`IV. Statement of Precise Relief Requested for Each Challenged Claim
` The Claims for Which Review is Requested (37 C.F.R. §
`42.104(b)(1))
`Qualcomm requests review and cancellation of claims 1–4 of the ’534 Patent
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`(the “Challenged Claims”).
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`The Specific Statutory Grounds on Which the Challenge is Based
`and Prior Art Relied Upon for Each Ground (37 C.F.R. §
`42.104(b)(2))
`Qualcomm requests IPR of the Challenged Claims on the grounds set forth
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`below and requests that each of the Challenged Claims be found unpatentable and
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`cancelled. An explanation of how the Challenged Claims are unpatentable is
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`provided in the form of the detailed description that follows, which indicates where
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`each of the claim elements can be found in, and the relevance of, the prior art.
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`Additional explanation and support for each ground is set forth in Ex. 1002
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`(Declaration of Lawrence T. Clark, Ph.D.), referenced throughout this petition.
`
`Ground
`Ground 1
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`Ground 2
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`Claims
`1–4
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`1–4
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`
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`Basis
`35 U.S.C. § 102 based on U.S. Patent No.
`6,650,589 to Clark (“Clark”)
`
`35 U.S.C. § 102 based on U.S. Patent No.
`6,920,071 to Kawata et al. (“Kawata”)
`
`
`The ’534 Patent issued on January 17, 2012, from U.S. Application No.
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`12/791,080, which was filed on June 1, 2010. The ’534 Patent claims priority as a
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`divisional of U.S. Application No. 12/325,476, which was filed on December 1,
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`2008, and issued as U.S. Patent No. 7,760,559, which is a continuation of U.S.
`
`Application No. 12/034,071, which was filed on February 20, 2008, and issued as
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`U.S. Patent No. 7,474,571, which is a divisional of U.S. Application No.
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`11/173,565, which was filed on July 1, 2005, and issued as U.S. Patent No.
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`7,355,905. Accordingly, the effective filing date of the ’534 Patent is July 1, 2005.
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`Clark was filed on November 29, 2001, issued on November 18, 2003, and is
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`prior art under pre-AIA 35 U.S.C. § 102(a)-(b).
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`Kawata was filed on May 14, 2004, published on January 6, 2005, as U.S.
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`Patent Application Publication No. 2005/0002224, issued on July 19, 2005, and is
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`prior art under pre-AIA 35 U.S.C. § 102(a), (e).
`
`V. Reasons for the Relief Requested Under 37 C.F.R. §§ 42.22(a)(2) and
`42.104(b)(4)
` Overview of the ’534 Patent and its Technology
`The ’534 Patent is entitled “Integrated Circuit with Separate Supply Voltage
`
`for Memory that is Different From Logic Circuit Supply Voltage.” Ex. 1001, [54].
`
`The ’534 Patent is related to “an integrated circuit compris[ing] at least one logic
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`circuit supplied by a first supply voltage and at least one memory circuit coupled to
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`the logic circuit and supplied by a second supply voltage.” Id., [57]. This
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`arrangement is shown by the embodiment of Figure 1 (with coloring annotations
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`added):
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`“A block diagram of . . . an integrated circuit 10 is shown” above, with the
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`boundary of the integrated circuit annotated in blue. Id., 2:56–57. “[T]he integrated
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`circuit includes a plurality of logic circuits 12 and a plurality of memory circuits 14”
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`that are coupled together. Id., 2:58–60.
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`As shown by the yellow annotation, “[t]he logic circuits 12 are powered by a
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`first supply voltage provided to the integrated circuit 10 (labeled VL in FIG. 1).” Id.,
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`2:60–62. As shown by the green annotation, “[t]he memory circuits 14 are powered
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`by a second power supply voltage provided to the integrated circuit 10 (labeled VM
`
`in FIG. 1).” Id., 2:62–64. Thus, the second supply voltage (VM) supplied to the
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`memory circuits 14 is different from the first supply voltage (VL) supplied to the
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`logic circuits 12. Ex. 1002 ¶¶ 34–35.
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`In this embodiment, the first supply voltage (VL) is also supplied to the
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`memory circuits 14, as shown by the yellow annotation extending to memory
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`circuits 14. Ex. 1001, 2:64–67. But the first supply voltage (VL) need not be
`
`supplied to the memory circuits 14 in all embodiments. See Ex. 1002 ¶¶ 193–194,
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`287–288 (dependent claim 2). The ’534 Patent describes this as a feature of “certain
`
`embodiments.” Ex. 1001, 2:64–67. For example, independent claim 1 of the ’534
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`Patent lacks this element, but it is required by dependent claim 2 (“wherein the
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`memory circuit is supplied by the first supply voltage in addition to the second
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`supply voltage during use”) as well as several other dependent claims reciting that
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`different subcomponents of the memory circuit are supplied by the first supply
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`voltage (e.g., claims 7–12).
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`The ’534 Patent states that “logic circuits 12 may generally implement the
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`operation for which the integrated circuit is designed,” which may involve
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`“generat[ing] various values during operation,” storing values in the memory
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`circuits, and “read[ing] various values from the memory circuits 14 on which to
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`operate.” Id., 3:4–9.
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`The ’534 Patent states that memory circuits 14 store data. “For example, . . .
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`the memory circuits 14 may include memory used for caches, register files,
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`integrated-circuit-specific data structures, etc.” Id., 3:9–12. “The memory circuits
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`14 may implement any type of readable/writable memory,” including, for example,
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`static random access memory (SRAM). Id., 3:12–15. But the memory circuits of
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`the ’534 Patent include more than just memory. Ex. 1002 ¶¶ 37–39, 90, 178–179,
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`223, 275. As shown in the memory circuit of Figure 2, for example, the memory
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`circuit may include a level shifter circuit 20, word line driver circuits 22, and other
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`circuits in addition to memory array 24 where data is stored. Ex. 1001, 3:51–57,
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`Fig. 2. As shown in Figure 3, the memory circuits (which include the memory
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`array) may include bit line driver circuits 30, memory cells 32A-32N, bit line
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`precharge circuits 34, bit line hold circuits 36, and senseamps 38. Id., 6:37–40, Fig.
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`3.
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`The circuit elements shown in Figures 2 and 3 as part of the illustrated
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`embodiment of the memory circuit from Figure 1 were conventional and well-
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`known at the effective filing date of the ’534 Patent. See Ex. 1002 ¶¶ 86, 91, 99–
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`100, 117, 119, 125, 152, 246 (citing Ex. 1013, at 384; Ex. 1014, at 604–05; Ex.
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`1016, at 313, 570, 574–79; Ex. 1017, at 83–90, 144–54; Ex. 1018, at 143–47).
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`Among these conventional circuit elements is a “level shifter circuit 20,” which is
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`“configured to level shift an input signal to produce an output signal” by “changing
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`the high assertion of the signal from one voltage to another.” Ex. 1001, 5:16–19.
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`“Level shifting may be performed in either direction (e.g. the voltage after level
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`shifting may be higher or lower than the voltage before level shifting).” Id., 5:19–
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`22. Two embodiments of level shifter circuit 20 are shown in Figures 4 and 5. Id.,
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`8:39–40, 9:56–60, Figs. 4, 5. However, other embodiments are within the scope of
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`the ’534 Patent. See Ex. 1002 ¶¶ 125, 185, 246 (discussing related ’905 Patent and
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`’534 Patent); Ex. 1001, 5:28–42, 6:4–7, 6:22–24, 8:20–24, 9:36–37, 10:16–20.
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`The word line drivers 22 are a second example of conventional circuit
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`elements that may form part of the memory circuit. Ex. 1002 ¶¶ 52, 99, 117 (citing
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`Ex. 1016, at 563–80; Ex. 1017, at 144–54; Ex. 1018, at 143–55). The word line
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`drivers 22 generate a set of word line signals to memory array 24. Ex. 1001, 4:2–4.
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`A third conventional circuit element of memory circuits 14 is memory array
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`24. See Ex. 1002 ¶¶ 52, 91, 152 (discussing related ’905 Patent and related ’559
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`Patent and citing Ex. 1016, at 563–80; Ex. 1018, at 143–55). Figure 3 of the ’534
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`Patent shows “a circuit diagram of a portion of one embodiment of the memory
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`array 24” of the memory circuit (as shown in Figure 2), which consists of additional
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`conventional circuit elements. See Ex. 1001, 6:32–8:38, Fig. 3. Among these
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`conventional circuit elements is a “bit line precharge circuit 34,” which precharges
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`bit lines in preparation for read operations. See id., 6:37–40, 7:40–57; Ex. 1002
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`¶¶ 7, 52, 101, 117 (discussing related ’905 Patent and citing Ex. 1016, at 563–80;
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`Ex. 1017, at 144–51, 164; Ex. 1018, at 143–55). “The memory cells 32A-32N [of
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`memory array 24] are supplied with the [second] VM supply voltage” and can be a
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`“typical CMOS SRAM cell.” Ex. 1001, 6:41–42, 6:61–64.
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`By supplying the memory circuit 14 (and its memory array 24) with a supply
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`voltage (VM) that is different than the supply voltage (VL) supplied to the logic
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`circuit 12, these two supply voltages can differ for each type of circuit. Id., 3:29–43;
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`Ex. 1002 ¶¶ 31–34. The logic circuit supply voltage (VL) can be decreased below
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`that of the memory circuit supply voltage (VM) while ensuring that the memory
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`circuit 14 still has a higher supply voltage (VM) that is sufficient for the memory to
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`remain stable. Ex. 1001, 3:23–43, Ex. 1002 ¶¶ 31–34.
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`As discussed herein, a POSITA would have known at the time of the ’534
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`Patent’s effective filing date that, all things being equal, a circuit’s power
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`consumption can be reduced by reducing the supply voltage to that circuit. Ex. 1002
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`¶¶ 53–56; see also Ex. 1001, 1:35–46. A POSITA would also have known at the
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`time of the ’534 Patent’s effective filing date that memory can become unreliable if
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`it is supplied by a voltage that is too low for the circuit’s design. Ex. 1002 ¶¶ 50–56;
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`see also Ex. 1001, 1:47–2:6. And, a POSITA would have known before the ’534
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`Patent’s effective filing date that the minimum usable voltage for a common supply
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`voltage shared by logic and memory circuits is dependent on the memory circuit.
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`Ex. 1002 ¶¶ 50–56; see also Ex. 1001, 2:3–6. Thus, in order to reduce the power
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`consumed by logic circuitry through reduction of its supply voltage, it was known to
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`a POSITA, and disclosed in the prior art (including Clark and Kawata), to use two
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`different supply voltages to supply logic circuitry and memory circuitry,
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`respectively. See § VI, infra.
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`The Prosecution History
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`As reflected above, the ’534 Patent claims priority as a divisional of U.S.
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`Patent No. 7,760,559, which is a continuation of U.S. Patent No. 7,474,571, which is
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`a divisional of U.S. Patent No. 7,355,905. See Advanced Cardiovascular Sys., Inc.
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`v. Medtronic, Inc., 265 F.3d 1294, 1305 (Fed. Cir. 2001) (“The prosecution history
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`of a related patent can be relevant if, for example, it addresses a limitation in
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`common with the patent in suit.”); Elkay Mfg. Co. v. Ebco Mfg. Co., 192 F.3d 973,
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`980 (Fed. Cir. 1999) (“When multiple patents derive from the same initial
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`application, the prosecution history regarding a claim limitation in any patent that
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`has issued applies with equal force to subsequently issued patents that contain the
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`same claim limitation.”).
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`1.
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`The Prosecution History of Predecessor U.S. Patent No.
`7,355,905
`As originally filed, claim 1 in the application that issued as predecessor U.S.
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`Patent No. 7,355,905 (“the ’905 Patent”) recited an “integrated circuit” comprising
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`“at least one logic circuit supplied by a first supply voltage,” “at least one memory
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`-13-
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`circuit coupled to the logic circuit and supplied by a second supply voltage,” as well
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`as other elements. Ex. 1006, at 25. Claim 13 recited a method comprising a logic
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`circuit and memory cell performing certain steps, with the logic circuit and memory
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`cell similarly supplied by different supply voltages. Id., at 27. The Examiner
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`initially rejected these and all other pending claims as anticipated under pre-AIA 35
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`U.S.C. § 102(e) by U.S. Patent No. 7,120,061 to Daga (“Daga”). Id., at 80–84.
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`(a) The Daga Patent
`Figure 3 of Daga is reproduced below, with coloring annotations added.
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`Figure 3 shows a system-on-a-chip 300 having circuitry supplied by two supply
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`voltages, ExtVDD and RegVDD. Ex. 1005, 3:13–24, Fig. 3. RegVDD is a first supply
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`voltage of “for example 1.8V,” which is generated on system-on-chip 300 by
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`voltage regulator 315 and “applied to . . . advanced logic 335” such as the
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`microcontroller 335 shown in Figure 3. Id., 3:18–23, Fig. 3. ExtVDD is a second
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`supply voltage, “for example 3.3V or 5V,” which is “applied to memory 340.” Id.,
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`3:16–18, 3:23–24, Fig. 3.
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`-14-
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`(b) The Claim Amendments to Attempt to Overcome Daga
`The applicants responded to the Examiner’s rejection based on Daga by
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`amending the claims in two ways. First, they amended independent claims 1 and 13
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`of the ’905 Patent application to require that the first supply voltage be “received on
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`a first input to the integrated circuit” and the second supply voltage be “received on
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`a second input to the integrated circuit.” Ex. 1006, at 97, 99. The applicants relied
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`on these claim amendments in their remarks, explaining that “Daga’s integrated
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`circuit has only one power supply input to the integrated circuit (ExtVDD, see Fig.
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`3).” Id., at 103. The applicants further argued: “Thus, Daga fails to anticipate ‘a
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`first supply voltage received on a first input to the integrated circuit; and . . . a
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`second supply voltage received on a second input to the integrated circuit’ as recited
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`in claim 1.” Id. (emphasis by applicants in original).
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`-15-
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`Second, the applicants amended independent claims 1 and 13 to recite that the
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`memory circuit includes a memory array, and the memory array is “continuously
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`supplied by the second supply voltage during use.” Id., at 97, 99. The applicants
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`relied on this new “continuously supplied” language to distinguish their claims from
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`Daga’s disclosures. Specifically, this language was used to distinguish prior art,
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`such as Daga, which uses non-volatile memory. See id., at 102–03; Ex. 1002 ¶ 105.
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`The applicants noted that “Daga teaches a non-volatile memory such as an
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`EEPROM or Flash memory (see, e.g., Daga, col. 3, lines 20-24)” and argued that
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`“[i]n such memories, the memory array does not include memory cells that are
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`continuously supplied with a supply voltage during use.” Ex. 1006, at 102
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`(emphasis by applicants in original). Instead, “the memory arrays are designed to
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`retain values without any power applied (hence the ‘nonvolatile’ nature of such
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`cells).” Id.
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`The applicants referred to Figure 4 in Daga (reproduced below) to further
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`explain this second argument. Id. Figure 4 “is a schematic diagram illustrating one
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`embodiment of the memory from FIG. 3.” Ex. 1005, 2:62–63. The applicants
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`specifically pointed to memory array 430 and argued there are no power supply
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`inputs to the memory array. Ex. 1006, at 102.
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`In comparison, Figure 3 of the ’534 Patent, which “is a circuit diagram of one
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`embodiment of a memory array shown in FIG. 2,” shows that “[t]he memory cells
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`32A-32N are supplied with the VM supply voltage.” Ex. 1001, 2:33–34, 6:41–42,
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`Fig. 3.
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`Based on these claim amendments and two distinguishing arguments
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`regarding the necessity of: (1) two, distinct power supply inputs to the integrated
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`circuit; and (2) memory cells continuously supplied with a supply voltage during
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`use, the Examiner allowed independent claims 1 and 13 (and the corresponding
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`dependent claims) in the form as issued in the ’905 Patent. See Ex. 1006, at 112.
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`2.
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`The Prosecution History of Predecessor U.S. Patent No.
`7,474,571
`The claims of predecessor U.S. Patent No. 7,474,571 were allowed in a first
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`Office Action; the claims were not subject to any rejection by the Examiner. Ex.
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`1020, at 72–76.
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`3.
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`The Prosecution History of Predecessor U.S. Patent No.
`7,760,559
`The claims of predecessor U.S. Patent No. 7,760,559 were primarily rejected
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`based on obviousness-type double patenting in view of the ’905 Patent. See Ex.
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`1021, at 61–63. Two claims (15, 16) were also rejected under 35 U.S.C. § 102(b) as
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`anticipated by U.S. Patent No. 6,181,606. Id., at 62–63. The claims of the ’559
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`Patent were not otherwise rejected. The applicants submitted a terminal disclaimer
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`to overcome the double-patenting rejection and amended claims 15 and 16 to
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`include the features of another claim (18) that had been indicated as allowable. Id.,
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`at 83–93, 99–109, 117–24, 126–30, 134–35, 149–52.
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`4.
`The Prosecution History of the ’534 Patent
`The claims of the application leading to the ’534 Patent were never rejected
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`based on prior art. The only rejection of the ’534 Patent claims was based on
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`obviousness-type double patenting in view of the ’905 Patent. Ex. 1019, at 70–76.
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`The applicants submitted a terminal disclaimer to overcome the double-patenting
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`rejection. Id., at 92–96, 102–03, 108–113, 143–47, 199–205.
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`37 C.F.R. § 42.104(b)(3): Claim Construction
`1.
`A Person of Ordinary Skill in the Art
`Qualcomm maintains that a POSITA, as of July 1, 2005, would have had a
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`master’s degree in electrical engineering or computer engineering or at least four
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`years of experience in the field of integrated circuit SRAM design, or an equivalent
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`combination of education and experience in this field. Ex. 1002 ¶¶ 46–49.
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`1.
`Construction of Claim Terms
`In this IPR, the claims of the ’534 Patent “shall be given [their] broadest
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`reasonable construction in light of the [’534 Patent’s] specification.” 37 C.F.R.
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`§ 42.100(b). Because a district court applies a different standard, the claim
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`constructions presented in this petition do not necessarily reflect the constructions
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`that Petitioners believe should be adopted by a district court.
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`In the ’1375 Case, the District Court adopted certain of Apple’s claim
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`construction positions. Ex. 1012 (Order Construing Claims), at 3–5. Petitioners
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`have submitted the District Court’s claim construction decision for the Board’s
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`consideration. Power Integrations, Inc. v. Lee, 797 F.3d 1318, 1326–27 (Fed. Cir.
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`2015) (“The fact that the board is not generally bound by a previous judicial
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`interpretation of a disputed claim term does not mean, however, that it has no
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`obligation to acknowledge that interpretation or to assess whether it is consistent
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`with the broadest reasonable construction of the term.”). Although Petitioners
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`reserve the right to appeal or otherwise challenge the District Court’s claim
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`construction order, Petitioners request that the Board in this IPR constr