·
`
`
`
`M. Morris Mano .1l
`
`IPR2019-00131
`PANASONIC EX. 1029, p. 1 of 14
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`

`

`Contents
`
`Preface
`
`XV
`
`1
`4
`7
`
`II
`
`18
`
`22
`
`/of
`
`CHAPTER ONE
`Digital Logic Circuits
`1·1 Digital Computers
`1·2 Logic Gates
`1-3 Boolean Algebra
`Complemmr of a Function I 0
`1-4 Map Simplification
`Prodvct-af·Swru Sfm�Jlifico.tion
`Don't-Care Condirioru
`16
`1-S Combinational Circuits
`
`Hai{-Mkr 19
`MJI.Mkf
`20
`,1-6 Flip-Flop�
`SR FU,.Fiop 22
`0 FU,.Fiop 23
`JK Flip-Flop 24
`T Flip-Flop 24
`E.dgc-Tfiumd Flip.Fiops 25
`27
`Exti!ation Talks
`1-7 Sequential
`Circuits
`Flip-Flop Input Equ4tioru
`SIOU Table 30
`SIOU Oiogr11m 31
`32
`�Example
`36
`� Proced.at
`Problems
`References
`
`28
`
`iii
`
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`iv Contents
`
`CHAPTER TWO
`Digital Components
`
`2-1 Integrated
`Circuits
`2-2 Decoders
`45
`NAND Gate Decoder
`
`Decoder Expansion
`46
`Encoders 47
`2·3 Multiplexers
`2-4 Registers
`
`
`Register with Parallel Load 51
`2-5 Shift Registers
`Bidirectional Shift Register with Parallel Load
`
`
`
`53
`2-6 Binary Counters
`Binary Counter with Parallel Load
`
`
`58
`2-7 Memory Unit
`
`Random-Access Memory 60
`
`Read-Only Memory 61
`Types of ROMs 62
`Problems
`References
`
`CHAPTER THREE
`Data Representation
`
`3-1 Data Types
`Number Systems 68
`Octal and Hexadecimal Numbers 69
`72
`Decimal Representation
`
`Alphanumeric Representation
`73
`3-2 Complements
`75
`
`(r-l)'s Complement
`(r's) Complement 75
`
`
`Subtraction of Unsigned Numbers 76
`3-3 Fixed-Point
`Representation
`78
`
`Integer Representation
`
`Arithmetic Addition 79
`
`Arithmetic Subtraction 80
`Overflow
`80
`
`Decimal Fixed-Point Representation 81
`
`41
`
`41
`43
`
`48
`50
`
`53
`
`56
`
`58
`
`63
`65
`
`67
`
`67
`
`74
`
`77
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`3-4 Floating-Point
`Representation
`3-5 Other Binary Codes
`Gray Code 84
`
`Other Decimal Codes 85
`
`Ocher Alphanumeric Codes 86
`3-6 Error Detection Codes
`Problems
`References
`
`Contents V
`
`83
`84
`
`87
`89
`91
`
`CHAPTER FO UR
`Transfer and Microoperations 93
`Register
`
`4·1 Register Transfer
`language
`4·2 Register
`Transfer
`4-3 Bus and Memory Transfers
`Bus Buffers I 00
`Three-Stare
`Memory Transfer 10 I
`4-4
`
`Arithmetic Microoperations
`Binary Adder 1 03
`Binary Adder-Subtractor
`I04
`Binary lncremenrer 1 05
`
`Arithmetic Circuit I 06
`4-5
`Logic Microoperations
`List of Logic Microoperations
`1 09
`
`Hardware Implementation
`III
`Some Applications III
`4-6 Shift Microoperations
`
`Hardware Implementation II5
`4-7 Arithmetic
`Logic Shift Unit
`Problems
`References
`
`93
`95
`97
`
`102
`
`108
`
`114
`
`116
`119
`122
`
`CHAPTER FIVE
`and Design 123
`Basic Computer Organization
`
`5-1 Instruction
`Codes
`Stored Prowam Organization
`I25
`
`Indirect Address I26
`
`123
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`vi Contents
`
`5-2 Computer Registers
`Common Bus System 1 29
`5-3 Computer Instructions
`1 34
`
`Instruction Set Completeness
`5-4 Timing and Control
`5-5 Instruction
`Cycle
`Fetch and Decode 1 39
`the Type of Instruction
`1 41
`Determine
`
`Register-Reference Instructions
`1 43
`5-6 Memory-Reference
`Instructions
`AND to AC 1 45
`ADD wAC 1 46
`LOA: Load to AC 1 46
`STA: Store AC 1 47
`BUN: Branch UnconditionaUy 1 47
`BSA: Branch and Save Return Address 14 7
`ISZ: Increment and Skip If Zero 149
`Control Flowchart 1 49
`5-7
`
`Input-Output and Interrupt
`
`Input-Output Configuration
`1 51
`
`Input-Output Instructions
`1 52
`Program Interrupt 15 3
`
`Interrupt Cycle 1 56
`5-8 Complete Computer Description
`5-9 Design of Basic Computer
`Control Logic Gates 1 60
`
`Control of Registers and Memory 1 60
`
`Control of Single Flip-Flops 1 62
`Control of Common Bus 1 62
`5-10 Design of Accumulator
`Logic
`
`Control of AC Register 1 65
`Adder and Logic Circuit 1 66
`Problems
`References
`
`127
`
`132
`
`135
`139
`
`145
`
`150
`
`157
`157
`
`164
`
`167
`171
`
`CHAPTER SIX
`Programming the Basic Computer 173
`
`6-1 Introduction
`6-2 Machine Language
`
`173
`174
`
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`Contents vii
`
`6-3 Assembly Language
`Rules of the Language 1 79
`An Example 1 81
`
`Translation to Binary 1 82
`6-4 The Assembler
`
`
`Representation of Symbolic Program
`in Memory 1 84
`First Pass 1 85
`Secorui Pass 1 87
`6-5 Program Loops
`6-6 Programming
`
`Arithmetic and Logic
`Operations
`
`Multiplication Program 1 93
`
`Double-Precision Addition 1 96
`Logic Operations 1 97
`Shift Operations 1 97
`6-7 Subroutines
`
`
`Subroutines Parameters and Dara Linkage 200
`6-8 Input-Output
`Programming
`204
`
`Character Manipulation
`Program Interrupt 205
`Problems
`References
`
`179
`
`183
`
`190
`
`192
`
`198
`
`203
`
`208
`211
`
`CHAPTER SEVEN
`Microprogrammed Control 213
`
`7-1 Control Memory
`7-2 Address Sequencing
`Coruiitional Branching
`217
`
`Mapping of Instruction
`219
`Subroutines
`220
`7-3 Microprogram Example
`
`Computer Configuration 220
`
`Microinstruction Format 222
`
`Symbolic Microinstructions
`225
`The Fetch Routine 226
`
`Symbolic Microprogram 227
`Binary Microprogram 229
`
`213
`216
`
`220
`
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`

`viii Contents
`
`7-4 Design of Control Unit
`232
`
`Microprogram Sequencer
`Problems
`References
`
`231
`
`235
`238
`
`CHAPTER EIGHT
`Central Processing Unit
`
`241
`
`241
`242
`
`247
`
`260
`
`266
`
`8-1 Introduction
`8-2 General Register
`Organization
`Control Word 244
`Examples of Microoperations
`246
`8-3 Stack Organization
`
`Register Stack 247
`Memory Stack 249
`
`Reverse Polish Notation 251
`253
`
`Evaluation of Arithmetic Expressions
`8-4
`255
`
`Instruction Formats
`258
`
`Three-Address Instructions
`
`Tw:J-Address Instructions
`258
`
`One-Address Instructions
`259
`
`Zero-Address Instructions
`259
`RISC Instructions
`259
`8-5 Addressing
`Modes
`
`Numerical Example 264
`8-6 Data Transfer
`and Manipulation
`
`
`Data Transfer Instructions 267
`
`Data Manipulation Instructions
`268
`
`Arithmetic Instructions 269
`
`Logical and Bit Manipulation Instructions
`270
`Shift Instructions
`271
`8-7 Program Control
`Status Bit Conditions 274
`Conditional Branch Instructions 275
`
`
`Subroutine Call and Return 2 78
`Program Interrupt 279
`
`Types of Interrupts 281
`8-8 Reduced Instruction
`Set Computer (RISC)
`283
`CISC Characteristics
`RISC Characteristics
`284
`
`273
`
`282
`
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`

`Overlapped Register Window s 285
`B.,-keley ruse 1 288
`Problems
`References
`
`Contents ix
`
`291
`297
`
`CHAPTER N IN E
`and Vector Processing 299
`Pipeline
`
`Example: Three-Segment Instruction Pipeline 316
`
`9-1 Parallel
`Processing
`9-2 Pipelining
`
`General Considerations
`304
`9-3 Arithmetic
`Pipeline
`9-4 Instruction
`Pipeline
`
`
`Example: Four-Segment Instruction Pipeline 311
`Data Dependency
`313
`Handling of Branch Instructions 314
`9-5 R ISC Pipeline
`
`
`Delayed Load 317
`Delayed Branch 318
`9-6 Vector Processing
`Vector Op.,-ations 321
`Matrix Multiplication
`322
`Memory Interleaving
`324
`Sup...comput£rs
`325
`9-7 Array Processors
`Attached Array Processor 326
`SIMD Array Processor 327
`Problems
`References
`
`299
`302
`
`307
`310
`
`315
`
`319
`
`326
`
`329
`330
`
`CHAPTER TEN
`Computer Arithmetic 333
`
`10-1 Introduction
`333
`334
`10.2 Addition
`and Subtraction
`
`Addition and Subtraction with Signed-Magnitude
`Data 335
`
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`

`X Contents
`
`Hardware Implementation
`
`336
`
`Hardware Algorithm 337
`
`
`Addition and Subtraction with Signed-2's
`
`Complement Data 338
`340
`10-3 Multiplication
`Algorithms
`
`
`Hardware Implementation for Signed-Magnitude
`Data 341
`
`Hardware Algorithm 34 2
`
`Booth Multiplication Algorithm 343
`Array Multiplier
`346
`348
`10-4 Division
`Algorithms
`
`
`Hardware Implementation for Signed-Magnitude
`Data 349
`Divide
`Overflow
`351
`
`Hardware Algorithm 352
`Other Algorithms 35 3
`10-5 Floating-Point
`
`Arithmetic Operations
`Basic Considerations 354
`
`Register Configuration 357
`
`Addition and Subtraction 358
`360
`Multiplication
`Division 362
`10-6 Decimal Arithmetic
`Unit
`BCD Adder 365
`BCD Subtraction 368
`10-7 Decimal Arithmetic
`Operations
`
`Addition and Subtraction 3 71
`Multiplication
`371
`Division 374
`376
`Floating-Point Operations
`Problems
`References
`
`376
`380
`
`CHAPTER ELEVEN
`
`Input-Output Organization
`
`11-1 Peripheral
`Devices
`
`ASCII Alphanumeric Characters 383
`11-2 Input-Output
`Interface
`110 Bus and Interface Modules 386
`
`110 versus Memory Bus 387
`
`381
`
`381
`
`385
`
`354
`
`363
`
`369
`
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`Contents xi
`
`Isolated versus Memory-Mapped 110 388
`
`
`
`Example of 110 Interface 389
`11-3 Asynchronous
`Data Transfer
`
`Strobe Control 391
`Handshaking 393
`
`Asynchronous Serial Transfer 396
`
`
`Asynchronous Communication Interface 398
`
`
`First-In, First-Out Buffer 400
`11-4 Modes of Transfer
`Example of Programmed 110 403
`
`Interrupt-Initiated 110 406
`
`Software Considerations 406
`11-5 Priority
`Interrupt
`
`Daisy-Chaining Priority 408
`
`Parallel Priority Interrupt 409
`Priority Encoder 411
`
`Interrupt Cycle 412
`Software Routines 413
`
`Initial and Final Operations 414
`11-6 Direct Memory Access (DMA)
`DMA Controller 416
`DMA Transfer 418
`11-7 Input-Output
`
`Processor (lOP)
`CPU-lOP Communication
`422
`IBM 370 110 Channel 423
`Intel 8089 lOP 427
`11-8 Serial Communication
`
`Character-Oriented Protocol 432
`Transmission Example
`433
`Data Transparency
`436
`
`Bit-Oriented Protocol 437
`Problems
`References
`
`391
`
`402
`
`407
`
`415
`
`420
`
`429
`
`439
`442
`
`CHAPTER TWELVE
`Memory Organization 445
`
`12-1 Memory Hierarchy
`12-2 Main Memory
`RAM and ROM Chips 449
`
`445
`448
`
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`

`xii Contents
`
`Memory Address Map 4 50
`
`Memory Connection to CPU 452
`12-3 Auxiliary
`Memory
`Magnetic Disks 454
`Magnetic Tape 455
`12·4 Associative
`Memory
`Hardware Organization
`457
`March Logic 459
`Read Operation
`460
`Write Operation
`461
`12·5 Cache Memory
`
`Associative Mapping 464
`Mapping 465
`Direct
`Set-Associative Mapping
`467
`Writing into Cache 468
`Cache Initialization 469
`12-6 Virrual
`Memory
`Address Space and Memory Space 4 70
`Address Mapping Using Pages 472
`
`Associative Memory Page Table 474
`
`Page Replacement 4 75
`12· 7 Memory Management
`Hardware
`
`Segmented-Page Mapping 477
`
`Numerical Example 4 79
`482
`Memory Protection
`Problems
`References
`
`CHAPTER THIRTEEN
`Multiprocessors
`
`13-1 Characteristics
`of Multiprocessors
`13-2 Interconnection
`Structures
`491
`
`Time-Shared Common Bus
`Memory 493
`Multipart
`Crossbar Switch 494
`496
`
`Multistage Switching Network
`
`Hypercube Interconnection
`498
`13·3 lnterprocessor
`Arbitration
`System Bus 500
`
`452
`
`456
`
`462
`
`469
`
`476
`
`483
`486
`
`489
`
`489
`491
`
`500
`
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`Contents xiii
`
`Procedure 502
`Serial Arbitration
`
`Parallel Arbitration Logic
`503
`
`Dynamic Arbitration Algorithms 505
`13·4 lnterprocessor
`
`Communication and
`Synchronization
`
`lnterprocessor Synchronization
`507
`
`Mutual Exclusion with a Semaphore 508
`13-5 Cache Coherence
`
`Conditions for Incoherence
`509
`to the Cache Coherence
`Solutions
`Problem 510
`Problems
`References
`
`506
`
`509
`
`512
`514
`
`Index
`
`515
`
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`

`
`
`SECTION l-7 Sequential Circuits 3 1
`
`The next state of B in the state table is equal to 1 when the present state of A
`
`
`is 0 and input x is equal to 1. The output column is derived from the output
`equation
`
`y = Ax ' + Bx'
`
`of Fig. 1-25
`TABLE 1-4 State Table for Circuit
`
`B
`
`Present
`Next
`state Input state Output
`X
`A B
`A
`0
`0 0
`I
`0 0
`0
`0
`0 1
`1
`0
`0
`0 I
`0
`
`y
`0 0
`0 I
`0 0 1
`1 0
`1
`0 0 I
`I 0
`0
`0 0
`0
`0
`
`0
`0
`
`I
`
`state table
`
`The state table of any sequential circuit is obtained by the procedure used
`
`
`
`n input
`
`
`
`
`in this example. In general, a sequential circuit with m flip-flops,
`n
`
`
`
`
`state, will contain variables, and p output variables m columns for present
`
`
`The columns for inputs, m columns for next state, and p columns for outputs.
`
`present state and input columns are combined and under them we list the 2m + "
`
`
`
`
`binary combinations from 0 through 2m . , - 1. The next-state and output
`
`
`columns are functions of the present state and input values and are derived
`
`
`
`directly from the circuit or the Boolean equations that describe the circuit.
`
`state diagram
`
`State Diagram
`The information available in a state table can be represented graphically in a
`
`
`
`
`
`
`state diagram. In this type of diagram, a state is represented by a circle, and
`
`
`
`
`the transition between states is indicated by directed lines connecting the
`
`
`
`
`circles. The state diagram of the sequential circuit of Fig. 1-25 is shown in Fig.
`
`
`1-26. The state diagram provides the same information as the state table and
`
`
`is obtained directly from Table 1-4. The binary number inside each circle
`
`
`
`identifies the state of the flip-flops. The directed lines are labeled with two
`
`
`
`
`binary numbers separated by a slash. The input value during the present state
`
`is labeled first and the number after the slash gives the output during the
`
`
`
`
`
`present state. For example, the directed line from state 00 to 01 is labeled 1/0,
`
`
`
`meaning that when the sequential circuit is in the present state 00 and the input
`
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`

`
`
`32 CHAPTER O N E Digital Logic Circuits
`
`
`
`Figure 1�26 State diagrams of sequential circuit.
`
`
`
`is 1, the output is 0. After a clock transition, the circuit goes to the next state
`
`
`01. The same clock transition may change the input value. If the input changes
`
`to 0, the output becomes 1, but if the input remains at 1, the output stays at
`
`
`0. This information is obtained from the state diagram along the two directed
`
`
`lines emanating from the circle representing state 01. A directed line connect­
`
`
`ing a circle with itself indicates that no change of state occurs.
`
`There is no difference between a state table and a state diagram except
`
`
`in the manner of representation. The state table is easier to derive from a given
`
`
`logic diagram and the state diagram follows directly from the state table. The
`
`
`state diagram gives a pictorial view of state transitions and is the form suitable
`
`
`
`
`
`for human interpretation of the circuit operation. For example, the state dia­
`
`gram of Fig. 1-26 clearly shows that starting from state 00, the output is 0 as
`
`
`long as the input stays at 1. The first 0 input after a string of 1's gives an output
`
`
`of 1 and transfers the circuit back to the initial state 00.
`
`Design Example
`The procedure for designing sequential circuits will be demonstrated by a
`
`
`
`
`
`
`
`specific example. The design procedure consists of first translating the circuit
`
`
`specifications into a state diagram. The state diagram is then converted into a
`
`
`state table. From the state table we obtain the information for obtaining the
`
`logic circuit diagram.
`We wish to design a clocked sequential circuit that goes through a se­
`
`
`
`
`quence of repeated binary states 00, 01, 10, and 11 when an external input x
`whenx = 0. This type
`
`is equal to 1. The state of the circuit remains unchanged
`
`
`of circuit is called a 2-bit binary counter because the state sequence is identical
`
`
`
`
`to the count sequence of two binary digits. Input x is the control variable that
`specifies when the count should proceed.
`The binary counter needs two flip-flops to represent the two bits. The
`
`
`
`
`
`state diagram for the sequential circuit is shown in Fig. 1-27. The diagram is
`
`
`drawn to show that the states of the circuit follow the binary count as long as
`
`binary counter
`
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