(19) United States
`(12) Patent Application Publication (10) Pub. No.: US 2012/0056681 A1
`Lee
`
`(43) Pub. Date: Mar. 8, 2012
`
`US 20120056681A1
`
`(54) SIGNAL AMPLIFICATION CIRCUITS FOR
`RECEIVING/TRANSMITTING SIGNALS
`ACCORDING TO INPUT SIGNAL
`
`(52) us. Cl. ........................................................ 330/310
`
`(57)
`
`ABSTRACT
`
`(76)
`
`Inventor:
`
`Chih—Hung Lee, Chiayi Hsien
`(TW)
`
`(21) Appl. No.:
`
`12/876,237
`
`(22)
`
`Filed:
`
`Sep. 6, 2010
`
`Publication Classification
`
`(51)
`
`Int. Cl.
`H03F 3/04
`
`(2006.01)
`
`One exemplary signal amplification circuit used for process-
`ing an input signal includes an input stage, a plurality of
`output stages, and a selecting stage. The input stage has an
`input node for receiving the input signal and an output node
`for outputting an intermediate signal. The output stages are
`coupled to a plurality of output ports of the signal amplifica-
`tion circuit, respectively. Each of the output stages generates
`a corresponding processed signal to a corresponding output
`port according to a gain and a signal derived from the inter-
`mediate signal of the input stage when enabled. The selecting
`stage is arranged for selectively coupling the output node of
`the input stage to at least one of the output stages.
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`Patent Application Publication
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`Mar. 8, 2012 Sheet 1 of8
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`Patent Application Publication
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`Mar. 8, 2012 Sheet 8 0f 8
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`US 2012/0056681 A1
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`US 2012/0056681A1
`
`Mar. 8, 2012
`
`SIGNAL AMPLIFICATION CIRCUITS FOR
`RECEIVING/TRANSMITTING SIGNALS
`ACCORDING TO INPUT SIGNAL
`
`BACKGROUND
`
`[0001] The disclosed embodiments ofthe present invention
`relate to amplifying an input signal, and more particularly, to
`signal amplification circuits which receive/transmit signals
`according to an input signal.
`[0002] As people around the world embrace mobile lif-
`estyles, there is a growing demand for their mobile devices to
`support several different kinds of radio connections. For
`example, a mobile device may have multiple wireless con-
`nections (e.g., a Bluetooth connection and a WiFi connection)
`at the same time. If transmitters/receivers for different radio
`
`connections are implemented in a multi-radio device indi-
`vidually, the hardware cost and the chip size may be high.
`Therefore, regarding a multi-radio device, there is a need for
`receiving/transmitting signals according to one input. For
`example, if a low-noise amplifier (LNA) of the multi-radio
`device can be configured to commonly amplify a plurality of
`radio-frequency signals, the LNA shared between different
`radio connections, such as the Bluetooth connection and the
`WiFi connection, would reduce the hardware cost and the
`chip size of the multi-radio device. Thus, designing a signal
`amplification circuit which can receive/transmit signals
`according to one input becomes an important
`issue for
`designers in this field.
`
`SUMMARY
`
`In accordance with exemplary embodiments of the
`[0003]
`present invention, signal amplification circuits which receive/
`transmit signals according to an input signal are proposed to
`solve the above-mentioned problem.
`[0004] According to a first aspect of the present invention,
`an exemplary signal amplification circuit is disclosed. The
`exemplary signal amplification circuit is for processing an
`input signal, and includes an input stage, a plurality of output
`stages, and a selecting stage. The input stage has an input
`node for receiving the input signal and an output node for
`outputting an intermediate signal. The output stages are
`coupled to a plurality of output ports of the signal amplifica-
`tion circuit, respectively. Each of the output stages generates
`a corresponding processed signal to a corresponding output
`port according to a gain and a signal derived from the inter-
`mediate signal ofthe input stage when enabled. The selecting
`stage is arranged for selectively coupling the output node of
`the input stage to at least one of the output stages.
`[0005] According to a second aspect of the present inven-
`tion, an exemplary signal amplification circuit is disclosed.
`The exemplary signal amplification circuit is for processing
`an input signal and includes a plurality of individual amplifier
`blocks. The individual amplifier blocks are coupled to a plu-
`rality of output ports of the signal amplification circuit,
`respectively. Each ofthe individual amplifier blocks includes:
`an input stage, having an input node for receiving the input
`signal; an output stage, coupled to a corresponding output
`port of the signal amplification circuit, for generating a cor-
`responding processed signal to the corresponding output port
`according to a gain and a signal derived from an intermediate
`signal of the input stage; and a selecting stage arranged for
`selectively coupling the input stage to the output stage.
`
`[0006] According to a third aspect of the present invention,
`an exemplary signal amplification circuit is disclosed. The
`exemplary signal amplification circuit is for processing an
`input signal, and includes an input stage and a plurality of
`output stages. The input stage has an input node for receiving
`the input signal and a plurality of output nodes. The output
`stages are coupled to a plurality of output ports of the signal
`amplification circuit, respectively. In addition, the output
`stages are directly connected to the output nodes of the input
`stage, respectively. Each of the output stages generates a
`corresponding processed signal to a corresponding output
`port according to a gain and a signal derived from an inter-
`mediate signal of the input stage when enabled.
`[0007] These and other objectives of the present invention
`will no doubt become obvious to those of ordinary skill in the
`art after reading the following detailed description of the
`preferred embodiment that is illustrated in the various figures
`and drawings.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 is a diagram illustrating a first exemplary
`[0008]
`implementation of a signal amplification circuit according to
`the present invention.
`[0009]
`FIG. 2 is a diagram illustrating a second exemplary
`implementation of a signal amplification circuit according to
`the present invention.
`[0010]
`FIG. 3 is a diagram illustrating a third exemplary
`implementation of a signal amplification circuit according to
`the present invention.
`[0011]
`FIG. 4 is a diagram illustrating a fourth exemplary
`implementation ofa signal amplification circuit according to
`the present invention.
`[0012]
`FIG. 5A is a simplified diagram illustrating a portion
`of a transceiver with a matching network shared between a
`transmitting circuit and a receiving circuit according to one
`exemplary design of the present invention.
`[0013]
`FIG. 5B is a simplified diagram illustrating a portion
`of a transceiver with a matching network shared between a
`transmitting circuit and a receiving circuit according to
`another exemplary design of the present invention.
`[0014]
`FIG. 6 is a diagram illustrating a fifth exemplary
`implementation of a signal amplification circuit according to
`the present invention.
`[0015]
`FIG. 7 shows an exemplary implementation of an
`input stage used in a differential signal amplification circuit
`according to the present invention.
`
`DETAILED DESCRIPTION
`
`[0016] Certain terms are used throughout the description
`and following claims to refer to particular components. As
`one skilled in the art will appreciate, manufacturers may refer
`to a component by different names. This document does not
`intend to distinguish between components that differ in name
`but not function. In the following description and in the
`claims, the terms “include” and “comprise” are used in an
`open-ended fashion, and thus should be interpreted to mean
`“include, but not limited to .
`.
`. ”. Also, the term “couple” is
`intended to mean either an indirect or direct electrical con-
`
`nection. Accordingly, if one device is coupled to another
`device, that connection may be through a direct electrical
`connection, or through an indirect electrical connection via
`other devices and connections.
`
`

`

`US 2012/0056681A1
`
`Mar. 8, 2012
`
`FIG. 1 is a diagram illustrating a first exemplary
`[0017]
`implementation of a signal amplification circuit according to
`the present invention. The exemplary signal amplification
`circuit 100 is for processing an input signal VIN to be
`received/transmitted. In other words, the signal amplification
`circuit 100 canbe part of a receiver or part ofa transmitter. For
`example, regarding signal reception, the input signal VIN
`may include a plurality of a radio-frequency signals (e.g., a
`Bluetooth signal and a WiFi signal) received by a single
`antenna (not shown), and a plurality of received signals cor-
`responding to the radio-frequency signals are generated as
`outputs of the signal amplification circuit 100. Regarding
`signal transmission, a plurality of signals to be transmitted are
`generated as outputs of the signal amplification circuit 100
`according to the same radio -frequency signal included in the
`input signal VIN. In this exemplary implementation, the sig-
`nal amplification circuit 100 includes an amplifier block 101
`and a matching network 108. The amplifier block 101
`includes, but is not limited to, an input stage 102, a selecting
`stage 104, and a plurality of output stages 106_1-106_N. The
`matching network 108 is coupled between an input port PM of
`the signal amplification circuit 100 and an input node N1." of
`the input stage 102, and implemented for providing desired
`impedance matching. In a case where the signal amplification
`circuit 100 serves as a low-noise amplifier in a receiver of a
`multi-radio device, the signal amplification circuit 100 is
`capable of supporting multiple radio connections such as a
`Bluetooth connection and a WiFi com1ection. Therefore, the
`matching network (e.g., a broadband matching network) 108
`should be properly designed to meet the impedance matching
`requirements of the supported radio connections.
`[0018] The input signal VIN is received by the input node
`NZ." of the input stage 102 via the matching network 108. In
`addition, an alternating-current (AC) coupling capacitor C is
`also placed between the matching network 108 and the input
`stage 102. Therefore, the input signal VIN passing through
`the matching network 108 and the AC coupling capacitor C is
`then processed by the input stage 102 according to a transcon-
`ductance ofthe input stage 102. As shown in FIG. 1, the input
`stage 102 includes a plurality of transistors M_1-M_J con-
`nected in parallel for setting the transconductance ofthe input
`stage 102. Regarding each of the transistors M_1-M_J, a
`control terminal (e.g., a gate electrode) is coupled to the input
`node Ni", and connection terminals (e.g., a drain electrode
`and a source electrode) are coupled to an output node N0,” of
`the input stage 102 and a reference voltage (e.g., a ground
`voltage GND), respectively. It should be noted that the par-
`allel connection of transistors can be regarded as a single
`transistor with an equivalent size. That is, the input stage 102
`is implemented by a transistor element made of a single
`transistor or made of a plurality of transistors connected in
`parallel and having gate electrodes connected to each. Due to
`a proper transconductance setting of the input stage 102, the
`input signal VIN is converted into an intermediate signal I at
`the output node Now ofthe input stage 102. It should be noted
`that the input impedance of the input stage 102 viewed from
`the matching network 108 can be fixed while the number of
`turned-on transistors M_1-M_J is fixed regardless of the
`operation mode at which the signal amplification circuit 100
`stays. Taking a receiver which has the signal amplification
`circuit 100 employed therein for example, the noise figure is
`low under such an amplifier configuration shown in FIG. 1.
`[0019] The selecting stage 104 is utilized for selectively
`out
`coupling the output node N to at least one of the output
`
`stages 106_1-106_N. In this exemplary implementation, the
`selecting stage 104 includes a plurality of transistor elements
`MS_1-MS_N coupled to the output stages 106_1 -106_N,
`respectively. The transistor elements MS_1-MS_N act as
`switches controlled by control
`signals VSWil'VSWiNs
`respectively. More specifically, each of the transistor ele-
`ments MS_1 -MS_N has a control terminal for receiving a
`corresponding control signal, a first connection terminal
`coupled to a corresponding output stage, and a second con-
`nection terminal coupled to the output node N0,” of the input
`stage 102.
`[0020] The output stages 106_1-106_N are coupled to a
`plurality of output ports Pom 1-Pom N of the signal amplifi-
`cation circuit 100, respectively. The output stages 106_1-
`106_N are configured to generate a plurality of processed
`signals VOUT_1-VOUT_N, respectively. More specifically,
`each of the output stages 106_1-106_N generates a corre-
`sponding processed signal to a corresponding output port
`according to a gain and a signal derived from the intermediate
`signal I of the input stage 102 when enabled. In this exem-
`plary implementation, each output stage includes a plurality
`of transistor elements. As shown in FIG. 1, the output stage
`106_1 includes a plurality of transistor element pairs 112_
`11-112_1K, wherein each ofthe transistor element pairs 112_
`11-112_1K includes a first transistor element (e.g., M1_1, .
`.
`.
`, or M1_K) and a second transistor element (e.g., M1'_1, .
`.
`.
`, or Ml'_K). Similarly, the output stage 106_N includes a
`plurality of transistor element pairs 112_N1-112_NL,
`wherein each ofthe transistor element pairs 1 12_N1 -1 12_NL
`includes a first transistor element (e.g., MN_1, .
`.
`.
`, or MN_L)
`and a second transistor element (e. g., MN'_1, .
`.
`.
`, or MN'_L).
`The first transistor elements have control terminals for receiv-
`ing first control signals D1_1-D1_K, .
`.
`.
`, and DN_1-DN_L,
`first connection terminals coupled to corresponding output
`ports PiouLl-POHLN, and second connection terminals
`coupled to the selecting stage 104; in addition, the second
`transistor elements M1'_1-M1'_K, .
`.
`.
`, and MN'_1 -MN'_L
`have control terminals for receiving second control signals
`D1'_1-D1'_K, .
`.
`.
`, and DN'_1-DN'_L, first connection ter-
`minals coupled to a reference voltage (e.g., the supply voltage
`VDD), and second connection terminals coupled to the
`selecting stage 104.
`[0021]
`It should be noted that the number of transistor
`element pairs in one output stage may be adjustable according
`to actual design requirements. For example, in one embodi-
`ment, the number oftransistor element pairs 112_11-112_1K
`may be equal to the number of transistor element pairs 112_
`N1 -1 12_NL; however, in another embodiment, the number of
`transistor element pairs 112_11-112_1K may be different
`from the number of transistor element pairs 112_N1-112_
`NL
`
`[0022] Regarding each of the output stages 106_1-106_N,
`the gain can be adaptively adjusted by controlling an on/off
`status of each transistor element included in the output stage.
`Taking the output stage 106_1 for example, only one of the
`first transistor element and the second transistor element
`
`included in each transistor element pairs is turned on to con-
`trol the current passing through a corresponding inductive
`load (i .e., the inductor L1). That is, a second transistor element
`in a transistor element pair is turned off by a second control
`signal when a first transistor element included in the same
`transistor element pair is turned on by a first control signal,
`and the first transistor element is tumed offby the first control
`signal when the second transistor element is turned on by the
`
`

`

`US 2012/0056681A1
`
`Mar. 8, 2012
`
`second control signal. Therefore, the current passing through
`the inductor Ll has a maximum value (i.e., the current passing
`through the turned-on transistor element MS_1) when all of
`the first transistor elements M1_1-M1_K are turned on under
`the control of the first control signals D1_1-D1_K and all of
`the second transistor elements M1'_1-M1'_K are turned off
`under the control of the second control signals D1'71-D1'7K.
`Similarly, regarding the output stage 106_N, the current pass-
`ing through a corresponding inductive load (i.e., the inductor
`LN) has a maximum value (e.g., the current passing through
`the turned-on transistor element MS_N) when all of the first
`transistor elements MN_1-MN_L are turned on under the
`control of the first control signals DN_1-DN_L and all of the
`second transistor elements MN'_1-MN'_L are turned off
`under the control ofthe second control signals DN'_1-DN'_L.
`To put it simply, the more the tumed-on first transistor ele-
`ments in an output stage, the greater the current passing
`through an inductive load coupled to the output stage. In this
`way, the gain of the output stage can be properly set to a
`desired value.
`
`[0023] The exemplary signal amplification circuit 100 can
`operate under an operational mode being either a shared
`mode or a combo mode. The switching between the shared
`mode and the combo mode can be controlled by the selecting
`stage 104 or the output stages 106_1-106_N. Assume that the
`selecting stage 104 is used to control the operational mode of
`the signal amplification circuit 100. When only one of the
`transistor elements MS_l-MS_N is turned on, the signal
`amplification circuit 100 operates under the shared mode as
`only one of the output stages 106_1-106_N is allowed to be
`connected to the input stage 102. For example, the output port
`Poutil is coupled to a first radio signal processing system
`(e.g., a WiFi receiver/transmitter) and the output port PMLN
`is coupled to a second radio signal processing system (e.g., a
`Bluetooth receiver/transmitter). When only the WiFi function
`ofthe multi-radio device is required to be active, the transistor
`element MS_1 is turned on, whereas the remaining transistor
`elements in the selecting stage 104 are turned off. In addition,
`the gain ofthe enabled output stage 106_1 should be properly
`configured to meet the WiFi requirements. Similarly, when
`only the Bluetooth function of the multi-radio device is
`required to be active, the transistor element MS_N is turned
`on, whereas the remaining transistor elements in the selecting
`stage 104 are turned off. In addition, the gain of the enabled
`output stage 106_N shouldbe properly configured to meet the
`requirements of the Bluetooth requirements.
`[0024] However, when a plurality of specific transistor ele-
`ments in the selecting stage 104 are turned on concurrently,
`the signal amplification circuit 100 operates under the combo
`mode as a plurality of specific output stages included in the
`output stages 106_1-106_N are allowed to be connected to
`the input stage 102 at the same time. For example, when both
`ofthe WiFi function and Bluetooth function ofthe multi-radio
`
`device are required to be active, the transistor elements MS_1
`and MS_N are both turned on, whereas the remaining tran-
`sistor elements in the selecting stage 104 are turned off. In
`addition, the gains of the concurrently enabled output stages
`106_1 and 106_N should be properly configured to meet the
`requirements. It should be noted that the selecting stage 104
`in this exemplary implementation is also arranged to increase
`isolation (or decrease coupling) between the specific output
`stages (e. g., output stages 106_1 and 106_N) which are con-
`currently enabled. In a case where the selecting stage 104 is
`omitted, the output stages 106_1-106_N would be directly
`
`connected to the input stage 102. When the output stage
`106_N is controlled to adjust it gain, the coupling effect
`between the concurrently enabled output stages 106_N and
`106_1 results in a significant gain variation ofthe output stage
`106_1. However, with the help of the selecting stage 104
`implemented between output stages, the undesired coupling
`effect can be effectively mitigated. Therefore, when the out-
`put stage 106_N is controlled to adjust it gain, the gain varia-
`tion of the output stage 106_1 caused by the gain tuning
`operation of the output stage 106_N can be reduced due to
`increased isolation provided by the selecting stage 104 imple-
`mented between the output stages 106_N and 106_1.
`[0025]
`In an altemative design, the output stages 106_1-
`106_N may be used to control the operational mode of the
`signal amplification circuit 100. In other words, in addition to
`setting the gain applied to a signal passing therethrough, each
`ofthe output stages 106_1-106_N is further arranged to deter-
`mine if a processed signal is generated at a corresponding
`output port, and therefore control whether the output stage
`should be enabled. Taking the output stage 106_1 for
`example, if the output stage 106_1 is required to be enabled
`for generating the corresponding processed signal VOUT_1,
`the output stage 106_1 is enabled by making each of the
`transistor element pairs 112_11-112_1K have one tumed-on
`transistor element and one turned-off transistor element.
`
`However, if the output stage 106_1 is not required to be
`enabled for generating the corresponding processed signal
`VOUT_1, the output stage 106_1 is disabled by turning off
`both of the first transistor element and the second transistor
`
`element included in each of the transistor element pairs 112_
`11-112_1K. As a result, when the output stage 106_1 is dis-
`abled, the transistor element MS_1 will be turned off regard-
`less of the voltage level of the control voltage szil- In one
`exemplary design, each of the control voltages szil'
`VSWiN is at a high logic level, and the output stages 106_1-
`106_N control the signal amplification circuit 100 to operate
`under the shared mode or combo mode by properly setting the
`first control signals M1_1-M1_K, .
`.
`.
`, and MN_1-MN_K and
`the second control signals M1'_1-M1'_L, .
`.
`.
`, and MN'_1
`-MN'_L. For example, when only the WiFi function of the
`multi-radio device is required to be active (i.e., the signal
`amplification circuit 100 should operate under the shared
`mode),
`the output stage 106_1 is enabled, whereas the
`remaining output stages are disabled. In addition, the gain of
`the enabled output stage 106_1 should be properly configured
`to meet the WiFi requirements. Similarly, when only the
`Bluetooth function of the multi-radio device is required to be
`active (i.e., the signal amplification circuit 100 should operate
`under the shared mode), the output stage 106_N is enabled,
`whereas the remaining output stages are disabled. In addition,
`the gain ofthe enabled output stage 1 06_N should be properly
`configured to meet the Bluetooth requirements. However,
`when both ofthe WiFi function and Bluetooth function ofthe
`
`multi-radio device are required to be active (i.e., the signal
`amplification circuit 100 should operate under the combo
`mode), the output stages 106_1 and 106_N are both enabled,
`whereas the remaining output stages are disabled. In addition,
`the gains ofthe concurrently enabled output stages 106_1 and
`106_N should be properly configured to meet the WiFi
`requirements and Bluetooth requirements.
`[0026]
`FIG. 2 is a diagram illustrating a second exemplary
`implementation of a signal amplification circuit according to
`the present invention. Similar to the exemplary signal ampli-
`fication circuit 100 mentioned above, the exemplary signal
`
`

`

`US 2012/0056681A1
`
`Mar. 8, 2012
`
`amplification circuit 200 is for processing the input signal
`VIN to be received or transmitted. That is, the signal ampli-
`fication circuit 200 can be part of a receiver or part of a
`transmitter. In this exemplary implementation, the signal
`amplification circuit 200 includes a plurality of amplifier
`blocks 202_1-202_N and a matching network 210. Each of
`the amplifierblocks 202_1 -202_N includes, but is not limited
`to, an input stage 204_1,
`.
`.
`.
`, or 204_N, a selecting stage
`206_1, .
`.
`.
`, or 206_N, and an output stages 208_1, .
`.
`.
`, or
`208_N. Please note that the amplifier blocks 202_1-202_N
`can be individual functional blocks, meaning that each of the
`amplifier blocks 202_1-202_N respectively has its own input
`stage, selecting stage, and output stage. More specifically,
`none of the input stage, selecting stage, and output stage
`belonging to one individual amplifier block is shared with
`other individual amplifier block(s). The matching network
`210 is coupled between an input port Pl." of the signal ampli-
`fication circuit 200 and the input nodes NiLl-NiLN of the
`respective input stages 204_1 -204_N, and implemented for
`providing desired impedance matching. The matching net-
`work (e.g., a broadband matching network) 210 should be
`properly designed to meet the impedance matching require-
`ments. The input signal VIN is transmitted to the input nodes
`Ninil -NZ.LN ofthe input stages 204_1 -204_N via the match-
`ing network 210 and an AC coupling capacitor C. Each ofthe
`input stages 204_1-204_N has a plurality of output nodes. For
`example, the input stages 204_1 includes output nodes Nomi
`11-N0m71J, and the input stages 204_N includes output nodes
`0at,
`0at
`N Nl-N NI. Each of the input stages 204_1 -204_N
`includes a plurality of transistor elements M1_1-M1_J, .
`.
`.
`,
`or MN_1-MN_I each having a control terminal coupled to the
`input node of the input stage, a first connection terminal
`coupled to an output node of the input stage, and a second
`connection terminal coupled to a reference voltage (e. g., the
`ground voltage GND). As shown in FIG. 2, second c01mec-
`tion terminals of the transistor elements in the same input
`stage are connected to each other. It should be noted that each
`of the input stages 204_1 -204_N is not required to have the
`same number of transistor elements. That is, the number of
`transistor elements implemented in each of the input stages
`204_1 -204_N can be adjusted according to actual design
`consideration. The transistor elements in each input stage are
`used to control the transconductance of the input stage. For
`example, the transconductance of the input stage would be
`increased when more transistor elements included in the input
`stage are turned on.
`[0027]
`In each amplifier block, the selecting stage 206_1, .
`.
`.
`, or 206_N is used to selectively couple the input stage
`204_1, .
`.
`.
`, or 204_N to the output stage 208_1, .
`.
`.
`, or
`208_N, and includes a plurality of transistor elements
`MS_ll-MS_1J, .
`.
`.
`, or MS_N1-MS_NI. For example, the
`selecting stage 206_1 selectively couples the input stage
`204_1 to the output stage 208_1, and includes transistor ele-
`ments MS_ll-MS_1J each having a control terminal for
`receiving a control signal VSW_ll, .
`.
`.
`, or VSW_lJ, a first
`connection terminal coupled to the output stage 208_1, and a
`second connection terminal coupled to a corresponding out-
`put node Nomill, .
`.
`.
`, or NouLlJ of the input stage 204_1.
`Similarly, the selecting stage 206_N selectively couples the
`input stage 204_N to the output stage 208_N, and includes
`transistor elements MS_N1-MS_NI each having a control
`terminal for receiving a control signal VSW_Nl,
`.
`.
`.
`, or
`VSW_NI, a first connection terminal coupled to the output
`stage 208_N, and a second connection terminal coupled to a
`
`, or NOHLNI of the
`.
`.
`corresponding output node NOHLNl, .
`input stage 204_N. It should be noted that each transistor
`element in the selecting stages 206_1-206_N acts as a switch
`controlled by a corresponding control signal.
`[0028] The output stages 208_1-208_N are coupled to a
`outi
`7
`plurality of output ports P
`1'P0m N of the signal amplifi-
`cation circuit 100, respectively, and are configured to gener-
`ate a plurality of processed signals VOUT_1-VOUT_N,
`respectively. More specifically, in each amplifier block, the
`output stage is coupled to a corresponding output port of the
`signal amplification circuit 200, and implemented for gener-
`ating a corresponding processed signal (e.g., VOUT_1, .
`.
`. , or
`VOUT_N) to the corresponding output port (e.g., PouLl, .
`.
`.
`, or PoutiN) according to a gain and a signal derived from an
`intermediate signal (e.g., I 1,
`.
`.
`. , or IN) ofthe input stage when
`enabled. As shown in FIG. 2, the output stage 208_1 includes
`a plurality of transistor element pairs 212_11-212_1K,
`wherein each of the transistor element pairs 212_11-212_1K
`includes a first transistor element (e.g., M1_1, .
`.
`.
`, or M1_K)
`and a second transistor element (e.g., M1'_1, .
`.
`.
`, or M1'_K).
`Similarly, the output stage 208_N includes a plurality of
`transistor element pairs 212_N1-212_NL, wherein each of
`the transistor element pairs 212_N1-212_NL includes a first
`transistor element (e.g., MN_1, .
`.
`.
`, or MN_L) and a second
`transistor element (e.g., MN'_1 ,
`.
`.
`.
`, or MN'_L). Therefore,
`regarding the output stage 208_1, the current passing through
`a corresponding conductive load (e. g., the inductor L1) has a
`maximum value (i.e., the current I 1 passing through the input
`stage 204_1 via the selecting stage 206_1) when all ofthe first
`transistor elements M1_1-M1_K are turned on under the
`control of the first control signals D1_1-D1_K and all of the
`second transistor elements M1'_1-M1'_K are turned offunder
`the control of the second control signals D1'_1-D1'_K. Simi-
`larly, regarding the output stage 208_N, the current passing
`through a corresponding inductive load (i.e., the inductor LN)
`has a maximum value (e.g., the current INpassing through the
`input stage 204_N via the selecting stage 206_N) when all of
`the first transistor elements MN_1-MN_K are turned on
`under the control ofthe first control signals DN_1-DN_K and
`all of the second transistor elements MN_1-MN'_K are
`turned off under the control of the second control signals
`DN'_1-DN'_K. As a person skilled in the art can readily
`understand operations ofthe output stages after reading above
`paragraphs directed to the output stages shown in FIG. 1,
`further description is therefore omitted here for brevity.
`[0029] The signal amplification circuit 200 can operate
`under an operational mode being either a shared mode or a
`combo mode. The switching between the shared mode and
`the combo mode can be controlled by the selecting stages
`206_1-206_N or the output stages 208_1-208_N. Assume
`that the selecting stages 206_1-206_N are used to control the
`operational mode of the signal amplification circuit 100.
`When only one of the selecting stages 206_1-206_N has
`turned-on transistor element(s), the signal amplification cir-
`cuit 200 operates under the shared mode as only one of the
`output stages 208_1-208_N is allowed to be connected to a
`corresponding input stage. For example,
`the output port
`Poutil is coupled to a first radio signal processing system
`(e.g., a WiFi receiver/transmitter) and the output port PouLN
`is coupled to a second radio signal processing system (e.g., a
`Bluetooth receiver/transmitter). When only the WiFi function
`of the multi-radio device is required to be active, at least one
`of the transistor elements MS_ll-MS_1] included in the
`selecting stage 206_1 is turned on, whereas all transistor
`
`

`

`US 2012/0056681A1
`
`Mar. 8, 2012
`
`elements in the remaining selecting stages of the signal
`amplification circuit 200 are turned off. In addition, the gain
`of the enabled output stage 208_1 should be properly config-
`ured to meet the WiFi requirements. Similarly, when only the
`Bluetooth function of the multi-radio device is required to be
`active, at least one of the transistor elements MS_N1-MS_NI
`included in the selecting stage 206_N is turned on, whereas
`all ofthe transistor elements in the remaining selecting stages
`of the signal amplification circuit 200 are turned off. In addi-
`tion