1111111111111/IIHlllrll'~mr,111111 II 111111111111111
`3 0611 00098 2817
`
`IPR2019-00129
`Qualcomm 2030, p. 1
`
`

`

`l t
`
`Design of Analog CMOS
`Integrated Circuits
`
`rd
`
`Behzad Razavi
`Professor of .Electrical Engineering
`University of California, Los Angeles
`
`llLINOIS INSTITUTE OF TECHNOLOGY
`PA.UL V. GA.LV!N LIBRARY
`35 \~EST 33RD STHEET
`CHICAGO, IL 60616
`
`Boston Burr Ridge, IL Dubuque, IA Madison, WI
`New York San Francisco St. Louis
`Bangkok Bogota Caracas Lisbon London Madrid Mexico City
`Milan New Delhi Seoul Singapore Sydney Taipei Toronto
`
`IPR2019-00129
`Qualcomm 2030, p. 2
`
`

`

`McGr~w-Hill Higher Education zz
`
`A Divisio11 ofTheMcGru1v•HilLCur11pt111i~)
`
`DESIGN OF ANALOG CMOS INTEGRATED CIRCUITS
`Published by McGraw-Hill, an imprint of The McGraw-Hill Companies , Inc. 1221 Avenue of the Americas,
`New York, NY, 10020. Copyright© 2001 , by The McGrawaHill Companies, Inc. All rights reserved. no part of
`this publication may be reprodut:ed or distributed in any form or by any means, or stored in a database or retrieval
`system, without the prior writren consent of The McGraw-Hill Companies, Inc. , including, but not limited to, in
`any network or other ciectronic storage or transmission, or broadcast tor distance learning.
`Some ancillaries, including electronic and print components, may not be available to customers outside the United
`States.
`
`This book is printed on acid-free paper.
`
`7 8 9 0 FGR/FGR O 9 8 7
`
`ISBN-13: 978-0-07-238032-3
`ISBN-10: 0-07-238032-2
`Vice president/Editor-in-chief: Kevin T. Kane
`Publisher: T'l10111as Casson ·
`Sponsoring editor: Caiherine Fields
`Developmental editor: Mic/ie/le L. Flomenh.oft
`Senior marketing manager: John T Wannemach.er
`Project manager: Jim. Labeots
`Production supervisor: Gina Hangns
`Senior designer: Kiera Cu1111ingh.am
`New mtdia: Phillip Meek
`Compositor: illleractive Composition Corporation
`Typeface: 10/12 Times Roman
`Printer: Quebecor World Fairfield
`
`Library of Congress Cataloging-in-Publication Data
`
`Razavi, Behzad.
`Design of analog CMOS integrated circuits/ Behzad Razavi.
`p. cm.
`ISBN 0-07-238032-2 (alk. paper)
`l. Linear inlegrale<l t:ircuits-Design and construction. 2. Metai oxide semiconductors,
`Complementary. I. Title.
`
`TK7874.654. R39 2001
`621.39'732-dc2J
`
`00-044789
`
`IPR2019-00129
`Qualcomm 2030, p. 3
`
`

`

`Contents
`
`About the Author. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii
`Preface. . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Acknowledgments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`
`1x
`xi
`
`1 Introduction to Analog Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`1 . 1 Why Analog? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`1.2 Why Integrated? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`1.3 Why CMOS?. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`1.4 Wny This Book? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`1.5 General Concepts . .... ... ................... . .. ................... . . ,
`1.5.1 Levels of Abstraction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`J .5 .2 Robust Analog Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`
`1
`1
`6
`6
`;
`7
`7
`7
`
`9
`2 Basic lVIOS Device Physics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`l 0
`2.1 General Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`10
`2.1 . l MOSF'.2T as a Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`2.1.2 MOSFET Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
`2.1.3 MOS Symbols............................ . .... . ....... . .......
`12
`2.2 MOS IJV Characlerislics. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`13
`2:2.1 Threshold Voltage . ....................... . ....... . ..... . .. . . ...
`13
`2.2.2 Derivation of Lrv Characteristics.. ... ........... . .. . ...... .... . . .
`15
`2.3 Second-Order Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
`2.4 MOS Device Models. . ................................. ...... .... . ... 28
`2.4.1 MOS Device Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
`2.4.2 MOS Device Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`29
`2.4.3 MOS Small-Signal tv!odel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
`2.4.4 MOS SPICE models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
`2.4.5 NMOS versus PMOS Devices ... ·.:':;." ·.·. .......................... 37
`2.4.6 Long-Channel versus Short-Ch~'iiheh:5evices.. . . . . . . . . . . . . . . . . . . . . 38
`
`xv
`
`IPR2019-00129
`Qualcomm 2030, p. 4
`
`

`

`xvi
`
`Contents
`
`3 Single-Stage Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
`3.1 Basic Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`47
`3.2 Common-Source Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`48
`3.2. l Common-Source Stage with Resistive Load...... . .. . ..... ... .... . 48
`3.2.2 CS Stage with Diode-Connected Load.. ... . ..... .. . ........... . .. 53
`3.2.3 CS Stage with Current-Source Load .... . . . . . . . . . . . . . . . . . . . . . . . . . . 58
`3.2.4 CS Stage with Triode Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
`3.2.5 CS Stage with-Source Degeneration .... . . ........... . . .. ....... . .
`60
`67
`3.3 Source Follow·cr . . ....... .
`3.4 Common-Gale Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`76
`3.5 Cascade Stage . ... ... ....... .. .. . .. .. . , .. , .... ,. . . .. . .. . ........ . .. . .
`83
`3.5. l Folded Cascode..... .. . .. . . ... .. . .... . . . .. . . ... ....... . ........ 90
`3.6 Choice of Device Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`92
`
`4 Differential Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
`4.1 Single-Ended and Differential Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
`4.2 Basic Differential Pair .. ... · . ... .. ... ........ . ..... .......... ...... ..... 103
`104
`4.2.1 Qualitative Analysis ...... . .... .... .. .
`4.2.2 Quantitative Analysis.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
`4.3 Common-Mode Response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . l 18
`4.4 Differential Pair with MOS Loads.. ..... .. ... .... ..... . .... . .. . .. .. . . .. 124
`' ",,.
`4.5 Gilbert Cell .. . ..... ....... .. ... ...... . .. . ..... . ... .. ... . . ..... .. .. . . .
`11-Q
`
`5 Passive and Active Current Mirrors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
`5.1 Basic Current Mirrors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
`5.2 Cascode Current MiITors ..... .. . . .......... .... . ... ........ . .. . .... ... l 39
`5.3 Active CmTent :tv1in-ors .. . . .......................... . ... . .... .... .. . .. 145
`5.3.l Large-Signal Analysis . ....... . .. .... .. . .... .. ......... . ....... .
`149
`Small-Signal Analysis ........ .. . . .. .. .. . .... ... . . . . .. ... . .. ... .
`15 1
`5.3.3 Conm10n-Mode Properties . ..... . ..... . . ...... . ........ ... ...... 154
`
`6 Frequency Response of Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
`6.1 General Considera tions . . . .. ...... . ... . . . . ... . .. . ...... .. ....... ... . , . 166
`6.1. l Miller Effect . . . . . . .. . .. . . . . . .. . . .. . . . . . . .. .. . .. . . . . . . .. . . . . . .. . 166
`6.1.2 Association of Poles with Nodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
`6.2 Common-Source Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
`6.3 Source Followers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
`6.4 Common-Gate Stage ...... . . ...... . .. , . .. .. : . . . . . . . . . . . . . . . . . . . . . . . . . 183
`6.5 Cascade Stage . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
`6.6 Differential Pair . ... ... ... . . . ..... .... . .. .. . .. ....... . ................ 187
`Appendix A: Dual of Miller's Theorem .. · .. ... . . . .... . .... . . . .. .. . . .... .. .. 193
`
`IPR2019-00129
`Qualcomm 2030, p. 5
`
`

`

`Contents
`
`xvii
`
`7 Noise . . . . .. ....... ; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
`7.1 Statistical Characteristics of Noise.. .. .. . .. . .. . .. . . .... . .... . . . . ....... 201
`7. i. l Noise Spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
`7.1.2 Amplitude Distribution . ... . , , , , . .. , . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
`7 .1.3 CoD'elated and Uncon-elated Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
`7 .2 Types of Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
`7.2.1 Thermal Noise .. .. .... . . ... : . . . .. . . .. . . .. · .. . ....... .. ........ .. 209
`7.2.2 Flicker Noise . .. . . . . . .. . .. ... ...... . .... . . ... .. ....... . .... .. .. 21S
`7.3 F.epresentatic1n c,f Nc,ise 1n Circuits . . . . ..... . . . . . .. ... . .. . . .... . .... ... 218
`7.4 Noi se in Single-~tage Amplifiers... . ..... . ... . .... . . . ................. 224
`7.4. 1 Common-Source Stage ......... . . . ....... .. .. , .,., ... . ....... .. 225
`7.4.2 Common-Gate Stage ...... . . .. ... . .. ... . . . . .. . . . .. . ...... . .. . . . . 228
`7.4.3 Source Followers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1
`7 .4.4 Cascade Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
`7.5 Noise in Differential Pairs . .... . . . . . . . .. .. . ... . ... . . . ............ . .. . .. 233
`7.6 Noise Bandwidth . . . . .. . . ... .. .. .............. .. . . . . .. . .. . .. ... .... .. . 239
`
`8 Feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
`8.1 General Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
`8.1. 1 Properties of Feedback Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
`8.1.2 Types of P\rr1plifiers . . . . .. . . . . .... . _ . .. .. . .. . .. . , . . . . . . . . . . . . . . . . 254
`8.2 Feedback Topologies . ... ... ... ... . . .. . ... . . . .. . ... . . . .. . ... . ..... .. . . 258
`8.2.1 Voltage-Voltage Feedback. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8
`8.2.2 Current-Voltage Feedback. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
`8.2.3 Voltage-Current Feedback .. ........... .. . . . ' : . . . . . . . . . . . . . . . . . . . . 266
`8.2.4 Current-Current Feedback.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
`8.3 Effect of Loading .. .. ... . . ... . ..... . .. ... . . , . . . . . . . . . . . . . . . . . . . . . . . . . 270
`8.3.1 Tvvo-Port i'\Jetvlork iv1o<lels . . .. . .. . . , . . .. . .... . . .. . . .. . .. , , , . . . . . 270
`8.3.2 Loading in Voltage-Voltage Feedback . . . . ,.. . .. . ..... .... ..... . .. 272
`8.3.3 Loading in Current-Voltage Feedback.. . . . .. ... .. .. . ..... . .. . .. . . 275
`8.3.4 Loading in Volmge-Current Feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
`8.3.5 Loading in Current:Current Feedback . . . . .. ...... . . .. . . .. . . . .. . , . 28 i
`8.3.6 Summary of Loading Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
`8.4 Effect of Feedback on Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
`
`9 Operational Amplifiers: . .. _,. ......... , . . . . . .... .. .. ; . .. ... .. .. .. .. .. 291
`9 .1 General J; onsiderntions .. , : . . . . . . . . . .. . . . . . . .. . . . . . . . . . . . . . .. . . . . . . . . . . 29 l
`9.1. ( P~rformar,ce Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
`9.2 One-Stage Op Amps .... ;}·<· , .• ; . . • . .. : ... .. ... . .. . . . .. . ... : ........... . .. 296
`9.3 Two-Stage OpAmps . . .. . , ... . .. . ... . .. . ........... . . . .. ... .. . ... . ... 307
`· 9·.4 Gain Boosting . . .. . , . .. :; i , .. ,, . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . • . . . . . . . . 309
`9 .5 Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
`9.6 Common-Mode Feedback. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
`
`IPR2019-00129
`Qualcomm 2030, p. 6
`
`

`

`xviii
`
`Contents
`
`9.7 Input Range Limit(cid:143) tions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
`9.8 Slew Rate ............ . · . ............... . . . .. , . . . . . . . . . . . . . . . . . . . . . . . . 326
`9.9 Power Supply Rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334
`9.10 Noise in Op Amps ... . .... ... . . ... . ............. . . ........ ...... .... 336
`
`10 Stability and Frequency Compensation ... . ... ................... __ . . 345
`10.1 General Considerations . . .. . . ........ . . . . . ... . .. .. . .... . . . . .... .. .. . . 345
`10.2 Multipole Systems ... .. . , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
`10.3 Phase Margin ......... . . . . . . ... . .. . ...................... .... ...... . 351
`10.4 Frequency Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
`10.5 Compensation of Two-Stage Op Amps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
`l 0.5. l Slewing in Tw·o-Stage Op Amps... . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
`10.6 Other Compensation Techniques .. .. ...... . ...... . .... . ............... 369
`
`11 Bandgap References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377
`11. l General Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377
`11.2 Supply-Independent Biasing . . . .. ............ .. ..... .. .... ..... , . . . . . 377
`1 l.3 Temperature-Independent References..... . ... . .... . . . . ... . .. . ... .. .. . 381
`,.,,,,
`11.3.1 NP0-<1ti'1P -'T'r ""lt-:,n"'
`.JC .l
`..... O_" ... T .....
`11.3.2 Positive-TC Voltage . . .... . ....... .. ..... . ..... ... . . . ..... .. .. 382
`11.3.3 Bandgap Reference .......... . . ..... . ................ . ........ 384
`11.4 PTAT Current Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390
`11.5 Constant-Gm Biasing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392
`11 .6 Speed and Nnise lssues.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
`11.7 Case Study . .. ..... . .......... . ....... .. ...... . . . . . .. . .. .. ... . .. . . . . 397
`
`.o.
`
`•
`
`.&. . ._
`
`1 V.J l.UE,"-'
`
`•
`
`•
`
`•
`
`•
`
`•
`
`•
`
`•
`
`,
`
`•
`
`•
`
`•
`
`•
`
`o
`
`o
`
`•
`
`,
`
`•
`
`o
`
`o
`
`o
`
`,
`
`o
`
`o
`
`•
`
`o
`
`o
`
`•
`
`o
`
`•
`
`•
`
`•
`
`•
`
`o
`
`•
`
`o
`
`o
`
`,
`
`o
`
`o
`
`,
`
`o
`
`12 Introduction to Switched-Capacitor Circuits . . . . . . . . . . . . . . . . . . . . . . . 405
`12.1 General Considerations.... . . . ................. . . . .. . ......... . ...... 405
`12..2 Sampling SwiLches .... .. . ..... . .... . ................................ 410
`12.2.1 MOSFETS as Switches ........ ..... . ..... . . ... ..... .. ........ 410
`12.2.2 Speed Considerations . . ...... .. .. . . . . . ... ... . ................. 414
`12.2.3 Precision Considerations .......... .. ....... . . . . . .. . ........... 417
`12.2.4 Charge Injection Cancellation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421
`12.3 Switched-Capacitor Amplifiers... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423·
`12.3.1 Unity-GainSampler/Buffer .... ... ... .. . .. ....... .. . .. . ....... 424
`12.3.2 Noninverting Amplifier . .. .. .. . .. ... .. . . . .. .. .. . ...... . ....... 432
`12.3.3 Precision Multiply-by-Two Circuit .... . .. ............ . . .... .. . . 438
`12.4 Switched-Capacitor lntc.grator ..... .. .. .. : . , . . . . . . . . . . . . . . . . . . . . . . . . . . 439
`12.5 Switched-Capacitor Common-Mode Feedback . .. . ............ .. .. . .... 442
`
`13 Nonlinearity and Mismatch ..... . ....... , :'. . . . . . . . . . . . . . . . . . . . . . . . . 448
`. 13.1 Nonlinearity . . ............ . ......... . .. . • .............. . ....... . .... . 448
`13 .1.1 General Considerations . .... . , ,: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448
`
`IPR2019-00129
`Qualcomm 2030, p. 7
`
`

`

`Contents
`
`xix
`
`13. l .2 Nonlinearity of Differential Circuits ... .. . . .......... ... . .. ..... 452
`13.1.3 Effect of Negative Feedback on Nonlinearity .......... . ..... . ... 454
`13.1.4 Capacitor Nonlinearity ........... . ... .. . .. ... .. .. . . . .... ..... 457
`13.1.5 Linearization Techniques ... .. .... .. ... .... ........... . .. . .... 458
`13.2 Mismatch ............ ... . .. .... . . . . . ..... . ............. .. . ......... 463
`13 .2. 1 Offset Cancellation Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 71
`13.2.2 Reduction of Noise by Offset Cancellation . . .. ... . .. . .. .. .. . .... 476
`13.2.3 Alternative Definition of CMRR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478
`
`14 Oscillators . . _ . ........... , .. .. . .. ~ . . ~ ... ....... . . ... . . . ... ........ 482
`14.1 General Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482
`14.2 Ring Oscillators ...... . ..... ... . ......... .. . . .. ......... .... .. . . . .... 484
`14.3 LC Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495
`14.3 .1 Crossed-Coupled Oscillator .................. ·... ....... .......
`499
`14.3.2 Colpitts Oscillator ............. . .... . ....... . . . .. . ... . ...... .. 502
`14.3.3 One-Port Oscillators ....... ..... ... . . .. ...... .. .. . .. ... . ...... 505
`14.4 Voltage~Controlled Oscillators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510
`14.4.1 Tuning in Ring Oscillators .... . ..... .. ..... ... ......... ... .... 512
`14.4.2 Tuning in LC Oscillators .......... . ....... . . . . . . ....... . ...... 521
`14.5 Mathematical Model of VCOs ... ... .. .... .. . .. ... . ... ....... . .. ... ... 52:'i
`
`15 Phase-Locked Loops . .... .... ....... .... . .............. . ... . . ..... 532
`15,1 Simple PLL .... . . ... ..... . . .. .. .. . ... . . .. .. . . .. . ........ ..... . ..... 532
`15 .1. 1 Phase Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532
`15.1.2 Basic PLL Topology .. ·........................ . . . . .. .... .... . 533
`15.1.3 Dynamics of Simple PLL .... . ........ . . . . ............... ..... 542
`15,.2 Charge-Pump PLLs . ............ . . .. ... . ..... ..... .. , , . . . . . . . . . . . . . . 549
`15 .2.1 Problen1 of Lock .. t\cquisition ........... .. . , .. .. . ..... ....... .. 549
`15.2.2 Phase/Frequency Detector and Charge Pump ., .... .. . . , . ....... . 550
`15.2.3 Basic Charge-Pump PLL . . .. .. ... ........... ·,. .. .. . . . . . . . . . . . . 556
`15.3 l'~onideal Effects in PLLs. . . .. . .. . .. ... . . . . .... .. ........... .. .. . .... 562
`15.3.l PFD/CPNonidealities . .... . ......... ...... ...... · ... .. . .... . . . _ 562
`15.3.2 Jitter in PLLs ............ . . ... . ... . .. . .. . .... ..... . .... . ..... 567
`15.4 Delay-Locked Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569
`15.5 Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572
`15.5.1 Frequency Multiplication and Synthesis .. .. ......... ....... . ... 572
`15.5.2 Skew Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574
`15.5.3 Jitter Reduction .... ................................ .. .. ... . .. 576
`
`16 Short-Channel Effects and Device Models . ... . ... . .... . .... ...... . . 579
`16.1 Scaling Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579
`16.2 Short-Channel Effects ..................... . .. ... .'............... ... . 583
`
`IPR2019-00129
`Qualcomm 2030, p. 8
`
`

`

`.,,xx
`
`Contents
`
`16.2.1 Threshold Voltage Variation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583
`16.2.2 Mobility Degradation with Vertical Field.... . ... ... .. . ...... . . . 585
`i 6.2.3 Velocity Saturation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587
`16.2.4 Hot Carrier Effects... ... . .. ... . ... . .... .. . .. . .. . . ..... ....... 589
`16.2.5 Output Impedance Variation with Drain-Source Voltage ......... . 589
`16.3 MOS Device Models ......... .. ....... ................. . ............ 591
`16.3.1 Level 1 Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592
`16.3.2 Level 2 Model ......... .. .. .... .... . .- .... .. .......... ..... .. . 593
`16.3.3 Level 3 Model ... .. . ..... . .... . ..... ... . ..... ... ............ . <:()<:
`. ,:-,.)
`16.3.4 BSITvi Series . . . . . . . . .. .... ..... .... .. . ..... ... .. . . ... ...... .. 596
`16.3.5 Other Models ..... .. . .. .... . . .... . ..... . . . .. . . . ..... . .. .. .... 597
`16.3.6 Charge and Capacitance J\.1qdeling . .... . .... . .... .. ............ 598
`16.3.7 Temperature Dependence................ . ... . ........ .. ... . .. 599
`Process Corners ......... . .......... . ........... . ........... .. ...... . 599
`1 C. A
`iv . ...,.
`16.5 Analog Design in a Digital World ............. . .... . . ......... .. . . . . . . 600
`
`17 CMOS Processing Technology . ... . ................ ........... ..... 604
`17 .1 General Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604
`17 .2 Wafer Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605
`606
`17.3
`Photolithography ...... .. . ....... ... . ... .. ...... . ..... . .. . ... . ..... . .
`,~ 4
`Oxidation ........ . . . ... ....... . ... . ......... ... . .... . . .... .. .. ... . .
`608
`1 I .
`Ion Impl antation . .. . . . , ... _ ........ . . ........ . . .... . .. ... ... .. . ... . .
`17.5
`t:J)Q
`vvu
`17.6
`Deposition and Etching .......... . .. . .. .. ...... . . .... ... ... .. ..... .. .
`L1 1 Ull
`Device Fabrication .. .... . .... .. .................................... .
`17.7
`611
`17. 7 .1 Active Devices ............... .. ... . ............... . . ... .. .. . .
`611
`17.7.2 Passive Devices .... . ... . ............................ . . . . .. ... 616
`17.7.3 Interconnects....... . .................. ... . . . ..... .. . .. . . .. .. 624
`17.8 Latch-Up . . . ........................ . ................ . .. ... . ........ 627
`
`18 Layout and Packaging ........ .... . ..... .. . .... . . .. . ......... . .... 631
`18.1 General Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 631
`18.1.1 Design Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632
`18. l .2 Antenna Effect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634
`18.2 Analog Layout Techniques .. . .. . ..... .. .. .. . . ........... ..... ; ... . ... 635
`18.2.1 Multifinger Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635
`18.2.2 Symmetry ... . .. .......................... : . . . . . . . . . . . . . . . . . . 637
`18.2.3 Reference Di'.stribution.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642
`18.2.4 Passive Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 644
`18.2.5 lnterconnects .. .... .. .... .. ... . . ..... . ............ . .......... 653
`18.3 Substrate Coupling..... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 660
`
`Index . ............................... · .. . .... .. . .. . . . ..... .... .. . .. 677
`
`IPR2019-00129
`Qualcomm 2030, p. 9
`
`

`

`Sec. 6.5
`
`Cascode Stage
`
`185
`
`If a common-gate stage is driven by a relatively large source impedance, then the output
`impedance of the circuit drops at high frequencies . This effect is better described in the
`context of cascode circuits.
`
`6.5 Cascode Stage
`
`As explained in Chapter 3, cascoding proves beneficial in increasing the voltage · gain of
`amplifiers and the output impedance of current sources while providing shielding as well.
`The invention of the cascode (in the vacuum tuqe era), huweVef, was motivated by the
`need for high-frequency amplifiers with relatively high input impedance. Viewed as a cas(cid:173)
`cade of a corrtlTion-source stage and a con1n1on.-gate stage, a cascade circuit offers the
`speed of the latter-by suppressing the Miller effect- and the input impedance of the
`former.
`Let us consider the cascade shown in Fig. 6.25, first identifying all of the device ca(cid:173)
`pacitances. At node. A, Ccs1 is connected to ground and Ccm to node X. At node X,
`Cv 81 , Cs 82 , and Ccs2 are tied to ground, and at node Y, Cvs2, Cc02, and CL are con(cid:173)
`nected to ground. The Miller effect of Cc Dl i.s determined by the gain from A to X. As an
`approximation, we use the low-frequency value of this gain, which for low values of RD
`(or negligible channel-length modulation) is equal to -gm1/(gm2 + gmbz) . Thus, if M1 and
`M 2 have roughly equal dimensions, CcDl is multiplied by approximately 2 rather than the
`large voltage gain in a simple comn1on-source stage. We therefore say Miller effect is less
`significant in cascade amplifiers than in common-source stages. The pole associated with
`node A is estimated as
`
`Wp,A = Rs [ccs1 + (1 +
`gml
`gm2 + gmb2
`
`1
`
`) CGm].
`
`(6 .64)
`
`.J..
`
`M1 I Coe1 + Cse2
`-
`
`A
`
`ICGS1
`
`-
`
`Figur~6.25 High-frequency model of
`a cascade stage.
`
`IPR2019-00129
`Qualcomm 2030, p. 10
`
`

`

`186
`
`Chap. 6
`
`Frequency Response of A.mp!ifiers
`
`We can also attribute a pole to node X. The total capacitance at this node is roughly
`equal to 2CcDI + CDst + Csm + Ccs2, giving a pole
`f?m2 + gmb2
`2CcD! + CDBl + CsB2 + Ccs2
`Finally, the output node yields a third pole:
`
`Wp ,X =
`
`(6.65)
`
`r f.. f..f.. \
`
`\ V ,VV /
`
`The relative magnitudes of the three poles in a cascode circuit depend on the actmtl
`design parameters, but wp ,x is typically chosen to be farther from the origin than the other
`·
`A'
`' '
`. . r.1
`·
`·
`1
`·
`lf) h' · h
`~
`1wo. _ s exp1a1ned 1n l..._., ... 1apter .=- .... , L.:.1s c .. ;01ce p ... ays an 1mportant ro1c H1 tne staou1ty 01 op
`amps.
`But what if Ro in Fig. 6.25 is replaced by a current SO\.!rce so as to achieve a higher de
`gain? We know from Chapter 3 that the impedance seen at node X reaches high values if the
`load impedance at the dl'ain of M 2 is large. For example, Eq. (3.11 0) predicts that the pole
`cit node X · may be quite lo'wer than (g1112 + gmb2 ) / C x if RD itseif is the output impedance
`of a PMOS cascode current source. Interestingly, however, the overall transfer function is
`negligibly affected by this phenoiih::-.IJun. This can be better seen by an example.
`
`1
`
`•
`
`1
`
`' . , . .
`
`Consider the cascode stage shown in Fig. 6.26(a), where the load resistor is replaced by an ideal
`
`If i7
`
`M2J_ •
`I
`·-
`-· I
`l '02
`vb ---i~
`XHI I
`I
`Rs
`r-AM--it'.M1 ~ Cv
`- I . l "
`I -
`If ~+
`'
`--
`~in V
`-::-
`J. -
`-
`
`I
`• o V~ .. +
`vu,
`=6
`.,- Cy
`J_
`
`(a)
`
`(b)
`
`Figure 6.26 Simplified model of a cascode stage.
`
`cuJTent source. Negiecting the capacitances associated with Mi, represen1ing V111 and M1 by a Norton
`equivalent as in Fig. 6.26(b), and assuming y = 0, compute the transfer function.
`Solution
`fin, we have Vx = - ·(V0 urCys + f in)/(Cxs),
`Since the current through Cx is equal t? -V0 urCrs -
`and the small-signal drain current of M2 is -g,,)2(- V0 u1Cys -
`fin )/(Cxs). The current through ro2
`
`IPR2019-00129
`Qualcomm 2030, p. 11
`
`

`

`Sec. 6.6
`
`Differential Pair
`
`187
`
`is then equal to -V0 utCys - gm2CVaiaCys + IinJ/(Cxs) . Noting that Vx plus the voltage drop across
`ro2 is equal to Vaut , we write
`
`]
`/"
`' V
`., _L I ) gm2
`,...,
`1,,7
`-ro2 L' ~~outLY.:,
`in - - -r out1...,yS
`,
`Cxs
`
`-
`
`\ 1
`I /
`/"
`(TT
`•1;u11...,YJ,
`in ; - - =
`Cxs
`
`n
`
`V:
`ow-
`
`(6.67)
`
`That is,
`
`Vaut
`
`-
`
`'
`
`, -
`
`,._,.,_,
`
`,
`
`(6.68)
`
`(6.69)
`
`(6.70)
`
`C
`1 -i-- (1 -+- o_~,,rnl"I )~ -t- rv r 1y·,S
`' - .L
`1 Qll~s.,, • V£..,' r
`~x
`\:vhicb, for gm2ro2 >> 1 and g7,,.,,2ro2Cy/Cx >> 1 (i.e., Cy > Cx)~ reduces to
`
`and hence
`
`Vaut
`ft.~
`
`l
`gm2
`:::::: - r:vs Cy
`_
`-C gm2 + Cys
`· "
`,x
`
`Vaut
`Vin
`
`l
`gmlgm2
`CyCxs gm2/Cx + s
`
`The n1agnitude of the pole at node X is still given by gm2/ C x . This is because at high frequencies
`(as Vile approach this pole) Cy shunts the output node~ dropping the gain and suppressing the ~1i1ler
`effect of r02 .
`
`---------------------------·''""""""..,_""""'""""'"""""""""""·=
`
`If a cascode structure is used as a current source, then ihe variation of its output impedance
`with frequency is of interest. Neglecting CGDl and Cy in Fig. 6.26(a), we have
`
`Zau t = (1 + gm2r02)Zx + r02,
`
`(oc ,...,1 \
`
`. I l)
`
`where Zx = ro1 ! l(Cxs')·t: Thus, Zaut contains a pole at (ro1 Cx)- 1 and falls at frequencies
`higher than this value:
`
`6.6 Differential Pair
`
`The versatility of differential pairs and their extensive use in analog systems motivate us to
`characterize their frequency response for both differential and common-mode signals.
`Consider the simple differential pair shown in Fig. 6.27(a), with the differential half cir(cid:173)
`cuit and the common-mode equivalent circuit depicted in Figs. 6.27(b) and (c), respectively.
`For differential signals, the response is identical to that of a common-source stage, exhibit(cid:173)
`ing Miller multiplication of Ccv- Note that since+ Vi 112/2 and -V; 112/2 are muitiplied by
`the same transfer function, the number of poles in Vaur / Vin is equal to that of each path
`(rather than the sum of the number of the poles in the two paths).
`For common-mode sjgnals, thy, total capacitance at node P. in Fig., 6.27 ( c) determines ihe
`high-frequency gain. Arising irom CGv3 , Cv 8 3·, Css 1, and Cs 8d: this capacitance can be
`
`IPR2019-00129
`Qualcomm 2030, p. 12
`
`