Jan-05-2006 14:57
`
`From-HOGAN & HARTSON
`
`RECEIVED
`CENTRAL FAX CENTER
`
`JAN O 5 2006
`
`T-910
`
`P.001/009
`
`F-082
`
`PTOISll/2~ (OIII03)
`Approved fDr USO IIU'Qwgh o'l'/3112008. 0MB D85\.0031
`Pa1t1n1 ;:uic Tr.,r.x,m11J!( Olllce: U 5 . DEPARTMENT OF COMMERCE
`d "'o callgi;!ion QI Information ~nlaa• ~ di:. 1.a .. , va~d. OM!l can11C>1 numbor.
`Certificate of Transmission under 37 CFR 1.8
`
`Serial No. 10/869,200
`Application of: Daniel Poznanovic, David E. Caliga, and Jeffrey Hammes
`Filed: June 16, 2004
`Art Unit: 2186
`Examiner: Thomas, Shane M.
`Attorney Docket No. SRC028
`For: SYSTEM AND METHOD OF ENHANCING EFFICIENCY AND UTILIZATION
`OF MEMORY BANDWIDTH IN RECONFIGURABLE HARDWARE
`Confirmation No.: 5929
`Customer No.: 25235
`
`I hereby certify that this correspondence is being facsimile transmitted to the United
`States Patent and Trademark Office
`
`1. Amendment in response to the Office Action dated October 19, 2005.
`
`on
`
`9
`No. of Pages
`(incl. Covet$heet)
`
`to centralized fax number: 571-273-8300
`
`Julje Lange
`Typed or printed name of person signing Certificate
`
`Note: Each paper must have its own certificate of transmission, or its certificate must
`identify each submitted paper.
`
`Client Reference No. 80404.0033.001
`
`Fax No. 719-448~5922
`
`\\\CS • 77~8? \/'I
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`Petitioners Amazon
`Ex. 1010, p. 225 of 399
`
`

`

`Jan-05-2006 14:57
`
`From-HOGAN l HARTSON
`
`t
`
`RECEIVED
`CENTRAL FAX CENTER
`JAN O 5 2006
`
`T-910
`
`P.002/009
`
`F-082
`
`Client Matter No. 80404.0033.001
`Via Facsimile
`
`IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`Confirmation No.: 5929
`Customer No.: 25235
`
`Serial No. 10/869,200
`
`Application of: Daniel Poznanovic, David E. Caliga,
`and Jeffrey Hammes
`Filed: June 16, 2004
`Art Unit: 2186
`Examiner: Thomas, Shane M.
`Attorney Docket No. SRC028
`For: SYSTEM AND METHOD OF ENHANCING
`EFFICIENCY AND UTILIZATION OF MEMORY
`BANDWIDTH IN RECONFIGURABLE HARDWARE
`
`AMENDMENT
`
`MAIL STOP AMENDMENT
`Commissioner for Patents
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`Sir:
`
`In response to the office communication mailed October 19, 2005, please
`amend the above-identified application as follows:
`Amendments to the Claims are reflected in the listing of claims which
`begins on page 2 of this paper.
`Remarks/Arguments begin on page 6 of this paper.
`
`\IICS • 'M'2117 v1
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`Petitioners Amazon
`Ex. 1010, p. 226 of 399
`
`

`

`Jan·05-Z006 14:57
`
`From-HOGAN & HARTSON
`
`+
`
`r-e10 P.003/oos
`
`F-oez
`
`Serial No. 10/869,200
`Reply to Office Action of October 19, 2005
`
`Amendments to the Claims:
`This listing of claims will replace all prior versions and listings of claims in the
`application:
`
`Listing of Claims:
`
`1.
`
`(Previously Presented) A reconfigurable processor that instantiates
`
`an algorithm as hardware comprising:
`
`a first memory having a first characteristic memory bandwidth and/or
`memory utilization; and
`a data prefetch unit coupled to the first memory, wherein the data prefetch
`
`unit retrieves data from a second memory of second characteristic memory
`bandwidth and/or memory utilization and place the retrieved data in the first
`memory and wherein at least the first memory and data prefetch unit are
`configured by a program.
`
`2.
`
`3.
`
`(Cancelled)
`
`{Cancelled)
`
`(Previously Presented) The reconfigurable processor of claim 1,
`4.
`wherein the data prefetch unit is coupled to a memory controller that controls the
`
`transfer of the data between the second memory and the data prefetch unit.
`
`(Previously Presented) The reconfigurable processor of claim 1,
`5.
`wherein the data prefetch unit receives processed data from on-processor
`memory and writes the processed data to an external off-processor memory.
`
`\\\CS • 772117 Yl
`
`2
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`Petitioners Amazon
`Ex. 1010, p. 227 of 399
`
`

`

`Jan-05-2006 14:57
`
`From-HOGAN & HARTSON
`
`+
`
`T-910 P.004/009
`
`F-08Z
`
`Serial No. 10/869,200
`Reply to Office Action of October 19, 2005
`
`(Original) The reconfigurable processor of claim 1, wherein the
`6.
`data prefetch unit comprises at least one register from the reconfigurable
`processor.
`
`(Original) The reconfigurable processor of claim 1, wherein the
`7.
`data prefetch unit is disassembled when another program is executed on the
`reconfigurable processor.
`
`(Previously Presented) The reconfigurable processor of claim 1
`8.
`wherein said second memory comprises a processor memory and said data
`prefetch unit is operative to retrieve data from the processor memory.
`
`(Original) The reconfigurable processor of claim 8 wherein said
`9.
`processor memory is a microprocessor memory.
`
`(Original) The reconfigurable processor of claim 8 wherein said
`10.
`processor memory is a reconfigurable processor memory.
`
`(Previously Presented)
`
`A reconfigurable hardware system,
`
`11.
`comprising:
`a common memory; and
`one or more reconfigurable processors that can instantiate an algorithm
`as hardware coupled to the common memory, wherein at least one of the
`reconfigurable processors includes a data prefetch unit to read and write data
`between the data prefetch unit and the common memory, and wherein the data
`prefetch unit is configured by a program executed on the system.
`
`The reconfigurable hardware system of claim 11,
`(Original)
`12.
`comprising a memory controller coupled to the common memory and the data
`prefetch unit.
`
`\\\CS • 77287 v1
`
`3
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`Petitioners Amazon
`Ex. 1010, p. 228 of 399
`
`

`

`Jan-05-2006 14:58
`
`From-HOGAN & HARTSON
`
`+
`
`T-910 P.005/009
`
`F-082
`
`Serial No. 10/869,200
`Reply to Office Action of October 19. 2005
`
`13.
`
`(Cancelled)
`
`14.
`
`(Cancelled)
`
`15.
`
`{Previously Presented) The reconfigurable hardware system of
`
`claim 11, wherein the at least one of the reconfigurable processors also includes
`a computational unit coupled to a data access unit.
`
`(Original)
`16.
`The reconfigurable hardware system of claim 15,
`wherein the computational unit is supplied the data by the data access unit
`
`17.
`
`(Previously Presented) A method of transferring data comprising:
`transferring data between a memory and a data · prefetch unit in a
`
`reconfigurable processor; and
`
`transferring the data between a computational unit and a data access unit,
`
`wherein the computational unit and the data access unit, and the data prefetch
`unit are configured by a program.
`
`(Original) The method of claim 17, wherein the data is written to
`18.
`the memory, said method comprising:
`
`transferring the data from the computational unit to the data access unit;
`
`and
`
`writing the data to the memory from the data prefetch unit.
`
`(Previously Presented) The method of claim 17, wherein the data
`19.
`is read from the memory, said method comprising:
`
`transferring the data from the memory to the data prefetch unit; and
`
`reading the data directly from the data prefetch unit to the computational
`unit through the data access unit.
`
`\\\C~ - 77287 v1
`
`4
`
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`
`Petitioners Amazon
`Ex. 1010, p. 229 of 399
`
`

`

`Jan-05-2006 14:58
`
`From-HOGAN & HARTSON
`
`+
`
`T-910 P.006/009
`
`F-082
`
`Serial No. 10/869,200
`Reply to Office Action of October 19, 2005
`
`20.
`
`(Original) The method of claim 19, wherein all the data transferred
`
`from the memory to the data prefetch unit is processed by the computational
`unit.
`
`(Original) The method of claim 19, wherein the data is selected by
`21.
`the data prefetch unit based on an explicit request from the computational unit.
`
`22.
`(Original) The method of claim 17, wherein the data transferred
`between the memory and the data prefetch unit is not a complete cache line.
`
`(Original) The method of claim 17, wherein a memory controller
`23.
`coupled to the memory and the data prefetch unit, controls the transfer of the
`data between the memory and the data prefetch unit.
`
`24.
`
`(Cancelled)
`
`111C$ • 772,87 V1
`
`5
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`Petitioners Amazon
`Ex. 1010, p. 230 of 399
`
`

`

`Jan-05-2006 14:58
`
`From-HOGAN & HARTSON
`
`+
`
`T-910 P.007/009
`
`F-OBZ
`
`Serial No. 10/869,200
`Reply to Office Action of October 19, 2005
`
`REMARKS/ARGUMENTS
`
`Claims 1, 4-12, and 15-24 were presented for examination and are pending
`in this application. In an Official Office Action dated October 19, 2005, claims 1, 4-
`12, and 15-24 were rejected. Claim 24 is canceled without prejudice and no new
`
`claims are presently added. Claims 1, 4-12, and 15-23 remain pending. The
`
`Applicants thank the Examiner for his consideration and address the Examiner's
`comments concerning the claims pending in this application below.
`
`Rejection of the Claims under 35 U.S.C. §102(e)
`
`Claims 1, 3, 4, 7-10, and 12-18 were rejected under 35 U.S.C. §102(e) as
`being anticipated by U.S. Patent Application Publication No. 2003/0084244
`
`("Paulraj"). Applicants respectfully traverse these rejections in light of the following
`
`remarks.
`
`MPEP §2131 provides:
`
`"A claim is anticipated only if each and every element as set forth in
`the claim is found, either expressly or inherently described, in a
`single prior art reference." Verdega/1 Bros. v. Union Oil Co. of
`California, 814 F.2d 628, 631, 2 U.S.P.Q.2d 1051, 1053 (Fed.
`
`''The identical invention must be shown in as complete
`Cir.1987).
`detail as contained in the claim." Richardson v. Suzuki Motor Co.,
`868 F.2d 1226, 1236, 9 U.S.P.Q.2d 1913, 1920 (Fed. Cir. 1989).
`
`Paulraj fails to disclose each and every limitation recited in the claims. The
`Examiner reasons that Paulraj discloses a system having a program that
`reconfigures computational units, data access units, and pre-fetch units. The
`Applicants disagree.
`The Examiner's logic in making the above assertion Is faulty. Assume for
`argument sake (as does the Examiner) that the computational unit Is the element of
`the Paulraj system that executes and collects performance data regarding an
`
`\\\CS - 77267 t/1
`
`6
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`Petitioners Amazon
`Ex. 1010, p. 231 of 399
`
`

`

`Jan-05-2006 14:58
`
`Fram-HOGAN & HARTSON
`
`+
`
`T-910 P.008/009
`
`F-082
`
`Serial No. 10/869,200
`Reply to Office Action of October 19, 2005
`
`application to determine an optimal memory configuration. The program operating
`on the Paulraj system depicted In Figure 5 of Paulraj "configures" the collection
`process so as to ascertain information about a specific application. In this sense
`
`the Examiner uses the term configure to state that the program executed by the
`
`Paulraj system modifies, directs, and/or controls the collection means (the
`
`computational unit) to properly assess the target application so that the memory
`
`can be optimally configured.
`The Examiner then extends this argument to the data access units and pre(cid:173)
`fetch units. While such an extension Is perhaps conceivable today given the
`present invention, it is not, nonetheless, disclosed by PaulraJ. Nor Is it reasonable
`
`to conclude that such an extension would be apparent to one skilled in the art at the
`
`time of the Applicants' invention.
`
`As the Examiner points out, Paulraj discloses creating a "configuration vector
`
`containing data relating to the optimal configuration to the necessary instruction for
`programming the programmable memory module." Paulraj [0024]. Paulraj also
`discloses a reconfiguration module that uses the vector to configure the
`
`programmable memory module. Once the Paulraj system collects Information
`
`about the target application and creates the configuration vector for optimal
`
`memory module configuration, "the configuration vector is then retrieved (step 212),
`
`used to program the FPGA module {step 214), and the application is executed with
`
`the optimal memory configuration for that application (step 216)." Paulraj [0026].
`
`The ''programu that the Examiner considers to configure the computational
`
`unit does not, according to Paulraj, uconfigure" the data access unit nor the pre(cid:173)
`
`fetch unit. The Examiner restates that he considers the reconfiguration unit of
`
`Paulraj to be a data pre-fetch unit. The Examiner also correctly states that Paulraj
`discloses that the reconfiguration unit retrieves the configuration vector and sets up
`
`a programmable memory module. It is conceivable to argue that the "program" of
`Figure 5 of Paulraj configures the configuration vector to configure the
`
`\\\C5 • T12fr7 Y1
`
`7
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`
`Petitioners Amazon
`Ex. 1010, p. 232 of 399
`
`

`

`.
`• ..
`. ..
`Jan-05-2006 14:58
`
`From-HOGAN & HARTSON
`
`+
`
`T-910 P.009/009
`
`F-OSZ
`
`Serial No. 10/869,200
`Reply to Office Action of October 19, 2005
`
`programmable memory module but once the vector Is configured Paulraj discloses
`
`that the vector is simply retrieved and used by the reconfiguration unit to program
`the FPGA module. No configuration by the ''program" of the reconfiguration module
`is even implied let alone disclosed. The Examiner expands Paulraj beyond the four
`corners of the document and what is literally presented so as to craft an argument
`for anticipation. Such a creation is not contemplated nor allowable under 35 U.S.C.
`§ 102(e). As the rules governing anticipation are clear, the Applicants submit that
`
`Paulraj does not disclose a pre-fetch unit and a memory unit that is configured by a
`program as is recited in claim 1.
`For at least the same aforementioned reasons, claims 11 and 17 are not
`anticipated by Paulraj. As Claims 4-10, 12, 15, 16, and 18-23 depend from claims
`1, 11, or 17 and carry with them the limitations recited in those independent claims,
`claims 4-10, 12, 15, 16, and 18-23 are also not anticipated by Paulraj. The
`
`Applicants respectfully request withdrawal of the rejections and reconsideration of
`the claims.
`
`In view of all of the above, the claims are now believed to be allowable and
`the case in condition for allowance which action is respectfully requested. Should
`the Examiner be of the opinion that a telephone conference would expedite the
`prosecution of this case, the Examiner is requested to contact Applicants' attorney
`at the telephone number listed below.
`No fee ls believed due for this submittal. However, any fee deficiency
`
`associated with this submittal may be charged to Deposit Account No. 50-1123.
`
`7
`
`~ed{~
`
`Michaeic.Martensen, No. 46,901
`Hogan & Hartson LU'
`One Tabor Center
`1200 17th Street, Suite 1500
`Denver, Colorado 80202
`(719} 448-5910 Tel
`(303) 899-7333 Fax
`
`IIICS • 77287 v1
`
`8
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`
`Petitioners Amazon
`Ex. 1010, p. 233 of 399
`
`

`

`PATENT APPLICATION FEE DETERMINATION RECORD
`Effective October 1. 2003
`
`CLAIMS AS FILED • PART I
`ICotumn 11
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`
`Petitioners Amazon
`Ex. 1010, p. 234 of 399
`
`

`

`UNJTED STATES PATENT AND TRADEMARK OFFICE
`
`UNITED STATES DEPARTMENT OF COMMERCE
`United States Patent and Trademark Office
`Address: COMMISSIONER FOR PATENTS
`P.O. Box 1450
`Alexandria. Virginia 22313·1450
`www.uspto.gov
`
`APPLICATION NO.
`
`FILING DATE
`
`FIRST NAMED INVENTOR
`
`ATTORNEY DOCKET NO.
`
`CONFIRMATION NO.
`
`10/869.200
`
`06/16/2004
`
`Daniel Poznanovic
`
`SRC028
`
`5929
`
`OJ/23/2006
`7590
`25235
`HOGAN & HARTSON LLP
`ONE TABOR CENTER, SUITE 1500
`1200 SEVENTEENTH ST
`DENVER, CO 80202
`
`EXAMINER
`
`THOMAS, SHANE M
`
`ART UNIT
`
`PAPER NUMBER
`
`2186
`
`DATE MAILED: 03/23/2006
`
`Please find below and/or attached an Office communication concerning this application or proceeding.
`
`PT0-90C (Rev. 10/03)
`
`Petitioners Amazon
`Ex. 1010, p. 235 of 399
`
`

`

`Office Action Summary
`
`Application No.
`
`Applicant(s)
`
`10/869,200
`
`Examiner
`
`POZNANOVIC ET Al.
`
`Art Unit
`
`Shane M. Thomas
`2186
`-- The MAILING DA TE of this communication appears on the cover sheet with the correspondence address -(cid:173)
`Period for Reply
`A SHORTENED STATUTORY PERIOD FOR REPLY IS SET TO EXPIRE .J. MONTH(S) OR THIRTY (30) DAYS,
`WHICHEVER IS LONGER, FROM THE MAILING DATE OF THIS COMMUNICATION.
`Extensions of time may be available under the provisions of 37 CFR 1. 136(a). In no event, however, may a reply be timely filed
`after SIX (6) MONTHS from the mailing date of this communication.
`If NO period for reply is specified above. the maximum statutory period will apply and will expire SIX (6) MONTHS from the mailing date of this communication .
`Failure to reply within the set or extended period for reply will. by statute, cause the application to become ABANDONED (35 U.S.C. § 133).
`Any reply received by the Office later than three months after the mailing date of this communication, even if timely filed , may reduce any
`earned patent term adjustment. See 37 CFR 1.704(b).
`
`Status
`1 )0 Responsive to communication(s) filed on 05 January 2006.
`2a)[8] This action is FINAL.
`2b)0 This action is non-final.
`3)0 Since this application is in condition for allowance except for formal matters, prosecution as to the merits is
`closed in accordance with the practice under Ex parte Quayle, 1935 C.D. 11,453 O.G. 213.
`
`Disposition of Claims
`
`4)[8] Claim(s) 1,4-12 and 15-23 is/are pending in the application .
`4a) Of the above claim(s) __ is/are withdrawn from consideration .
`5)0 Claim(s) __ is/are allowed.
`6)[8] Claim(s) 1,4-12 and 15-23 is/are rejected.
`7)0 Claim(s) __ is/are objected to.
`8)0 Claim(s) __ are subject to restriction and/or election requirement.
`
`Application Papers
`
`9)0 The specification is objected to by the Examiner.
`10)0 The drawing(s) filed on __ is/are: a)O accepted or b)O objected to by the Examiner.
`Applicant may not request that any objection to the drawing(s) be held in abeyance. See 37 CFR 1.85(a).
`Replacement drawing sheet(s) including the correction is required if the drawing(s) is objected to. See 37 CFR 1.121 (d) .
`11 )0 The oath or declaration is objected to by the Examiner. Note the attached Office Action or form PT0-152.
`
`Priority under 35 U.S.C. § 119
`
`12)0 Acknowledgment is made of a claim for foreign priority under 35 U.S.C. § 119(a)-(d) or (f).
`a)O All b)O Some .. c)O None of:
`1. 0
`· Certified copies of the priority documents have been received.
`2.0 Certified copies of the priority documents have been received in Application No. __ .
`3.0 Copies of the certified copies of the priority documents have been received in this National Stage
`application from the International Bureau (PCT Rule 17.2(a)).
`*Seethe attached detailed Office action for a list of the certified copies not received.
`
`Attachment(s)
`1) [8J Notice of References Cited (PT0-892)
`2) 0 Notice of Draftsperson's Patent Drawing Review (PT0-948)
`3) 0 Information Disclosure Statement(s) (PT0-1449 or PTO/SB/08)
`Paper No(s)/Mail Date __ .
`
`4) 0 Interview Summary (PT0-413)
`Paper No(s)/Mail Date. __ .
`5) 0 Notice of Informal Patent Application (PT0-152)
`6) 0 Other: __ .
`
`U.S. Patent and Trademark Office
`PTOL-326 (Rev. 7-05)
`
`Office Action Summary
`
`Part of Paper No./Mail Date 03162006
`
`Petitioners Amazon
`Ex. 1010, p. 236 of 399
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`

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`Application/Control Number: 10/869 ,200
`Art Unit: 2186
`
`Page 2
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`DETAILED ACTION
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`This Office action is responsive to the response filed 1/5/2006. Claims 1,4-12, and 15-23
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`remain pending; claims 2,3,13,14, and 24 have been canceled.
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`Response to Arguments
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`Applicant's arguments filed 1/5/2006 have been fully considered but they are not
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`persuasive for the reasons stated herein.
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`Applicant does not argue the rejections of claims 1-10 and appears to be arguing the
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`rejection of claim 17 (page 7, ~2, of the response):
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`"The Examiner then extends this argument to the data access units and prefetch units"
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`Examiner notes that only one --data access unit-- and one --prefetch unit-- are claimed.
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`"While such an extension is perhaps conceivable today given the present invention, it is
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`not, nonetheless, disclosed by Paulraj. Nor is it reasonable to conclude that such an extension
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`would be apparent to one skilled in the art at the time of Applicant's invention,"
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`The Examiner respectfully traverses and states that the Applicant has mischaracterized
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`the prior rejection made by the Examiner with regard to claim 17. The following is a more
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`detailed explanation of the Examiner's previous interpretation of the claims that clearly shows
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`that each limitation of Applicant's clam 17 is anticipated by Paulraj or necessarily inherent,
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`based on the teachings of Paulraj taken by one having ordinary skill in the art.
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`While the Examiner does state on page 5, lines 4-8, ofthe prior Office action (filed
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`10/19/2005) that the same program that "modifies, directs, and/or controls the collection means
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`Petitioners Amazon
`Ex. 1010, p. 237 of 399
`
`

`

`Application/Control Number: 10/869,200
`Art Unit: 2186
`
`Page 3
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`(i.e. the computation unit) to properly assess the target application so that the memory can be
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`optimally configured" is extended to the data access unit and the data prefetch unit, the Examiner
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`was merely stating that different portions of the --program-- (entire figure 5 that is running on
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`the system of Paul raj in order to perform the cache optimization when a new application is
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`started) are responsible for --configuring-- the computational unit, the data access unit, and the
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`data prefetch unit, so as to perform their unique procedures in order to optimize the
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`reconfigurable cache.
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`The Examiner is considering the entirety of figure 5 of Paulraj to be an "access program."
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`In other words, because Applicant does not specifically claim any limitations on specifics of the
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`"program" [that does the configuring], the Examiner is broadly interpreting the term "program"
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`to simply be a "collection of processes working together to accomplish a common task" - which
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`is coherent with the IEEE definition of a "program" (refer to cited IEEE 100, page 874). Further,
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`as it well known in the art, for a computer system to implement a method, computer instructions
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`(either low-level or high-level) must be executed in order to perform the execution of the steps of
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`the method. The --program--, as related to Paulraj figure 5, is being considered by the Examiner
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`to be the steps required to implement a cache configured exclusively for a specific application,
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`such as will be shown below.
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`The first portion ( which is being considered by the Examiner to be performed by the
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`--prefetch unit--) of the program of figure 5 of Paulraj (steps START through 200) determines
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`(1) whether the operation of the program of figure 5 should run (i.e. when a new application is to
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`be run that requires cache optimization - an inherent step since it can be argued that only if a new
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`application is to be executed by the system of Paul raj will the operation of the program of figure
`
`Petitioners Amazon
`Ex. 1010, p. 238 of 399
`
`

`

`Application/Control Number: 10/869,200
`Art Unit: 2186
`
`Page 4
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`5 be executed. Ref er to 121 of Paulraj which states that a wide range of applications can be
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`used" and that the "cache architecture ... reconfigure itself for optimal performance"; therefore,
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`in order to be reconfigured, a first configuration must be present and if a change to that
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`configuration is to occur, it is necessarily inherent that a new application is to be run to trigger
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`the reconfiguration. Secondly, the first portion (pref etch unit) of the program of figure 5 of
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`Paulraj (steps START through 200) determines (2) whether a vector is known for a given
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`application that is to be executed on the system of Paulraj. It can be seen and argued herein, that
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`in order to determine whether or not a given vector is known for a specific application, the first
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`portion must perform a lookup or access of the memory comprising the vectors; therefore, it is
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`necessarily inherent that the program configure the data prefetch unit to access and index the
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`vector memory in order to ascertain whether or not the program should perform the steps of
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`collecting and analyzing application data (steps 202-210 of figure 5). Without the program's
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`configuration, the data prefetch unit would not know which application to search for when
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`indexing the memory for the corresponding application vector. In other words, the. program
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`portion that is to perform the lookup of the vector must configure the data prefetch unit
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`accordingly by sending the unique application identification and instructing the data prefetch unit
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`to perform the search of the vector memory.
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`Further, if the memory vector is known (right path of step 200) the data prefetch unit is
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`configured by the program as shown in figure 5, to retrieve the vector by accessing and reading
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`the vector memory and subsequently, relaying the vector so the program can configure the FPGA
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`to the vector's cache specification. Yet further, it can be seen in figure 5, that the data prefetch
`
`Petitioners Amazon
`Ex. 1010, p. 239 of 399
`
`

`

`Application/Control Number: 10/869,200
`Art Unit: 2186
`
`Page 5
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`unit is configured to not read from the vector memory if a determination is made that the
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`application does not have a corresponding vector entry (left path of step 200).
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`Simply put, the data prefetch unit must be configured to (1) be able to access the vector
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`memory when a new application is to be executed and (2) to respond with either a vector or a
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`"vector not found" indication so that the program may either program the FPGA module (step
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`214) or begin the process of collecting performance data (step 204), respectively.
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`Similarly, the --data access unit-- (the unit that takes the vector data and accesses the
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`vector memory to store the vector in an available location within the memory) is configured by
`
`the program of figure 5 to receive the vector created by the computational unit (in step 208) and
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`then store the vector (step 210). It can be seen that the data acct!ss unit requires configuration,
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`since if a vector is not created, a store by the data access unit would not have been required.
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`Only when a new vector is created is the data access unit configured to execute a storage/write
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`routine.
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`Finally, the "program" that is being executed by the --computational unit-- of Paulraj
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`(steps 202-208) is shown as being only a portion of the program of figure 5 (i.e. the program that
`
`performs the configurations based on the decision block 200). The program of Paulraj
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`configures the prefetch unit to check the vector data for a particulat application to be executed
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`and retrieve the vector· if available. If not available, the program configures the computational
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`unit to collect and analyze application data and configures the data access unit to store the vector
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`in the memory.
`
`As argued herein, the prior art of Paulraj anticipates the claims as presented by the
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`Applicant and interpreted by the Examiner. The Examiner does not "extend Paulraj beyond the
`
`Petitioners Amazon
`Ex. 1010, p. 240 of 399
`
`

`

`Application/Control Number: 10/869,200
`Art Unit: 2186
`
`Page 6
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`four corners of the document" since each limitation, as argued by the Applicant in the response
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`filed 1/5/2006, is shown as being met in relation to figure 5 of Paulraj. Each of the
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`computational unit, data access unit, and the prefetch unit (as defined by the Examiner in relation
`
`to Paulraj) are configured by the program of the steps of figure 5 in order to correctly implement
`
`the cache reconfiguration system of Paulraj. Without program configuration,
`
`Claim Rejections -35 USC§ 102
`
`The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the
`
`basis for the rejections under this section made in this Office action:
`
`A person shall be entitled to a patent unless -
`
`( e) the invention was described in (I) an application for patent, published under section I 22(b ), by another filed
`in the United States before the invention by the applicant for patent or (2) a patent granted on an application for
`patent by another filed in the United States before the invention by the applicant for patent, except that an
`international application filed under the treaty defined in section 351 (a) shall have the effects for purposes of this
`subsection of an application filed in the United States only if the international application designated the United
`States and was published under Article 21 (2) of such treaty in the English language.
`
`Claims 1,4-12, and 15-23, are rejected under 35 U.S.C. 102(e) as being anticipated by
`
`Paulraj (U.S. Patent Application Publication No. 2003/0084244).
`
`As per claim 1, Paulraj shows a reconfigurable processor in figure 6 and a first memory
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`(L 1) having a first characteristc memory utilization and a second memory (L2) having a second
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`characteristic memory utilization. It is well known in the art that L 1 caches have a higher
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`utilziation rate than a lower-level cache such as L2. Paulraj teaches in ,1 that upon a command
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`from a processor, a search for the requested data is begines with the highest level cache (L 1) and
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`[if a miss occurs] continues next to the next level cache (L2). Thus it is inherent that the memory
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`utilziation characteristc of the L 1 cache of the reconfigurable processor 110 in figure 6 is greater
`
`Petitioners Amazon
`Ex. 1010, p. 241 of 399
`
`

`

`Application/Control Number: 10/869 ,200
`Art Unit: 2186
`
`Page 7
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`than the memory utilziation characteristic of the L2 cache (and likewise for the L3 cache) as the
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`L2 cache would only be utilzied when a miss to the Ll cache occurred. In other words, the
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`reconfigurable processor always utilizes the LI cache for a memory access and the only utilzies
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`the L2 cache for requested data when the data is not in the LI cache. Therefore, the cache
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`utilziation characteristics of the --first memory-- and the --second memory-- are different.
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`Paulraj further teaches a functional unit 102 that executes applications using the
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`memories LI and L2 (paragraph 9). As is known in the art, a cache memory controller is often
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`used to access and move data between a memory hierarchy. The Examiner is considering a data
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`pref etch unit to be the logic assocatied with the moving, and only the moving, of data between
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`the first and second memories (L 1 and L2) since Paulraj shows a c