Case 2:18-cv-00321-JLR Document 131-19 Filed 11/05/18 Page 2 of 20
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`THE HONORABLE JAMES L. ROBART
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`IN THE UNITED STATES DISTRICT COURT
`FOR THE WESTERN DISTRICT OF WASHINGTON
`AT SEATTLE
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`SRC LABS, LLC & SAINT REGIS
`MOHAWK TRIBE,
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` Plaintiffs,
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` v.
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`MICROSOFT CORPORATION,
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` Defendant.
`
` CASE NO. 2:18-cv-00321-JLR
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`DECLARATION OF TAREK EL-
`GHAZAWI
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`DECLARATION OF TAREK EL-GHAZAWI
`CASE NO. 2:18-CV-321-JLR-1
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`KELLER ROHRBACK. L.L.P.
`1201 THIRD AVENUE, SUITE 3200
`SEATTLE, WA 98101-3053
`TELEPHONE: (206) 623-1900
`FACSIMILE: (206) 623-3384
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`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2023, p. 1
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`I.
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`INTRODUCTION
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`1. I have been asked by counsel for Plaintiffs to provide opinions regarding how one of
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`ordinary skill in the art would have understood certain claim terms at issue in this lawsuit.
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`2. All of the opinions stated in this report are based on my current personal knowledge and
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`professional judgment. If called as a witness during the trial in this matter, I am prepared to
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`testify competently about them.
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`3. I am being compensated for my work in this matter but my compensation does not
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`depend on the opinions I render or the outcome of this litigation. I do not have a personal
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`interest in the outcome of this litigation.
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`II.
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`QUALIFICATIONS
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`4. My curriculum vitae is attached as Exhibit A. A summary of my qualifications relevant to
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`this case is provided below.
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`5. I am a Professor of Electrical and Computer Engineering at The George Washington
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`University (GWU), I have created the NSF Industry/University Center for High-Performance
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`Reconfigurable Computing at GWU and directed it for about ten years, I have led many
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`industry and federally funded research projects in reconfigurable computing and published
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`closed to three hundred research publications. I received many honors in my field, a few
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`examples follow. I was elected an IEEE Fellow for my contributions to reconfigurable
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`computing and parallel programming (only one in a thousand members get that honor) and
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`was awarded the Alexander von Humboldt research award for the same reasons (100 scientists
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`selected from around the world in any year by the Humboldt Foundation in Germany), I am a
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`DECLARATION OF TAREK EL-GHAZAWI
`CASE NO. 2:18-CV-321-JLR-2
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`KELLER ROHRBACK. L.L.P.
`1201 THIRD AVENUE, SUITE 3200
`SEATTLE, WA 98101-3053
`TELEPHONE: (206) 623-1900
`FACSIMILE: (206) 623-3384
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2023, p. 2
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`

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`Case 2:18-cv-00321-JLR Document 131-19 Filed 11/05/18 Page 4 of 20
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`distinguished speaker for the IEEE Computer Society and served as a distinguished visiting
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`fellow for the UK Royal Academy of Engineering.
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`III.
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` BASIS OF OPINIONS
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`6. My opinions are abased on my years of education, research, experience, as well as my
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`reading of the patents and prosecution histories. In forming my opinions I have considered the
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`materials identified in this declaration, the patents, and the file histories.
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`7. I may rely on additional materials and provide additional opinions to respond to
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`arguments raised by the Defendants.
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`8. This declaration only represents the opinions I have formed to date. I reserve the right to
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`revise, supplement, or amend my opinions based on new information and my continuing
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`analysis of the patents.
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`IV.
`BACKGROUND OF THE TECHNOLOGY
`A. Traditional Computers
`9. Conventional computers, also known as von Neumann machine or von Neumann
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`Computers. In a traditional computer, hardware is fixed and cannot be changed after
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`manufacturing while different software programs use the existing fixed hardware to perform
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`the required application. The software program is simply a sequence of instructions. Both the
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`software program and the data to operate on reside in the main memory and therefore the
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`processor is connected to the main memory through bus lines that include data bus and address
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`bus. The address bus specifies the address of the memory location where the instruction to be
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`performed or the operand to be manipulated reside. The data bus is used to transfer the
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`instruction and input data to the processor and take the results back from the processor to the
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`DECLARATION OF TAREK EL-GHAZAWI
`CASE NO. 2:18-CV-321-JLR-3
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`KELLER ROHRBACK. L.L.P.
`1201 THIRD AVENUE, SUITE 3200
`SEATTLE, WA 98101-3053
`TELEPHONE: (206) 623-1900
`FACSIMILE: (206) 623-3384
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`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2023, p. 3
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`Case 2:18-cv-00321-JLR Document 131-19 Filed 11/05/18 Page 5 of 20
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`memory. The processor typically goes through a fixed routine of steps to execute the
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`instructions of the software program one by one, this routine is called the instruction execution
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`cycle. The typical steps for such an instruction execution are: Instruction Fetch; Instruction
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`Decode; Execute; Data Memory Access; and Write back the result.
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`10. Conventional computers suffer many inherent limitations: 1. Their architectural is fixed
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`(rigid) and cannot be configured; 2. Their architectures is complex to satisfy all general
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`computations; and 3. They operate in a sequential many. Applications needs and
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`computations required can however change. Conventional processors will have to use the
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`available chip resources to execute those computation. This is by contrast to FPGAs that are
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`malleable and allow customization to create just as needed simple compute architectures and
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`create as many of those as needed to solve the problem at hand.
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`B. FPGAs
`11. An FPGA, or a Field Programmable Gate Array, is an electronic chip that can be
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`programmed and reprogrammed in the field of application, after manufacturing, to provide
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`different functionalities as needed. To do so, FPGAs are largely comprising configurable
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`logical blocks that can be configured to perform the desired logical functions and a set of
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`connecting configurable interconnects. Configurations are established by a bit stream that is
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`generated by application engineers using some form of programming interface.
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`C. Relevant Advanced Computing Concepts History of Heterogeneous Computers
`12. Many architectural enhancements were developed and leveraged over the years
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`sometimes as a concept utilized internally to enhance the conventional architectures or to be
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`used externally to provide computing acceleration. Among these concepts that are relevant
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`DECLARATION OF TAREK EL-GHAZAWI
`CASE NO. 2:18-CV-321-JLR-4
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`KELLER ROHRBACK. L.L.P.
`1201 THIRD AVENUE, SUITE 3200
`SEATTLE, WA 98101-3053
`TELEPHONE: (206) 623-1900
`FACSIMILE: (206) 623-3384
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2023, p. 4
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`

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`Case 2:18-cv-00321-JLR Document 131-19 Filed 11/05/18 Page 6 of 20
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`here are array processing/spatial parallelism, pipelining, systolic arrays, data flow
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`architectures, vector processors and heterogeneous (accelerated) computing.
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`13. Array Processing/Spatial Parallelism- when the underlying has a great deal of data
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`parallelism, in other words multiple data items that need to be processed in the same way at
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`the same time, this parallelism can be exploited to speed up the computation. In conventional
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`processors only if multiple independent processing units are available they can be used up to
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`the available fixed number of such units. In the case of FPGAs, as many units as needed by the
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`application are created and used thereby enabling better unitization of the chip and a much
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`more speed of processing.
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`14. Dataflow Processing: This is a form of processing which is data driven, where rather
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`than executing instructions one by one from the program as in traditional systems (control
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`flow), activities are executed when their input data are received.
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`15. Pipelining: Pipelining is a form of overlapped processing established by breaking the
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`processor needed for a computation into physical modules, called stages that correspond to the
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`subtasks that make up that overall computation. Computations that correspond to different
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`data can be processed concurrently one by each different stage to gain speed. In conventional
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`processors a pipeline can be used for instruction processing and a fixed number of pipelines can
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`be available for arithmetic.
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`16. Systolic Arrays: A systolic arrays is a homogeneous array of interconnected processing
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`elements to perform synchronized processing of data as they proceed in a wave-front style
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`through the array. An analogy between the data movement and the blood circulation in the
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`body is the basis for the name.
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`DECLARATION OF TAREK EL-GHAZAWI
`CASE NO. 2:18-CV-321-JLR-5
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`KELLER ROHRBACK. L.L.P.
`1201 THIRD AVENUE, SUITE 3200
`SEATTLE, WA 98101-3053
`TELEPHONE: (206) 623-1900
`FACSIMILE: (206) 623-3384
`
`
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`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2023, p. 5
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`

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`Case 2:18-cv-00321-JLR Document 131-19 Filed 11/05/18 Page 7 of 20
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`17. Vector Processors: a vector processor is a fixed processor that is optimized for
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`processing vectors/arrays. It has multiple functional units that are built around pipelines that
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`can even be chained connecting the inputs of some to the outputs of the others to form even
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`longer pipelines for obtaining higher speedups. A vector processor also have internal registers
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`that can hold vector operands. Vector processors are typically back end processors, i.e., are
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`managed by a conventional processor. They are suitable for manipulating long arrays.
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`18. Heterogeneous Accelerators: Heterogeneous processors or accelerators are specialized
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`processors that are interconnected to a conventional processor to provide accelerated
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`processing for areas that specialize in. Examples include graphical processing units (GPUs),
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`FPGAs and gaming processors.
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`D. SRC Computers
`19. In the early 2000 my team, which I direct at GWU, has undertaken in cooperation with
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`the government research projects to evaluate the current state of the art in high-performance
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`reconfigurable computing at the time and help advance this field. As part of the process we
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`acquired the first SRC systems (SRC 6 serial #1) among other ones from other vendors to
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`thoroughly evaluate. The state of the art at the time was that FPGA boards used as
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`heterogeneous accelerators were connected to the main system processor through the PCI Bus.
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`Our observation was that this has established a limitation on the performance of such systems.
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`The SRC was the only product that used the RAM bus to connect the FPGA resources to the
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`main processor, which did set SRC apart from the rest. SRC systems also had in addition a
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`more matured software system and training structure.
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`DECLARATION OF TAREK EL-GHAZAWI
`CASE NO. 2:18-CV-321-JLR-6
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`KELLER ROHRBACK. L.L.P.
`1201 THIRD AVENUE, SUITE 3200
`SEATTLE, WA 98101-3053
`TELEPHONE: (206) 623-1900
`FACSIMILE: (206) 623-3384
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`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2023, p. 6
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`

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`Case 2:18-cv-00321-JLR Document 131-19 Filed 11/05/18 Page 8 of 20
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`CLAIM CONSTRUCTION
`20. I have been informed and understand that one of cannons of claim construction is that
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`V.
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`the district court must construe the claims as one of ordinary skill in the art in the relevant field
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`of the invention would, theoretically, construe the claims, and not as a layperson would
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`construe them. I have also been informed that the Court’s claim constructions will be the basis
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`for the jury instructions at trial so my understanding of the claim terms as one of skill in the art
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`should be translated into plain English, to the extent that is possible, to aid the jury’s
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`understanding.
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`21. I have also been informed that ascertaining the meaning of the claims requires that they
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`be viewed in the context of those sources available to the public that show what a person of
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`skill in the art would have understood disputed claim language to mean. The Federal Circuit
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`has stated that different weights are to be placed on these sources. First, the words of the claims
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`themselves provide the starting point for any claim-construction analysis. The second most
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`relevant source is the patent's specification. Third in importance is the prosecution history,
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`which is also part of the intrinsic evidence that directly reflects how the patentee has
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`characterized the invention. Last, extrinsic evidence—testimony, dictionaries, learned treatises,
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`or other material not part of the public record associated with the patent—also may be helpful
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`but is less significant than the intrinsic record in determining the legally operative meaning of
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`claim language.
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`22. I have also been informed that when determining the “ordinary meaning” a claim term
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`the use of technical dictionaries or even a standard dictionary, such as Webster's, is often
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`DECLARATION OF TAREK EL-GHAZAWI
`CASE NO. 2:18-CV-321-JLR-7
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`KELLER ROHRBACK. L.L.P.
`1201 THIRD AVENUE, SUITE 3200
`SEATTLE, WA 98101-3053
`TELEPHONE: (206) 623-1900
`FACSIMILE: (206) 623-3384
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`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2023, p. 7
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`Case 2:18-cv-00321-JLR Document 131-19 Filed 11/05/18 Page 9 of 20
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`appropriate. Generally, however, technical dictionaries in the relevant field should take
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`precedence over general dictionaries.
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`23. I have also been informed that § 112, ¶6 does not does not apply to a claim term if the
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`term is understood by persons of ordinary skill in the art to have a sufficiently definite meaning
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`as the name for a structure.
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`24. I have been asked to provide my opinion regarding the meaning of the following claim
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`terms using the legal principals I was instructed on above.
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`B. Claim Terms from the 6,076,152 & 6,247,110 Patents
`1. “memory bank” – claims 1, 3, 11
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`Plaintiff’s Proposed Construction
`A physical location viewed by the data
`processor as part of the memory subsystem
`having a range of memory addresses that
`may be accessed using only memory access
`methods
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`Microsoft’s Proposed Construction
`a group of devices which are a part of the
`memory subsystem and connected together
`for use as a memory for a data processor
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`25. Microsoft’s proposed construction is too narrow because it implies that only memory
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`can be put into a memory bank. This is clearly inconsistent with the whole computer
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`architecture field as it eliminates the well-established practice of memory-mapped I/O for
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`example which places I/O devices at memory locations. This is particularly incorrect in the
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`context of the ’152/’110 patents because the MAP processors are located in the memory banks.
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`This is clearly illustrated by Fig. 3, which shows the MAP Assembly as part of the overall
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`Memory Bank:
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`DECLARATION OF TAREK EL-GHAZAWI
`CASE NO. 2:18-CV-321-JLR-8
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`KELLER ROHRBACK. L.L.P.
`1201 THIRD AVENUE, SUITE 3200
`SEATTLE, WA 98101-3053
`TELEPHONE: (206) 623-1900
`FACSIMILE: (206) 623-3384
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`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2023, p. 8
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`2. “Means connecting said plurality of memory algorithm processors to said data bus and
`to said address bus such that said plurality of memory algorithm processors are
`individually addressable by said at least one data processor as said at least one data
`processor executes said application program” – claim 1
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`Plaintiff’s Proposed Construction
`Not a means plus function claim element.
`Alternatively:
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`Function: allow the plurality of memory
`algorithm processors to be accessible using
`normal memory access protocols by the data
`processor
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`Structure: placing the plurality of memory
`algorithm processors in the memory space
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`Microsoft’s Proposed Construction
`Function: connecting said plurality of
`memory algorithm processors to said data
`bus and to said address bus such that said
`plurality of memory algorithm processors are
`individually addressable by said at least one
`data processor as said at least one data
`processor executes said application program
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`Structure: No disclosed corresponding
`structure.
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`26. I have been informed by counsel for Plaintiffs that there is a class of claim limitations
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`called means plus function claim elements. If it qualifies as a means plus function claim
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`DECLARATION OF TAREK EL-GHAZAWI
`CASE NO. 2:18-CV-321-JLR-9
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`KELLER ROHRBACK. L.L.P.
`1201 THIRD AVENUE, SUITE 3200
`SEATTLE, WA 98101-3053
`TELEPHONE: (206) 623-1900
`FACSIMILE: (206) 623-3384
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`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2023, p. 9
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`

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`Case 2:18-cv-00321-JLR Document 131-19 Filed 11/05/18 Page 11 of 20
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`element, then the Court must construe the function stated in the claim element according to
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`normal rules of claim construction. After the function is identified, the Court must then
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`examine the patent specification to locate the structure corresponding to the claimed function.
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`I have been informed that the corresponding structure may be disclosed anywhere in the patent
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`specification and may be generically described if the structure was well known in the art at the
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`time of invention. I have also been informed that if the patent specification fails to disclose
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`adequate corresponding structure, the claim is indefinite.
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`27. The parties disagree about whether this term is a means plus function claim element. I
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`understand that here there is a rebuttable presumption that this claim term is a means plus
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`function limitation because this it uses the word “means.” But I understand that this
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`presumption can be overcome if the claim itself connotes to one of ordinary skill in the art
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`sufficiently definite structure to perform the claimed function.
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`28. There are several issues that need to be resolved regarding this claim term (i) whether
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`this claim term is a means plus function limitation and (ii) if so, the proper construction of the
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`function and the structure corresponding to that function.
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`29. Based on my reading of the claim language, patent specification, and prosecution
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`history it is my opinion that this claim limitation is not a means plus function element because
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`it describes sufficient structure to perform the claimed function, which is to “allow the plurality
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`of memory algorithm processors to be accessible using normal memory access protocols by the
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`data processor.”
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`DECLARATION OF TAREK EL-GHAZAWI
`CASE NO. 2:18-CV-321-JLR-10
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`KELLER ROHRBACK. L.L.P.
`1201 THIRD AVENUE, SUITE 3200
`SEATTLE, WA 98101-3053
`TELEPHONE: (206) 623-1900
`FACSIMILE: (206) 623-3384
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`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2023, p. 10
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`Case 2:18-cv-00321-JLR Document 131-19 Filed 11/05/18 Page 12 of 20
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`30. This construction comports with my understanding of the ordinary meaning of the
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`claim term, which states: “such that said plurality of memory algorithm processors are
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`individually addressable by said at least one data processor.”
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`31. The prosecution history and specification confirm this construction by repeatedly
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`stating that the processor can access the memory algorithm processors using normal memory
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`access protocols:
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`Wherein the data processor’s memory bank contains memory
`algorithm processors that are memory addressable by the data
`processor – that is, the data processor views the memory
`algorithm processors merely as part of the data processor’s
`memory.1
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`By placing MAPS 112 in the MEMORY SPACE that is
`associated with the plurality of PROCESSORS 108, any given
`MAP 112 can be readily accessed by any given PROCESSORS
`108 merely through the use of memory read operation or
`memory write operation.2
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`Each of the processors 108 “views” each individual one of the
`plurality of USER FPGAs 134 merely as an individual memory
`addressable locations within memory bank 120.3
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`Still further provided is a computer system memory structure
`which includes one or more FPGAs for the purpose of using
`normal memory access protocol to access it as well as being
`capable of direct memory access ("DMA") operation.4
`
`The computer architecture 100 comprises a multiprocessor
`system employing uniform memory access across common
`
`
`1 SRC00002102
`2 SRC00002103.
`3 SRC00002106.
`4 ’152 patent, 2:16-20.
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`DECLARATION OF TAREK EL-GHAZAWI
`CASE NO. 2:18-CV-321-JLR-11
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`KELLER ROHRBACK. L.L.P.
`1201 THIRD AVENUE, SUITE 3200
`SEATTLE, WA 98101-3053
`TELEPHONE: (206) 623-1900
`FACSIMILE: (206) 623-3384
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`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2023, p. 11
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`

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`Case 2:18-cv-00321-JLR Document 131-19 Filed 11/05/18 Page 13 of 20
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`
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`shared memory with one or more MAPs 112 located in the
`memory subsystem, or memory space.5
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`By placing the MAP 112 in the memory subsystem or memory
`space, it can be readily accessed through the use of memory
`read and write commands, which allows the use of a variety of
`standard operating systems.6
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`32. I understand these statements to disclose physically locating the memory algorithm
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`processors in the memory space of the processor. This structure enables the processor to access
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`the memory algorithm processors using normal memory access protocols, such as memory
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`read and write commands. Such functionality is implied from the structure and is obvious to
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`anyone with average experience in the field. They are also addressed in some of the patents
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`themselves.
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`33. The claim itself discloses the structure needed to enable this functionality by describing
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`a “memory bank with a data bus and an address bus connected to said at least one data
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`processor” with “a plurality of memory algorithm processors within individually addressable
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`portions of said memory bank”:
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`1. In a computer system having at least one data processor for executing an
`application program by operating on user data in accordance with
`application program instructions, said computer system having at least one
`memory bank with a data bus and an address bus connected to said at
`least one data processor, the improvement comprising:
`a plurality of memory algorithm processors within individually addressable
`portions of said memory bank;
`means connecting said plurality of memory algorithm processors to said data
`bus and to said address bus such that said plurality of memory algorithm
`processors are individually memory addressable by said at least one data
`processor as said at least one data processor executes said application
`program; and
`
`5 ’152 patent, 4:1-4.
`6 ’152 patent, 4:29-32.
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`DECLARATION OF TAREK EL-GHAZAWI
`CASE NO. 2:18-CV-321-JLR-12
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`KELLER ROHRBACK. L.L.P.
`1201 THIRD AVENUE, SUITE 3200
`SEATTLE, WA 98101-3053
`TELEPHONE: (206) 623-1900
`FACSIMILE: (206) 623-3384
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2023, p. 12
`
`

`

`Case 2:18-cv-00321-JLR Document 131-19 Filed 11/05/18 Page 14 of 20
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`said plurality of memory algorithm processors being configured as individual
`data processing machines that can be memory addressed to perform data
`processing related to said application program in accordance with an
`identified algorithm, said data processing being performed on at least one
`operand that is received as a result of a write operation to said memory bank
`by said at least one data processor.
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`34. This is confirmed by Dr. Trimberger’s declaration that was filed as Ex. 1003 to
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`Microsoft’s Petition Requesting Inter Partes Review (IPR) of the ’152 patent (“Trimberger
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`Decl.”). In his declaration, Dr. Trimberger states that locating the memory algorithm
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`processors in the processor’s memory would make them individually memory addressable by
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`the processor. 7
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`35. Dr. Trimberger agrees that “A Skilled Artisan would therefore understand that
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`‘memory addressable’ in the context of the 152 Patent means accessible using normal memory
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`access protocol.”8
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`36. Alternatively, if the Court finds that this claim element is a means plus function claim
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`then I believe that the function should must be construed as “allow the plurality of memory
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`algorithm processors to be accessible using normal memory access protocols by the data
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`processor.”
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`37. The corresponding structure disclosed in the specification is “placing the plurality of
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`memory algorithm processors in the memory space.” This is described in numerous places.
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`38. The Abstract describes “A multiprocessor computer architecture incorpating a plurality
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`of programmable hardware memory algorithm processors (‘MAP’) in the memory subsystem.”
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`7 Trimberger Decl. at ¶¶ 156-174.
`8 Trimberger Decl. at ¶¶ 79-84.
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`DECLARATION OF TAREK EL-GHAZAWI
`CASE NO. 2:18-CV-321-JLR-13
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`13
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`KELLER ROHRBACK. L.L.P.
`1201 THIRD AVENUE, SUITE 3200
`SEATTLE, WA 98101-3053
`TELEPHONE: (206) 623-1900
`FACSIMILE: (206) 623-3384
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`

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`Case 2:18-cv-00321-JLR Document 131-19 Filed 11/05/18 Page 15 of 20
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`39. Figures 2 and 3 shows MAPs located in the memory space (or memory bank):
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`KELLER ROHRBACK. L.L.P.
`1201 THIRD AVENUE, SUITE 3200
`SEATTLE, WA 98101-3053
`TELEPHONE: (206) 623-1900
`FACSIMILE: (206) 623-3384
`
`
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`DECLARATION OF TAREK EL-GHAZAWI
`CASE NO. 2:18-CV-321-JLR-14
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`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2023, p. 14
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`

`

`Case 2:18-cv-00321-JLR Document 131-19 Filed 11/05/18 Page 16 of 20
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`40. The architectural structure of locating the plurality of memory algorithm processors in
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`the memory space is what makes them accessible to the data processor using normal memory
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`access protocols by the data processor:
`
`Still further provided is a computer system memory structure
`which includes one or more FPGAs for the purpose of using
`normal memory access protocol to access it as well as being
`capable of direct memory access ("DMA") operation.9
`
`The computer architecture 100 comprises a multiprocessor
`system employing uniform memory access across common
`shared memory with one or more MAPs 112 located in the
`memory subsystem, or memory space.10
`
`By placing the MAP 112 in the memory subsystem or memory
`space, it can be readily accessed through the use of memory
`read and write commands, which allows the use of a variety of
`standard operating systems.11
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`41. The patented invention states the very purpose of locating the memory algorithm
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`processors in the memory space (or memory bank) is so that they may be accessed using these
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`the same “normal memory access protocol” that a CPU uses to store and retrieve data from
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`memory.12 This would have been readily understood by one of ordinary skill in the art in
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`December 1997.
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`42. Accordingly, if this claim element is a means plus function claim element it is not
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`indefinite because the patent specification discloses adequate corresponding structure that
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`clearly implies the function.
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`9 ’152 patent, 2:16-20.
`10 ’152 patent, 4:1-4.
`11 ’152 patent, 4:29-32.
`12 ’152 patent, 2:16-20.
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`DECLARATION OF TAREK EL-GHAZAWI
`CASE NO. 2:18-CV-321-JLR-15
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`KELLER ROHRBACK. L.L.P.
`1201 THIRD AVENUE, SUITE 3200
`SEATTLE, WA 98101-3053
`TELEPHONE: (206) 623-1900
`FACSIMILE: (206) 623-3384
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`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2023, p. 15
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`

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`Case 2:18-cv-00321-JLR Document 131-19 Filed 11/05/18 Page 17 of 20
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`3. “means coupling said plurality of individual memory algorithm processors to said data
`bus and to said address bus” – claim 11
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`Plaintiff’s Proposed Construction
`Not a means plus function. In the
`alternative, if the court disagrees:
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`Function: allows the memory algorithm
`processors to be individually memory
`addressable
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`Structure: connecting the plurality of
`memory algorithm processors to the data bus
`and address bus
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`Microsoft’s Proposed Construction
`Function: “coupling said plurality of
`individual memory algorithm processors to
`said data bus and to said address bus”
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`Structure: No disclosed corresponding
`structure
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`43. As with the prior term, the parties disagree about whether this term is a means plus
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`function claim element. So again there are several issues that need to be resolved regarding this
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`claim term (i) whether this claim term is a means plus function limitation and (ii) if so, the
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`proper construction of the function and the structure corresponding to that function.
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`44. Based on my reading of the claim language, patent specification, and prosecution
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`history it is my opinion that this claim limitation is not a means plus function element because
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`it is describing only a structure.
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`45. The “means coupling” anything to a bus would always be a structure. This is because it
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`is a description of which modules (in this case the memory algorithm processors, the data bus
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`and the address bus) are attached to one another.
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`
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`DECLARATION OF TAREK EL-GHAZAWI
`CASE NO. 2:18-CV-321-JLR-16
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`KELLER ROHRBACK. L.L.P.
`1201 THIRD AVENUE, SUITE 3200
`SEATTLE, WA 98101-3053
`TELEPHONE: (206) 623-1900
`FACSIMILE: (206) 623-3384
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`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2023, p. 16
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`

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`Case 2:18-cv-00321-JLR Document 131-19 Filed 11/05/18 Page 18 of 20
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`46. This is illustrated in Fig. 3.
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`47. A processors memory bank or memory space is always connected to a data bus or
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`address bus. So if the memory algorithm processors are in the memory bank then they will be
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`connected to a data bus and address bus.
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`DECLARATION OF TAREK EL-GHAZAWI
`CASE NO. 2:18-CV-321-JLR-17
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`KELLER ROHRBACK. L.L.P.
`1201 THIRD AVENUE, SUITE 3200
`SEATTLE, WA 98101-3053
`TELEPHONE: (206) 623-1900
`FACSIMILE: (206) 623-3384
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`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2023, p. 17
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`

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`Case 2:18-cv-00321-JLR Document 131-19 Filed 11/05/18 Page 19 of 20
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`C. Claim Terms from the 7,421,524 Patent
`1. “memory module bus” – claims 1, 3, 11
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`Plaintiff’s Proposed Construction
`a bus used to communicate with a range of
`locations where a memory module could be
`inserted and accessed by the data processor
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`Microsoft’s Proposed Construction
`A bus used to communicate with a memory
`module
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`
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`48. In the context of this case, the SRC definition is correct because it does not restrict only
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`memory to be mapped to the memory bank space, thereby