Case 2:18-cv-00317-JLR Document 115-2 Filed 11/05/18 Page 1 of 29
`
`EXHIBIT 1
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2015. p. 1
`
`

`

`Case 2:18-cv-00317-JLR Document 115-2 Filed 11/05/18 Page 2 of 29
`
`UNITED STATES DISTRICT COURT
`WESTERN DISTRICT OF WASHINGTON
`AT SEATTLE
`
`
`SRC LABS, LLC, and
`SAINT REGIS MOHAWK TRIBE,
`Plaintiffs,
`
`
`
`v.
`
`
`AMAZON WEB SERVICES, INC.,
`AMAZON.COM, INC., and
`VADATA, INC.,
`
`Defendants.
`
`)
`)
`)
`)
`)
`)
`)
`)
`)
`)
`)
`)
`)
`)
`
`
`
`Case No. 2:18-cv-00317-JLR
`
`JURY TRIAL DEMANDED
`
`OPENING REPORT OF BRAD HUTCHINGS, PH.D.,
`REGARDING MARKMAN ISSUES
`
`I, BRAD L. HUTCHINGS, PH.D., declare as follows:
`
`1.
`
`The facts and opinions listed below are within my personal knowledge. If called
`
`as a witness, I could and would testify competently to the matters provided herein. I am over the
`
`age of eighteen and am a citizen of the United States.
`
`2.
`
`I understand that Plaintiffs SRC Labs, LLC, and Saint Regis Mohawk Tribe (col-
`
`lectively, “SRC”) assert U.S. Patent Nos. 7,149,867 (the “’867 patent”), 7,225,324 (the “’324 pa-
`
`tent”), 7,620,800 (the “’800 patent”), and 9,153,311 (the “’311 patent) (collectively, “the patents-
`
`in-suit”) against Amazon Web Services, Inc., Amazon.com, Inc., and VADATA, Inc. (collectively,
`
`“Amazon”). I was asked by Amazon to provide my opinions about what certain claim terms of
`
`the patents-in-suit mean to a person having ordinary skill in the art at the time the patents-in-suit
`
`were filed.
`
`1
`
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2015. p. 2
`
`

`

`Case 2:18-cv-00317-JLR Document 115-2 Filed 11/05/18 Page 3 of 29
`
`I.
`
`QUALIFICATIONS
`
`3.
`
`Here, I provide a brief summary of my qualifications. My qualifications are stated
`
`more fully in my curriculum vitae, which is attached to this declaration as Exhibit A. I have re-
`
`viewed the patents-in-suit and am familiar with the subject matter thereof, which relates to my
`
`training, education, and background. I am qualified to testify as an expert on matters related to
`
`these patents.
`
`4.
`
`I am a professor in the department of Electrical and Computer Engineering at
`
`Brigham Young University (BYU) in Provo, Utah. I received a Bachelor of Science degree in
`
`Computer Science in 1984, a Master of Science degree in Computer Science in 1987, and a Ph.D.
`
`degree in Computer Science in 1992, all from the University of Utah. I have been a professor at
`
`BYU since 1992. Since that time, I also established the Reconfigurable Computing Laboratory at
`
`BYU in 1993. In 1998, I was a visiting scholar at HP Labs in Bristol, England, where I was part
`
`of a group that designed and studied reconfigurable devices for portable appliances. From 2003
`
`to 2007, I worked as a director at Tabula, an FPGA design and manufacturing company that I
`
`helped to start. I have published extensively in the reconfigurable-computing community and reg-
`
`ularly consult with the industry. I serve on the committees of many of the conferences related to
`
`reconfigurable computing and FPGAs. My research interests include programmable devices and
`
`architectures, tool flows, debugging strategies, and parallel computation.
`
`5.
`
`I have over 25 years of experience working with and designing FPGAs. In that
`
`time, I have also taught numerous FPGA-related courses to both undergraduate and graduate stu-
`
`dents. I have published over 70 articles related to FPGA technology and am a named inventor on
`
`over 60 patents related to FPGA devices and debugging of FPGA circuits. I was also qualified as
`
`an expert witness in patent-litigation matters related to FPGA technology.
`
`II. MATERIALS CONSIDERED
`
`2
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2015. p. 3
`
`

`

`Case 2:18-cv-00317-JLR Document 115-2 Filed 11/05/18 Page 4 of 29
`
`6.
`
`In reaching my opinions, I have reviewed the patents-in-suit and their respective
`
`file histories and prior art that was referenced by the Patent Office during prosecution of the pa-
`
`tents. I have also reviewed the parties’ proposed claim constructions along with support each party
`
`cited in support of the respective constructions to date. I also reviewed SRC’s infringement con-
`
`tentions and Amazon’s invalidity contentions. Additionally, I have reviewed dictionary definitions
`
`and any literature I reference below. In forming my opinions, I also relied on my knowledge and
`
`expertise in the field. My opinions below are not exhaustive, and they are provided without the
`
`benefit of being able to consider the opinions of any expert retained by SRC. I reserve the right to
`
`offer additional opinions in response to any expert opinions or briefing from SRC, including during
`
`my deposition or at the claim construction hearing in this action. I may also provide a tutorial to
`
`the Court concerning the patents-in-suit generally, the underlying technology, and the state of the
`
`art at the time of the alleged invention, or provide any other testimony the Court may request or
`
`find helpful.
`
`7.
`
`I am being compensated for my time in this proceeding at my standard rate of $500
`
`per hour. My compensation in this matter is not based in any way on the outcome of the litigation,
`
`or the nature of my opinions, and I have no financial or business interest in any of the parties in
`
`this case.
`
`III. LEVEL OF ORDINARY SKILL IN THE ART
`
`8.
`
`I understand that the ’867 patent claims priority to June 18, 2003; the ’324 and ’800
`
`patents claim priority to October 31, 2002; and the ’311 patent claims priority to May 27, 2014.
`
`In forming my opinions regarding claim construction, I have applied the level of ordinary skill as
`
`of the priority date claimed for each of the patents-in-suit.
`
`3
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2015. p. 4
`
`

`

`Case 2:18-cv-00317-JLR Document 115-2 Filed 11/05/18 Page 5 of 29
`
`9.
`
`In my opinion, a person having ordinary skill in the art at the time of the alleged
`
`invention of the patents-in-suit would have had a Bachelor’s degree in electrical engineering, com-
`
`puter engineering, or a related field, with two to three years of experience working with reconfig-
`
`urable systems. With more education, such as additional graduate degrees and/or study, less ex-
`
`perience is needed to attain the ordinary level of skill.
`
`10.
`
`Both now and at the time of the filing of the patents-in-suit, I possessed at least
`
`ordinary skill in the art. At the relevant time frame, I worked with, taught, and knew many indi-
`
`viduals who would qualify as persons of ordinary skill in the art. As a result of my education and
`
`over twenty-five years of experience in reconfigurable computing, I am very familiar with the state
`
`of the art in the area to which the patents-in-suit relate.
`
`IV. CLAIM CONSTRUCTION FRAMEWORK
`
`11.
`
`I understand that claim construction is governed by a number of legal principles. I
`
`am not a lawyer. I have been advised of the relevant legal principles and have used them as a basis
`
`for my opinions.
`
`12.
`
`I understand that claim terms and phrases are to be given their plain and ordinary
`
`meaning unless the patentee provided a special meaning. I also understand that claims must be
`
`read in light of the written description of the invention in the patent’s specification. Additionally,
`
`I understand that the prosecution history can further inform the meaning of the claim language by
`
`demonstrating how the inventor understood the invention and whether the inventor limited the
`
`invention in the course of prosecution, making the claim scope narrower than it might be otherwise.
`
`In addition, I understand that both general and technical dictionaries may assist the Court in con-
`
`struing a claim term.
`
`A. Means-plus-function terms
`
`4
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2015. p. 5
`
`

`

`Case 2:18-cv-00317-JLR Document 115-2 Filed 11/05/18 Page 6 of 29
`
`13.
`
`I understand that a patentee may express a claim limitation as a means for perform-
`
`ing a given function. These kinds of terms are called “means-plus-function” terms and are subject
`
`to special rules of claim construction.
`
`14.
`
`I also understand that one determines whether a claim term is in means-plus-func-
`
`tion form by considering whether the claims disclose a structure or whether the limitation speaks
`
`in purely functional terms. A claim term that uses the word “means” may trigger a presumption
`
`that it is a means-plus-function term. This presumption can be overcome if the term itself recites
`
`the structure, the term connotes a known structure to one of skill in the art, or the claim does not
`
`recite any function for the means term to perform. Conversely, a term that does not use similar
`
`“means” phrasing is presumed not to be in means-plus-function form. This presumption is over-
`
`come where the term does not connote a sufficiently definite structure to perform the entire claimed
`
`function or recites a function without reciting structure for performing that function. I further
`
`understand that it is not sufficient that one of skill could have carried out the recited function in a
`
`variety of ways. Instead, the relevant inquiry is whether the term connotes to a person of ordinary
`
`skill in the art a sufficiently definite structure for performing the recited function.
`
`15.
`
`I understand that means-plus-function limitations are construed to “cover the cor-
`
`responding structure, material, or acts described in the specification and equivalents thereof.” 35
`
`U.S.C. § 112(6). Means-plus-function limitations are construed using a two-step process. First,
`
`the court uses ordinary principles of claim construction to determine the function explicitly set
`
`forth in the claims. Second, the court determines from the perspective of a person of ordinary skill
`
`in the art what structure, if any, disclosed in the specification corresponds to the claimed function.
`
`Any such structure must be clearly associated with the performance of the function.
`
`B.
`
`Indefiniteness
`
`5
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2015. p. 6
`
`

`

`Case 2:18-cv-00317-JLR Document 115-2 Filed 11/05/18 Page 7 of 29
`
`16.
`
`I understand that in order for a patent to be valid, it must satisfy the statutory defi-
`
`niteness requirement. The definiteness requirement provides that the patent specification must
`
`“conclude with one or more claims particularly pointing out and distinctly claiming the subject
`
`matter that the applicant regards as the invention.” 35 U.S.C. § 112(2). In determining whether a
`
`patent claim is indefinite, a court must consider whether the claims, read in light of the specifica-
`
`tion delineating the patent, provide reasonable certainty about the scope of the invention to one
`
`skilled in the art.
`
`17.
`
`In the case of means-plus-function limitations, it is my understanding that if a cor-
`
`responding structure for performing the function is not set out in the specification, then the claim
`
`is indefinite. It is my understanding that even if the specification discloses some corresponding
`
`structure, a means-plus-function limitation may be indefinite if that disclosure is inadequate to
`
`perform the entire claimed function. I understand that in order to meet the definiteness requirement
`
`of 35 U.S.C. § 112(6), the specification must include a disclosure sufficient for one skilled in the
`
`art to understand what structure disclosed in the specification performs the function recited in the
`
`claim. To ascertain the structure that corresponds with the recited function, the specification must
`
`clearly link or associate a structure with the particular function recited in the claim.
`
`18.
`
`In addition, I understand that for claims directed towards computer-implemented
`
`inventions, the structure disclosed in the specification generally must be more than a general-pur-
`
`pose computer or microprocessor. This is because general purpose computers can be programmed
`
`to perform different tasks in different ways and such a disclosure would effectively provide no
`
`limit on the scope of the claims. Thus, the corresponding structure for a computer-implemented
`
`function is not a computer, but is a specific algorithm that allows a general-purpose computer or
`
`microprocessor to perform the claimed function. An “algorithm” is a fixed step-by-step procedure
`
`6
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2015. p. 7
`
`

`

`Case 2:18-cv-00317-JLR Document 115-2 Filed 11/05/18 Page 8 of 29
`
`for accomplishing a given result. A patentee may express the procedural algorithm in any under-
`
`standable terms including as a mathematical formula, in prose, or as a flow chart. A patentee is
`
`not required to produce a listing of source code or a highly detailed description of the algorithm to
`
`be used to achieve the claimed function in order to satisfy 35 U.S.C. § 112(6). The patentee is
`
`required, however, to at least disclose the algorithm that transforms the general-purpose micropro-
`
`cessor to a special-purpose computer which is programmed to perform the algorithm. I am in-
`
`formed that a patent claim is invalid as being indefinite if the specification fails to disclose in
`
`sufficient detail an algorithm for programming the computer or microprocessor. There is one ex-
`
`ception to this general rule—a patent can meet the requirements of Section 112(6) by reciting only
`
`a general-purpose computer or microprocessor (with no corresponding algorithm) if the claimed
`
`function can be achieved without any special programming.
`
`V.
`
`OVERVIEW OF THE ’311 PATENT
`
`19.
`
`The ’311 patent is titled “System and Method for Retaining DRAM Data when
`
`Reprogramming Reconfigurable Devices with DRAM Memory Controllers.” DRAM is a well-
`
`known component in computer engineering; it stands for dynamic random access memory and is
`
`a type of random access semiconductor memory used in computing devices. Data stored in DRAM
`
`decays over time, as charges in the memory cells leak away. To prevent this, DRAM cells must
`
`be “refreshed”—their data must be read and written back to them on a regular basis. Generally, in
`
`DRAM systems, the memory controller initiates the refresh cycle. Some DRAM systems also
`
`offer a “self-refresh” mode, in which the DRAM refreshes its contents without the memory con-
`
`troller’s involvement. This is generally used when the system enters a power-save mode but the
`
`memory contents must be preserved.
`
`20.
`
`The ’311 patent attempts to disclose “a system and method for preserving DRAM
`
`memory contents when a reconfigurable device, for example an FPGA having a DRAM memory
`
`7
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2015. p. 8
`
`

`

`Case 2:18-cv-00317-JLR Document 115-2 Filed 11/05/18 Page 9 of 29
`
`controller, is reconfigured, reprogrammed or otherwise powered down.” ’311 patent at 1:63-66.
`
`An FPGA, or a field programmable array, is a computer chip whose circuits can be configured or
`
`re-programmed by a consumer or developer—“in the field,” as it were. Like most computer sys-
`
`tems, FPGA-based systems are usually coupled with a random-access memory (typically DRAM)
`
`subsystem to store machine code and data while it is in use. Interfacing with the DRAM subsystem
`
`requires a memory controller, which in FPGA systems comprises part of the field programming of
`
`the FPGA. See, e.g., id. at 1:28-45.
`
`21.
`
`As the patent describes:
`
`A significant problem arises in reconfigurable computing when the FPGA is repro-
`grammed during a live application and the memory controller tri-states all inputs
`and outputs (I/O) between the FPGA device and the DRAM. The result is corrupted
`data in the memory subsystem. Therefore, dynamically reconfigurable processors
`are excluded as viable computing options, especially in regard to database applica-
`tions or context switch processing. The reason for this is that the time it takes to
`copy the entire contents of DRAM data and preserve it in another part of the system,
`reconfigure the processor, then finally retrieve the data and restore it in DRAM is
`just too excessive.
`
`Id. at 1:48-59.1
`
`22.
`
`To attempt to solve this problem, the ’311 patent introduces a data maintenance
`
`block and delegates to it the self-refresh command signals. The data maintenance block keeps the
`
`DRAM cells in self-refresh mode while the FPGA is being reprogrammed and until a newly con-
`
`figured memory controller is ready to reassume control over the refresh cycle. See generally id.
`
`at 1:67-2:22, 2:43-56. The Summary of the Invention of the patent describes that “the FPGA drives
`
`
`1 One skilled in the art would understand that when the FPGA tri-states all outputs during recon-
`figuration, the control signals connected to the DRAM take on arbitrary values and the DRAM is
`no longer controlled by the FPGA (including the refresh cycle).
`
`8
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2015. p. 9
`
`

`

`Case 2:18-cv-00317-JLR Document 115-2 Filed 11/05/18 Page 10 of 29
`
`the majority of the DRAM input/output (I/O) and the data maintenance block drives the self-re-
`
`fresh command inputs.” Id. at 2:7-9. As the same section describes, “the data maintenance block
`
`does not contain the memory controller.” Id. at 2:13-14.
`
`23.
`
`The ’311 patent describes that “using the self-refresh capability of DRAM alone is
`
`not adequate for maintaining data integrity during reconfiguration.” Id. at 2:29-31. That is because
`
`when the memory controller resumes control over the DRAM subsystem, it assumes that no useful
`
`data is in DRAM and so initializes itself by reading and writing to specific memory locations as
`
`part of a calibration process. The ’311 patent discloses reading the data at those DRAM locations
`
`before the FPGA is reconfigured, storing them in the data maintenance block during reconfigura-
`
`tion, and then retrieving and writing them to the DRAM after reconfiguration is complete and the
`
`memory controller is initialized. See generally id. at 2:23-42.
`
`24.
`
`In particular, the Summary of the Invention describes that the memory controller
`
`within the FPGA communicates with the data maintenance block via a communication port to
`
`instruct the data maintenance block to send self-refresh command signals to the DRAM. Id. at
`
`2:17-22. Before the FPGA is reconfigured, the memory controller retrieves data from DRAM and
`
`transmits the data via the communication port to the data maintenance block, where the data is
`
`stored. Id. at 2:21-42. This data includes data from specific memory addresses in the DRAM that
`
`will be corrupted when the memory controller in the FPGA attempts to calibrate with the DRAM
`
`after the FPGA is reconfigured. Id. at 2:49-52. The Summary of the Invention explains that the
`
`specific memory addresses “used during calibration/leveling are known and typically detailed in
`
`the controller IP specification.” Id. at 2:31-33. The FPGA retrieves the data from the DRAM
`
`using direct memory access (DMA) read requests to the specific memory addresses. Id. at 5:1-6.
`
`The DRAM data is then stored in the data maintenance block’s block RAM. Id. at 5:7-10. After
`
`9
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2015. p. 10
`
`

`

`Case 2:18-cv-00317-JLR Document 115-2 Filed 11/05/18 Page 11 of 29
`
`the process of storing the DRAM data in the data maintenance block is complete, the data mainte-
`
`nance block sends a self-refresh command to the DRAM and transmits an acknowledge signal
`
`back to the FPGA. Id. at 2:43-45. The FPGA can then be reprogrammed.
`
`25.
`
`Once reprogramming is complete, the memory controller calibrates with the
`
`DRAM, thereby corrupting data stored in the specific memory addresses of the DRAM. Id. at
`
`2:49-52. The data maintenance block then notifies FPGA logic surrounding the memory controller
`
`that the FPGA has awakened from “either an initial power up condition or a reconfiguration con-
`
`dition.” Id. at 2:49-56. If a “reconfiguration condition is detected,” the memory controller re-
`
`trieves stored DRAM data from the data maintenance block via the communication port and writes
`
`it back to the specific address locations corrupted during the calibration process. Id. at 2:56-61.
`
`Once this is complete, the FPGA resumes normal operation, servicing DRAM memory requests in
`
`“the traditional fashion.” Id. at 2:61-63.
`
`26.
`
`I understand that SRC asserts claims 1, 3, 9 and 10 of the ’311 patent. Claim 1 of
`
`is an independent claim, while the other three asserted claims depend from it.
`
`VI. DISPUTED CLAIM TERMS OF THE ’311 PATENT
`A.
`“a data maintenance block”
`
`27.
`
`The term “a data maintenance block” appears in asserted claim 1 of the ’311 patent
`
`(and is also referred to explicitly in claim 9 and claim 10). I understand the parties dispute the
`
`construction of this term and have proposed the following competing constructions:
`
`“a data maintenance block”
`Amazon’s Proposed Construction
`SRC’s Proposed Construction
`“a circuit separate from the memory control-
`“circuit or logic device for retaining DRAM
`ler that drives self-refresh command inputs
`memory data when the reconfigurable logic de-
`and stores DRAM memory data when the re-
`vice is reconfigured”
`configurable logic device is reconfigured”
`
`
`
`
`10
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2015. p. 11
`
`

`

`Case 2:18-cv-00317-JLR Document 115-2 Filed 11/05/18 Page 12 of 29
`
`28.
`
`As shown above, the parties’ proposed constructions have certain similarities. Both
`
`parties agree that the claimed data maintenance block is a circuit for “stor[ing]” or “retaining”
`
`“DRAM memory data when the reconfigurable logic device is reconfigured.” In my opinion,
`
`however, SRC’s proposed construction omits a portion of the implicit definition of the term in the
`
`patent and is thus inaccurate. Amazon’s proposed construction, on the other hand, correctly re-
`
`flects the requirement that the claimed data maintenance block not only store DRAM data when
`
`the reconfigurable logic device is reconfigured, but also that it is separate from the memory con-
`
`troller and drives self-refresh command inputs.
`
`29.
`
`“Data maintenance block” was not a term of art in 2014, when the ’311 patent was
`
`filed. Accordingly, I understand its meaning needs to be gleaned from the ’311 patent itself and
`
`its prosecution history. The patent makes clear that the data maintenance block 1) is separate from
`
`the memory controller, 2) stores DRAM memory data when the reconfigurable logic device is
`
`reconfigured, and 3) drives self-refresh command inputs. I address each of these requirements
`
`below.
`
`30.
`
`First, the ’311 patent makes clear that the “data maintenance block” must be sepa-
`
`rate from the memory controller. Each independent claim of the ’311 patent separately recites a
`
`“memory controller” and a “data maintenance block.” In particular, claim 1 requires “a reconfig-
`
`urable logic device having a memory controller” in addition to “a data maintenance block coupled
`
`to said reconfigurable logic device.” Likewise, claim 11, the only other independent claim, re-
`
`quires “a reconfigurable device having a memory controller” as well as “a data maintenance block
`
`coupled to said reconfigurable device.”
`
`31.
`
`Throughout the specification of the ’311 patent, the data maintenance block is sim-
`
`ilarly described as separate from, and working in concert with, the memory controller. ’311 patent
`
`11
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2015. p. 12
`
`

`

`Case 2:18-cv-00317-JLR Document 115-2 Filed 11/05/18 Page 13 of 29
`
`at Abstract (“The DRAM memory controller is utilized in concert with an internally or externally
`
`located data maintenance block . . . .”); id. at 2:4-7 (“In accordance with the system and method
`
`of the present invention, an FPGA based DRAM controller is utilized in concert with an internally
`
`or externally located data maintenance block.”); id. at 2:13-14 (“the data maintenance block does
`
`not contain the memory controller”).
`
`32.
`
`At points, the specification discusses that the data maintenance block may be “in-
`
`ternally or externally located.” Id. at Abstract, 2:5-7. After reading the ’311 patent, one skilled in
`
`the art would understand the patent describing that the data maintenance block is internally or
`
`externally located in relation to the reconfigurable device, not the memory controller: “In a rep-
`
`resentative embodiment of the present invention, the data maintenance block 106 may be conven-
`
`iently provided as a . . . separate integrated circuit device or, in alternative embodiments, may be
`
`provided as a portion of an FPGA comprising the reconfigurable logic device 104.” Id. at 4:23-
`
`29.
`
`33.
`
`The patent also makes clear visually that the “data maintenance block” is separate
`
`from the memory controller, as shown in Figure 1 below.
`
`12
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2015. p. 13
`
`

`

`Case 2:18-cv-00317-JLR Document 115-2 Filed 11/05/18 Page 14 of 29
`
`34.
`
`Figure 1 shows that the data maintenance block 106 is separate from memory con-
`
`troller 118. Although I understand that patent figures generally illustrate embodiments, here the
`
`’311 patent states that Figure 1 “illustrat[es] the data maintenance block of the present invention.”
`
`
`
`Id. at 3:59-64.
`
`35.
`
`In fact, if the data maintenance block were not separate and distinct from the
`
`memory controller, the system disclosed in the ’311 patent would not be able to work as described.
`
`The Summary of the Invention describes that what the patent discloses is “a system and method
`
`for preserving DRAM data contents in a reconfigurable computing environment when the pro-
`
`grammable device is reconfigured with a new design that does not include a DRAM controller.”
`
`13
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2015. p. 14
`
`

`

`Case 2:18-cv-00317-JLR Document 115-2 Filed 11/05/18 Page 15 of 29
`
`Id. at 3:21-25. In other words, if the data maintenance block was part of the memory controller,
`
`and the memory controller is eliminated when the FPGA is reconfigured, then the data maintenance
`
`block along with the data that it stores would be lost or corrupted during reconfiguration, thereby
`
`defeating the purpose of the data maintenance block described in the patent.
`
`36.
`
`Relatedly, the data maintenance block, while the FPGA is being reconfigured, must
`
`store DRAM memory data that would otherwise be corrupted during calibration. The patent’s
`
`background explains the problem it attempts to solve: “A significant problem arises in reconfigu-
`
`rable computing when the FPGA is reprogrammed during a live application and the memory con-
`
`troller tri-states all inputs and outputs (I/O) between the FPGA device and the DRAM. The result
`
`is corrupted data in the memory subsystem.” Id. at 1:48-53. The patent’s proposed solution is to
`
`store the DRAM data that would ordinarily be corrupted in prior art systems in block RAM of a
`
`data maintenance block separate from the memory controller while the FPGA is reconfigured, and
`
`then write the data back to DRAM after the FPGA is reconfigured:
`
`Also illustrated is a data maintenance block 106 in accordance with the present
`invention for retaining DRAM memory 102 data when the logic device 104 is
`reconfigured during operation of the computer subsystem 100.
`
`Id. at 4:20-23 (emphasis added);
`
`The method comprises providing a data maintenance block coupled to the recon-
`figurable device, coupling the data maintenance block to self-refresh command in-
`puts of the DRAM memory, storing data received from the reconfigurable device
`at the data maintenance block and maintaining stable input levels on the self-
`refresh command inputs while the reconfigurable logic device is reconfigured.
`
`Id. at 3:42-49 (emphasis added).
`
`37.
`
`After the reconfigurable logic device of the ’311 patent is reconfigured, the memory
`
`controller of the reconfigurable logic device retrieves the DRAM memory data stored in the data
`
`maintenance block and writes it back to the same DRAM memory addresses that were corrupted:
`
`14
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2015. p. 15
`
`

`

`Case 2:18-cv-00317-JLR Document 115-2 Filed 11/05/18 Page 16 of 29
`
`If a reconfiguration condition is detected, and before processing incoming DMA
`requests, the controller retrieves stored DRAM data from the data maintenance
`block (again through the communication port) and writes it back to the specific
`address locations corrupted during the calibration/leveling process.
`
`
`Id. at 2:56-61 (emphasis added).
`
`
`At the operation indicated by numeral 6, the reconfigure controller 110 retrieves
`the data maintenance block 106 block RAM 114 contents and stores it in a small
`section of block RAM (not shown) in the reconfigure controller 110. The reconfig-
`ure controller 110 detects that the memory controller and physical interface 118
`and DRAM memory 102 initialization is complete at the operation indicated by
`numeral 7 and initiates DMA write requests to restore the memory contents cor-
`rupted during the calibration/leveling sequence with the data values read prior to
`reconfiguration.
`
`
`Id. at 5:27-36 (emphasis added).
`
`
`38.
`
`Therefore, a data maintenance block, as claimed in the ’311 patent, must store
`
`DRAM memory data when the reconfigurable logic device is reconfigured.
`
`39.
`
`The ’311 patent also makes clear that the data maintenance block must drive the
`
`self-refresh command inputs of DRAM memory. The ’311 patent expressly states that in the Sum-
`
`mary of the Invention: “the FPGA drives the majority of the DRAM input/out (I/O) and the data
`
`maintenance block drives the self-refresh command inputs.” Id. at 2:7-9 (emphasis added).
`
`40.
`
`As the patent describes, “[t]he data maintenance block 106 is coupled to the DRAM
`
`memory 102 to supply reset (RESET#) and clock enable (CKE#) signals thereto.” Id. at 4:52-54;
`
`see also id. at Fig. 1. It was known to one of skill in the art at the time the patent was filed that the
`
`“clock enable” signal controls whether the DRAM is in self-refresh mode. Thus, when the recon-
`
`figurable logic device is being reconfigured, the data maintenance block de-asserts the “clock en-
`
`able” signal of the DRAM. Id. at 5:12-16 (“At the operation indicated by numeral 3, the reconfig-
`
`ure controller 110 detects a refresh command from the refresh timer 116, waits a refresh cycle time
`
`(tRFC) and instructs the data maintenance block 106 to de-assert CKE to the DRAM memory
`
`15
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2015. p. 16
`
`

`

`Case 2:18-cv-00317-JLR Document 115-2 Filed 11/05/18 Page 17 of 29
`
`102.”). When the reconfiguration is complete, the data maintenance block asserts the “clock ena-
`
`ble” signal. Id. at 5:19-24 (“As indicated by the operation at numeral 5, the reconfigure controller
`
`110 recognizes a post-reconfigure condition (Ack=High), holds the memory controller and physi-
`
`cal interface 118 in reset and instructs the data maintenance block 106 to assert CKE to the DRAM
`
`memory 102.”).
`
`41.
`
`For these reasons, it is my opinion that “a data maintenance block” is properly con-
`
`strued as “a circuit separate from the memory controller that drives self-refresh command inputs
`
`and stores DRAM memory data when the reconfigurable logic device is reconfigured,” as pro-
`
`posed by Amazon.
`
`VII. OVERVIEW OF THE ’867 PATENT
`
`42.
`
`The perceived speed and efficiency of a computer system in everyday usage de-
`
`pends, in part, on the speed of its storage. But the faster the storage, the less one can have of it,
`
`and vice versa. In part this is due to cost, but also some of the fastest types of storage—such as
`
`on-chip caches—have very limited capacity. Thus, one of the evergreen problems of computer
`
`architecture is maximizing these two fundamentally opposed variables: speed and capacity.
`
`43.
`
`The solution to this problem, used in modern computer architectures, is to imple-
`
`ment a memory hierarchy. Thus, a modern computer will have a very large and very slow hard
`
`disk; a much faster, but considerably smaller RAM subsystem; and two or three levels of on-chip
`
`cache, with each level successively smaller yet closer to the computational core of the chip—and
`
`therefore faster. Each level of the hierarchy is used to duplicate a smaller and, in theory, more
`
`immediately relevant subset of the contents of the lower levels. Thus, the L1 cache (closest to the
`
`computational core) might contain only the most recently used bytes; the L2 cache might contain
`
`a larger am