Feinmetall Exhibit 2023
`FormFactor, Inc. v. Feinmetall, GmbH
`IPR2019-00082
`
`Page 1 of 7
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`FormFactor, Inc. v. Feinmetall, GmbH
`IPR2019-00082
`
`Page 1 of 7
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`
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`Copyright © 1995 by Butterworth—Heinemann.
`
`&A member of the Reed Elsevier group.
`
`All rights reserved.
`
`No part of this publication may be reproduced. stored in a retrieval system. or
`transmitted in any form or by any means, electronic, mechanicaL photocopying,
`recording. or otherwise. without the prior written permission of the publisher.
`
`@Recognizing the importance of preserving what has been written.
`
`Butterworth—Heinemann prints its books on acid-free paper whenever possible.
`
`Library of Congress Cataloging-iml’uhlieatien Data
`Afshar, Amir.
`Principles oi semiconductor network testing,l Ami: Afshar.
`p.
`cm.
`
`Includes bibliographical reierenoes and index.
`ISBN 0-?506-9472-6 (hardcover: alk. paper}
`1. Integrated circuits—Testing.
`2. Semiconductors—Testing.
`I. Title.
`I995
`TK7S‘?4.A339
`62l.38]5'43-—dc20
`
`95-13336
`ClP
`
`British Library Cataloguing-in-Puhlication Data
`A catalogue record for this book is available from the British Library.
`
`The publisher oflers discounts on bulk orders of this book.
`For information. please write:
`
`Manager of Special Sales
`Butterworth—Heinemann
`
`313 Washington Street
`Newton. MA 02158-1626
`
`[0987654321
`
`Printed in the United States of America
`
`Page 2 of 7
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`Page 2 of 7
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`Contents
`
`Foreword
`Preface
`
`xi
`xiii
`
`1 Diode and Transistor Operation 1
`Introduction
`l
`1.1 Semiconductor Materials
`
`3
`
`1.2 Bipolar Transistors
`1.3 MOS Transistors
`References
`21
`
`6
`15
`
`2
`
`Integrated Circuit Test Basics
`Introduction 23
`
`23
`
`2.1 Designing Integrated Circuits
`2.2 Silicon Wafer Production 25
`2.3 Test Limits Guardbanding 23
`2.4 Wafer Test Hardware
`31
`
`24
`
`2.5 Bonding and Packaging
`2.6 Final Test
`34
`
`34
`
`2.? Quality Assurance (QA) Test
`References
`56
`
`35
`
`3 Digital Logic Test
`Introduction
`57
`
`57
`
`3.] Continuity Test
`3.2 Shorts Test
`60
`3.3 Functional Test
`
`60
`
`61
`
`61
`ICC Test
`3.4
`62
`3.5 Breakdown Voltage (VB) Test
`3.6
`V0,, Test (High Level Output Voltage)
`3.7
`Var. Test (Low Level Output Voltage)
`3.8
`1”. Test (Low Level Input Current)
`
`64
`
`63
`63
`
`Page 3 of 7
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`Page 3 of 7
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`
`
`VIII Contents
`
`6'!
`67
`
`64
`3.9 1", Test (High Level Input Current)
`65
`3.10 IOZi-I Test (High Level Three-state Output Current)
`66
`3.11 IOZL Test (Low Level Three-state Output Current)
`3.12 for. (Saturation) Test (Low Output Saturation Current)
`3.13 10,, (Saturation) Test (High Output Saturation Current)
`3.14 Voltage Hysteresis Wars} Test
`68
`3.15 A Binary Search Algorithm 3'0
`3.16 AC Testing Description 72
`3.1? Propagation Delay Test (rpm, in”, tmz, rpm)
`3.18 Output Pulse Width (tw) Test
`24
`3.19 Rise and Fall Time Test (rmtpj
`7'5
`3.20 Setup Time Test (tsp)
`75
`3.21 Hold Time Test (is)
`75
`3.22 Removal Time (rm...) or Recovery Time (tug) Test
`3.23 Noise in Digital Circuits
`76
`References
`82
`
`‘16
`
`73
`
`4 Noise Identification 83
`Introduction 83
`
`4.1 Grounding 85
`4.2 General Guidelines for Grounding 87
`4.3 Resistor Noise
`88
`4.4
`Inductor Noise
`89
`
`90
`4.5 Capacitor Noise
`4.6
`1 /f or Flicker Noise
`4.? Shot Noise
`92
`4.8 Thermal Noise
`
`93
`
`92
`
`93
`
`4.9 Popcorn (Burst) Noise
`4.10 Contact Noise
`94
`4.11 Using Capacitors for Suppressing Noise
`4.12 Decoupling 95
`96
`4.13 Facts about Power Supplies
`4.14 Suppressing Noise Created by Capacitive Load 98
`4.15 Noise in Bipolar Transistors
`99
`References
`99
`
`95
`
`5 Operational Amplifier
`Introduction
`101
`5.1
`Ideal Behavior of an Op Amp
`5.2 Feedback Configurations
`104
`5.3 Basic 0p Amp Internal Structure
`5.4 Common Mode Signal
`108
`5.5
`Input Impedance
`110
`5.6 Singlenended Output
`5.?
`Input Bias Current (In)
`
`103
`
`104
`
`101
`
`110
`111
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`Page 4 of 7
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`
`
`114
`
`111
`Slew Rate (SR)
`5.8
`5.9 Op Amp DC Measurement (Nulling Circuit)
`5.10 VOS Test (Input Ofl‘set Voltage)
`115
`5.11 VOS Test Using Nailing Circuit
`116
`5.12 108 Test (Input Offset Current)
`11?
`118
`5.13 VON Test (Negative Output Voltage Swing)
`119
`5.14 VOP Test (Positive Output Voltage Swing)
`5.15 CMRR Test (Common Mode Rejection Ratio)
`5.16 SR Test (Slew Rate)
`121
`5.17 AV (Gain) Test
`121
`5.18 PSRR Test (Power Supply Rejection Ratio)
`5.19 Noise in Op-amp Circuits (Crosstalk)
`123
`5.20 Oscillation
`123
`5.21 Noise in Different Types of Operational Amplifiers
`5.22 The Decibel
`128
`References
`128
`
`119
`
`122
`
`Contents ht
`
`125
`
`6 Data Acquisition Devices
`Introduction
`131
`
`131
`
`Field of Application
`6.1
`6.2 Definition of Terms
`
`133
`133
`
`159
`160
`
`142
`
`6.3 Operation of a 4-Bit Converter
`6.4 Conversion Operation
`143
`145
`6.5 AD and BM Test Description
`158
`6.6
`IIH Test (Logical “1“ Input Current)
`159
`6.?
`[IL Test (Logical “0” Output Current)
`6.8
`[021. Test (Three-state Low Level Output Leakage)
`6.9
`1021-! Test (Three—state High Level Output Leakage)
`6.10 VOI-I Test (Logic “1" Output Voltage)
`160
`6.11 VOL Test (Logic “0" Output Voltage)
`161
`6.12 ICC/Inn Test (Power Supply Current)
`161
`162
`6.13 ICC+R Test (Combined ICC+R Current)
`6.14 1mm Test (Analog High on Channel Input Current)
`while Clock is On
`162
`6.15 IthOI Test (Analog Low on Channel Input Current)
`while Clock is On
`163
`6.16 IN” Test (Analog High on Channel Input Current)
`while Clock is Off
`163
`6.17 limo: Test (Analog Low on Channel Input Current)
`while Clock is Off
`163
`6.18 Functional Test
`164
`
`6.19 TmLE Test (ALE Pulse Width)
`6.20 RES Test (Resolution Test)
`165
`6.21 Nonlinearity Test
`166
`6.22 RL Test (Ladder Resistance Test)
`
`165
`
`167
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`x Contact:
`
`167
`6.23 1"”,s Test (Minimum Start Pulse Width)
`168
`6.24 T; Test (Minimum Address Setup Time)
`168
`6.25 TH Test (Minimum Address Hold Time}
`6.26 TB Test (Analog MUX Delay Time from ALE)
`6.27 Tm. 7}“, Test (0E Control to Q Logic State)
`6.28 Tm, THO Test (OE Control to High-Z)
`169
`6.29 Tc Test {Conversion Time)
`170
`6.30 Fe Test (Clock Frequency)
`170
`References
`170
`
`168
`169
`
`7 Digital Signal Processing
`Introduction
`173
`
`173
`
`175
`
`174
`7.1 Anti-aliasing Filter
`7.2 Sample-and-Hold Module
`7.3 Audio Digitizer
`175
`7.4 Function Generator and Signal Properties
`7.5 Fourier Series and Fourier Transforms
`177
`7.6 Signal Conversion
`180
`7.7 Sampling Rate
`183
`7.8 Errors
`185
`References
`187
`
`175
`
`189
`
`8 CODEC (Coder/Decoder)
`Introduction
`189
`190
`8.1
`Frame Concept
`8.2 Companding Rules in Communication
`8.3 C—Message and P-Message‘
`194
`8.4 Unit of Noise Power
`195
`8.5 Standards for CODEC 198
`198
`8.6 Device Minimum Capability
`8.7 Basic Modulations in Telecommunication
`8.8 CODEC Requirements
`199
`199
`8.9
`Introduction to CODEC Testing
`8.10 Single-tone CODEC Testing (Analog Method}
`8.11 Multitone CODEC Testing 204
`8.l2 Ftill-channel and Half-channel Tests
`8.13 I“, 1m, Test (Supply Current)
`205
`8.14 CODEC Dynamic Tests—-Encoder Section
`8.15 CODEC Dynamic Tests-‘Decoder Section
`References
`208
`
`192
`
`198
`
`200
`
`205
`
`205
`207
`
`Index
`
`209
`
`Page 6 of 7
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`Page 6 of 7
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`
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`32 PRINCIPLES OF SEMICONDUCTOR NETWORK TESTING
`
`
`
`
`Figure 2.7 The probe card of Figure 2.6. now mounted on the special automated
`machine designed for testing dies on wafers. (Courtesy oi CerProbe Corp.)
`
`Figure 2.3 A close-up View of a die undergoing electrical testing in wafer sorting stage.
`The inker is adjusted on and above the center of the die. (Courtesy of Intel Corp.)
`
`Figure 2.7 shows the probe card assemny mounted on the wafer prober. Figure
`2.8 shows a close-up of a wafer undergoing test. Note the location of the probe
`needles and also the inker at the oenter of and above the die.
`All of the DC and functional tests in the software program are applied to
`
`Page 7 of 7
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`Page 7 of 7
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