`
`DAVID A. JOHNS
`
`KEN MARTIN
`
`INTEL 1233
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`ANALOG INTEGRATED
`ClRCUIT DESIGN
`
`
`
`___—_____/__——
`
`David Johns
`
`Ken Martin
`
`University of Toronto
`
`,..—..
`
`John Wiley & Sons, Inc.
`. Brisbane
`New York
`. Chichester
`Toronto
`. Singapore
`. Weinheim
`
`2
`
`89
`
`
`
`
`
`

`

`Acquisitions Editor
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`ication Services and printed and bound
`This book was set in Times Roman by Publ
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`by R.R. Donnelley/Crawfordsville. The cover was pri
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`f preserving what has been written, it is a
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`Copyright © 1997, by John Wiley & Sons, Inc.
`
`All rights reserved. Published simultaneously in Canada.
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`Reproduction or translation of any part of
`this work beyond that permitted by Sections
`107 and 108 of the 1976 United States Copyright
`Act without the permission of the copyright
`OWner is unlawful. Requests for permission
`or further information should be addressed to
`the Permissions Department, John Wiley & Sons, Inc.
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`Library of Congress Cataloging-in-Publication Data:
`
`/ David Johns, Ken Martin.
`
`Johns, David, 1958—
`Analog integrated circuit design
`p.
`cm.
`Includes bibliographical references.
`ISBN 0-471—14448-7 (cloth '. alk. paper)
`1. Linear integrated circuits—Design and construction.
`1. Martin, Kenneth W. (Kenneth W.) 1952— . II. Title.
`TK7874.J65 1996
`96-34365
`621 .3815——dc20
`CIP
`
`
`
`ISBN 0—471-14448-7
`
`Printed in the United States of America
`
`
`
`
`1098765432
`
`

`

`
`
`Contents
`
`CHAPTER I
`
`39
`42
`
`56
`
`61
`
`96
`105
`
`
`
`129
`
`135
`
`137
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`
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`
`
`INTEGRATED-CIRCUIT DEVICES AND MODELLING
`Semiconductors and pn Junctions
`1
`1.1
`16
`1.2
`MOS Transistors
`1.3
`Advanced MOS Modelling
`1.4
`Bipolar-Junction Transistors
`1.5
`Device Model Summary
`
`1.6
`SPICE-Modelling Parameters
`1.7
`Appendix
`65
`
`1.8
`References
`7 8
`
`1.9
`Problems
`78
`
`
`
`
`
`CHAPTER 2
`PROCESSING AND LAYOUT
`82
`2.1
`CMOS Processing
`
`2.2 Bipolar Processing
`
`2.3 CMOS Layout and Design Rules
`
`2.4
`Analog Layout Considerations
`
`2.5
`Latch-Up
`1 18
`
`121
`References
`2.6
`
`2.7
`121
`Problems .
`
`
`
`
`CHAPTER 3
`BASIC CURRENT MIRRORS AND SINGLE-STAGE AMPLIFIERS
`
`125
`3.1
`Simple CMOS Current Mirror
`128
`3.2
`Common-Source Amplifier
`
`Source-Follower or Common—Drain Amplifier
`3.3
`
`132
`3.4
`Common-Gate Amplifier
`
`Source—Degenerated Current Mirrors
`3.5
`
`High-Output-Impedance Current Mirrors
`3.6
`140
`
`3.7
`Cascode Gain Stage
`
`3.8
`MOS Differential Pair and Gain Stage
`
`146
`3.9
`Bipolar Current Mirrors
`
`3.1
`0 Bipolar Gain Stages
`
`
`142
`
`.Il_a_-.fi:#-—au==:ya:
`
`
`
`149
`
`

`

`154
`Frequency Response
`3.1 1
`3.12 SPICE Simulation Examples
`3.13 References
`176
`3.14 Problems
`176
`
`169
`
`CHAPTER 4
`
`NOISE ANALYSIS AND MODELLING
`
`181
`
`Time—Domain Analysis
`4. 1
`186
`Frequency—Domain Analysis
`4.2
`4.3 Noise Models for Circuit Elements
`
`181
`
`196
`
`4.4 Noise Analysis Examples
`4.5 References
`216
`4 .6 Problems
`217
`
`204
`
`Contents
`xi
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`7.1 Using an Opamp for a Comparator
`7.2 Charge-Injection Errors
`308
`7.3 Latched Comparators
`317
`7.4 Examples of CMOS and BiCMOS Comparators
`7.5 Examples of Bipolar Comparators
`328
`7.6 References
`330
`
`7.7 Problems
`331
`
`CHAPTER 5
`
`BASIC OPAMP DESIGN AND COMPENSATION
`
`221
`
`221
`5.1 Two-Stage CMOS Opamp
`5.2 Feedback and Opamp Compensation
`5.3
`SPICE Simulation Examples
`251
`5.4 References
`252
`5.5 Problems
`253
`
`232
`
`CHAPTER 6
`
`ADVANCED CURRENT MIRRORS AND OPAMPS
`
`256
`
`6.1
`6.2
`6.3
`6.4
`6.5
`6.6
`
`256
`Advanced Current Mirrors
`266
`Folded-Cascode Opamp
`273
`Current—Mirror Opamp
`Linear Settling Time Revisited
`280
`Fully Differential Opamps
`Common-Mode Feedback Circuits
`
`278
`
`287
`
`Current-Feedback Opamps
`6.7
`SPICE Simulation Examples
`6.8
`References
`299
`6.9
`6. 10 Problems
`300
`
`291
`295
`
`CHAPTER 7
`
`COMPARATORS
`
`304
`
`304
`
`321
`
`
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`

`

`AND TRANSLINEAR CIRCUITS
`8.1
`Performance of Sample—and-Hold Circuits
`8.2 MOS Sample—and—Hold Basics
`336
`8.3
`Examples of CMOS S/H Circuits
`343
`8.4
`Bipolar and BiCMOS Sample and Holds
`8.5
`Bandgap Voltage Reference Basics
`353
`8.6
`Circuits for Bandgap References
`357
`8.7
`Translinear Gain Cell
`364
`8.8
`Translinear Multiplier
`366
`8.9
`References
`368
`8.10 Problems
`370
`
`
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`
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`DISCRETE-TIME SIGNALS
`
`373
`9.1 Overview of Some Signal Spectra
`
`9.2 Laplace Transforms of Discrete-Time Signals
`
`9.3 Z-Transform
`377
`9.4 Downsampling and Upsampling
`
`9.5 Discrete-Time Filters
`382
`
`9.6
`Sample-and—Hold Response
`
`9.7 References
`391
`
`9.8 Problems
`391
`
`
`SWITCHED-CAPACITOR CIRCUITS
`394
`
`CHAPTER I0
`
`10.1
`10.2
`10.3
`10.4
`10.5
`10.6
`10.7
`10.8
`10.9
`
`Basic Building Blocks
`Basic Operation and Analysis
`409
`First-Order Filters
`
`398
`
`415
`423
`
`427
`
`Biquad Filters
`Charge Injection
`Switched-Capacitor Gain Circuits
`Correlated Double-Sampling Techniques
`434
`Other Switched-Capacitor Circuits
`441
`References
`443
`
`10.10 Problems
`
`SAMPLE AND HOLDS, VOLTAGE REFERENCES,
`
`XII
`
`Contents
`
`CHAPTER 8
`
`334
`
`334
`
`349
`
`CHAPTER 9
`
`373
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`374
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`379
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`389
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`
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`DATA CONVERTER FUNDAMENTALS
`445
`
`
`447
`
`
`448
`
`433
`
`
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`
`
`CHAPTER I I
`
`1 1.1
`
`Ideal D/A Converter
`
`Ideal A/D Converter
`11.2
`11.3 Quantization Noise
`452
`11.4 Signed Codes
`
`
`
`
`

`

`Contents
`
`xiii
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`
`463
`
`487
`
`531
`
`1 1.5 Performance Limitations
`1 1.6 References
`461
`1 1.7 Problems
`461
`
`454
`
`CHAPTER 12
`
`NYQUIST-RATE D/A CONVERTERS
`
`12.1
`12.2
`12.3
`12.4
`12.5
`12.6
`
`463
`Decoder-Based Converters
`469
`Binary-Scaled Converters
`Thermometer-Code Converters
`
`475
`
`Hybrid Converters
`References
`484
`Problems
`484
`
`481
`
`CHAPTER 13
`
`NYQUIST-RATE A/D CONVERTERS
`
`492
`504
`
`13.1
`13.2
`13.3
`13.4
`13.5
`13.6
`13.7
`13.8
`13.9
`13.10
`13.11
`
`487
`Integrating Converters
`Successive-Approximation Converters
`Algorithmic (or Cyclic) A/D Converter
`Flash (or Parallel) Converters
`507
`Two—Step A/D Converters
`513
`Interpolating A/D Converters
`516
`519
`Folding A/D Converters
`523
`Pipelined A/D Converters
`Time—Interleaved A/D Converters
`References
`527
`Problems
`528
`
`526
`
`CHAPTER 14
`
`OVERSAMPLING CONVERTERS
`
`14.1
`14.2
`14.3
`14.4
`14.5
`14.6
`14.7
`14.8
`14.9
`14.10
`14.11
`
`Oversampling without Noise Shaping
`Oversampling with Noise Shaping
`System Architectures
`547
`551
`Digital Decimation Filters
`555
`Higher-Order Modulators
`Bandpass Oversampling Converters
`Practical Considerations
`559
`Multi-Bit Oversampling Converters
`Third-Order A/D Design Example
`References
`57 1
`Problems
`572
`
`531
`538
`
`557
`
`565
`568
`
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`CHAPTER 15 CONTINUOUS-TIME FILTERS
`
`574
`
`15.1
`15.2
`
`Introduction to Gm-C Filters
`Bipolar Transconductors
`
`575
`584
`
`
`
`

`

`xiv
`Contents
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`
`
`597
`607
`
`CMOS Transconductors Using Triode Transistors
`15.3
`CMOS Transconductors Using Active Transistors
`15.4
`BiCMOS Transconductors
`616
`15.5
`15.6 MOSFET-C Filters
`620
`15.7
`Tuning Circuitry
`626
`15.8
`Dynamic Range Performance
`15.9
`References
`643
`15.10 Problems
`645
`
`635
`
`CHAPTER 16
`
`PHASE-LOCKED LOOPS
`
`
`
`648
`16.1 Basic Loop Architecture
`16.2 PLLs with Charge-Pump Phase Comparators
`
`16.3 Voltage—Controlled Oscillators
`670
`16.4 Computer Simulation of PLLs
`680
`
`16.5 Appendix
`689
`
`16.6 References
`692
`
`16.7 Problems
`693
`
`
`648
`
`663
`
`
`
`

`

`
`
`l9
`l .2 M03 Transistors
`
`sometimes used in digital circuits, where the circle indicates that a low voltage on the
`gate turns the transistor on, as opposed to a high voltage for an n-channel transistor
`(Fig. 1.7(a)). The symbols of Fig. 1.8(d) or Fig. 1.8(e) might be used in larger circuits
`where many transistors are present, to simplify the drawing somewhat. They will not
`be used in this text.
`
`
`
`
`
`
`
`
`
`Basic Operation
`
`The basic operation of MOS transistors will be described with respect to an n-channel
`transistor. First, consider the simplified cross sections shown in Fig. 1.9, where the
`source, drain, and substrate are all connected to ground. In this case, the MOS transis-
`tor operates similarly to a capacitor. The gate acts as one plate of the capacitor, and
`the surface of the silicon, just under the thin insulating SiOz, acts as the other plate.
`If the gate voltage is very negative, as shown in Fig. 1.9(a), positive charge will
`be attracted to the channel region. Since the substrate was originally doped p', this
`negative gate voltage has the effect of simply increasing the channel doping to p”,
`
`Source
`VG << 0
`Si02
`Drain
`
`
`
`
`
`
`
`
`
`Depletion region j
`- Channel
`
`p‘ substrate
`\__T___
`
`
`
`
`
`
`
`Fig. 1.9 An n-channel MOS transistor. (a) VG << 0 , resulting in an accu-
`mulated channel (no current flow); (b) VG >> 0, and the channel is present
`(current flow possible From drain to source).
`
`(b)
`
`

`

`20
`
`Chapter 1
`
`0 Integrated-Circuit Devices and Modelling
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`resulting in what is called an accumulated channel. The n+ source and drain regions
`are separated from the p+-channel region by depletion regions, resulting in the equiva-
`lent circuit of two back-to-back diodes. Thus, only leakage current will flow even if
`one of the source or drain voltages becomes large (unless the drain voltage becomes
`so large as to cause the transistor to break down).
`In the case of a positive voltage being applied to the gate, the opposite situation
`occurs, as shown in Fig. 1.9(b). For small positive gate voltages, the positive carriers
`in the channel under the gate are initially repulsed and the channel changes from a p—
`doping level to a depletion region. As a more positive gate voltage is applied, the gate
`attracts negative charge from the source and drain regions, and the channel becomes
`an n region with mobile electrons connecting the drain and source regions.5 In short, a
`sufficiently large positive gate-source voltage changes the channel beneath the gate to
`an n region, and the channel is said to be inverted.
`The gate-source voltage, for which the concentration of electrons under the gate
`is equal to the concentration of holes in the p’ substrate far from the gate, is com—
`monly referred to as the transistor threshold voltage and denoted th (for n-channel
`transistors). For gate-source voltages larger than th, there is an n—type channel
`present, and conduction between the drain and the source can occur. For gate—source
`voltages less than th, it is normally assumed that the transistor is off and no current
`flows between the drain and the source. However, it should be noted that this assump-
`tion of zero drain—source current for a transistor that is off is only an approximation. In
`fact, for gate voltages around th, there is no abrupt current change, and for gate-
`source voltages slightly less than th, small amounts of subthreshold current can
`flow, as discussed in Section 1.3.
`When the gate-source voltage, VGS , is larger than Vm, the channel is present. As
`VGS is increased, the density of electrons in the channel increases. Indeed, the carrier
`density, and therefore the charge density, is proportional to VGS — Vm, which is often
`called the efi‘ective gate-source voltage and denoted Vefl. Specifically, define
`
`Veff E Ves ‘th
`
`The charge density of electrons is then given by
`
`On = Cox(Ves — th) = Coxvelf
`
`Here, Cox is the gate capacitance per unit area and is given by
`
`Cox = K°XE°
`tox
`
`(1-54)
`
`(155)
`
`(1.56)
`
`where K0)( is the relative permittivity of Si02 (approximately 3.9) and tOX is the
`thickness of the thin oxide under the gate. A point to note here is that (1.55) is only
`accurate when both the drain and the source voltages are zero.
`
`_____’____———————
`
`5. The drain and source regions are sometimes called diffusion regions or junctions for historical reasons.
`This use of the word junction is not synonymous with our previous use, in which it designated a pn inter-
`face of a diode.
`
`
`
`

`

`1.2 M05 Transistors
`
`21
`
`C95 = WLCOX
`
`and the total charge of the channel, QT_n, is given by
`
`QT-n = WLCOX(VGS_th) = WLCOXVeif
`
`(1.57)
`
`(1.58)
`
`
`
`To obtain the total gate capacitance, (1.56) should be multiplied by the effective
`gate area, WL, where W is the gate width and L is the effective gate length. These
`
`dimensions are shown in Fig. 1.10. Thus the total gate capacitance, 095, is given by
`
`
`
`
`
`
`
`The gate capacitance, Cgs , is one of the major load capacitances that circuits must be
`capable of driving. Gate capacitances are also important when one is calculating
`charge injection, which occurs when a MOS transistor is being turned off because the
`channel charge, QM, must flow from under the gate out through the terminals to
`other places in the circuit.
`Next, if the drain voltage is increased above 0 V, a drain-source potential differ-
`ence exists. This difference results in current flowing from the drain to the source.6
`The relationship between VDs and the drain-source current, ID, is the same as for a
`resistor, assuming VDs is small. This relationship is given [Sze, 1981] by
`W
`1D = unQnEVDS
`
`(1.59)
`
`where un E 0.06 mZ/Vs is the mobility of electrons near the silicon surface, and On
`is the charge concentration of the channel per unit area (looking from the top down).
`Note that as the channel length increases, the drain—source current decreases, whereas
`this current increases as either the charge density or the transistor width increases.
`Using (1.58) and (1.59) results in
`W
`W
`ID = unCox-L_(VGS’th)VDS = ”noovaethDS
`
`(1'60)
`
`sao2
`
`/
`
`n channel
`
`Fig. 1.10 The important dimensions of 0 MOS transistor.
`
`6. The current is actually conducted by negative carriers (electrons) flowing from the source to the drain.
`Negative carriers flowing from source to drain results in a positive current from drain to source, IDS .
`
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`

`

`
`
`22
`
`Chapter 1
`
`0 Integrated-Circuit Devices and Modelling
`
`where it should be emphasized that this relationship is only valid for drain—source
`voltages near zero (i.e., VDS much smaller than Vefi ).
`As the drain-source voltage increases, the channel charge concentration decreases
`at the drain end. This decrease is due to the smaller gate-to-channel voltage difference
`across the thin gate oxide as one moves closer to the drain. In other words, since the
`drain voltage is assumed to be at a higher voltage than the source, there is an increasing
`voltage gradient from the source to the drain, resulting in a smaller gate-to-channel
`voltage near the drain. Since the charge density at a distance X from the source end of
`the channel
`is proportional to VG — Vcn(X) — Vm, as VG — Vch(x) decreases,
`the
`charge density also decreases.7 This effect is illustrated in Fig. 1.11.
`Note that at the drain end of the channel, we have
`
`VG_VCh(L) = VGD
`
`(1.61)
`
`For small VDS, we saw from (1.60) that ID was linearly related to VDS. However, as
`VDs increases, and the charge density decreases near the drain, the relationship
`becomes nonlinear. In fact, the linear relationship for ID versus VDS flattens for larger
`
`VDS, as shown in Fig. 1.12.
`
`
`
`I.
`
`Increasingx Qn(l-) = Cox(VGD—Vin)
`
`Qn(x) = Cox(VGS‘Vch(x)_th)
`
`Fig. 1.11 The channel charge density for VDS > 0.
`W
`ID < HnCox‘EWes—VmWDs
`
`1,
`
`
`
`If
`ID = “n00 \‘l'vWas— th)VDS
`x L
`
`VDs
`
`For VDS not close to zero, the
`Fig. 1.12
`ID versus VDS relationship is no longer
`linear.
`
`is the gate-to—channel voltage drop at distance x from the source end, with VG being the
`7. VG — VCH(X)
`same everywhere in the gate, since the gate material is highly conductive.
`
`
`
`
`
`

`

`1,2 MOS Transistors
`
`23
`
`As the drain voltage is increased, at some point the gate-to-channel voltage at the
`drain end will decrease to the threshold value Vm—the minimum gate—to-channel
`voltage needed for n carriers in the channel to exist. Thus, at the drain end, the chan—
`nel becomes pinched ofi‘, as shown in Fig. 1.13. This pinch-off occurs at VGD = th,
`since the channel voltage at the drain end is simply equal to VD. Thus, pinch-off
`occurs for
`
`vDG > —vm
`
`(1.62)
`
`Denoting VDS-sat as the drain-source voltage when the channel becomes pinched off,
`we can substitute VDG = V05 ‘V68 into (1.62) and find an equivalent pinch-off
`expression
`
`VDs > Vpsw
`
`where VDS-sat is given8 by
`
`VDS-sat = VGs—th = Veff
`
`(1.63)
`
`(164)
`
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`, The electron carriers travelling through the pinched-off drain region are velocity
`saturated, similar to a gas under pressure travelling through a very small tube. If the
`drain—gate voltage rises above this critical pinch-off voltage of —Vtn , the charge con-
`centration in the channel remains constant (to a first-order approximation) and the
`drain current no longer increases with increasing VDS. The result is the current-
`voltage relationship shown in Fig. 1.14 for a given gate—source voltage. In the region
`of operation where VDS > VDS-sat , the drain current is independent of VDs and is
`called the active region.9 The region where ID changes with VDS is called the triode
`region. When MOS transistors are used in analog amplifiers, they almost always are
`biased in the active region. When they are used in digital logic gates, they often oper-
`ate in both regions.
`
`V820
`
`'.
`
`_.
`
`Depletion region‘L—I
`
`
`_
`
`»
`
`I
`
`l'
`in
`
`n
`
`VG >> Vm
`
`
`
`{/
`
`Pinch—off for
`VGD < th
`
`
`
`Fig. 1.13 When VDS is increased so that VGD < Vm, the chonnei becomes pinched oil at the drain end.
`
`
`
`
`
`
`
`
`
`8. Because of the body effect, the threshold voltage at the drain end of the transistor is increased, resulting
`in the true value of V033“ being slightly lower than V9" .
`9. Historically, the active region was called the saturation region, but this led to confusion because in the
`case of bipolar transistors, the saturation region occurs for small VCE , whereas for MOS transistors it
`occurs for large VDs- The renaming of the saturation region to the active region is becoming widely
`accepted.
`
`

`

` 24
`
`Chapter 1
`
`C integrated-Circuit Devices and Modelling
`2
`
`W
`V
`ID = linCoxf[(VGs — th)VDS ‘ %]
`
`ID =
`
`
`llnCoxW
`2 ITO/GS ‘ th)2
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`In
`
`'---.-m__v__~~__-
`
`.’ LH—i VGS constant
`
`.f”
`
`:
`.
`'
`
`Active
`reglon
`
`f
`//. Triode
`/
`region
`_/
`
`3"-
`IW
`VDS-sat = Vett
`ID 5 llnCoxtWGs * th)VDS
`
`VDS
`
`ID versus VDS curve for an ideal MOS transistor. For
`Fig. 1.14 The
`VDs > VDS_sat , ID is approximately constant.
`
`Before proceeding, it is worth discussing the terms weak, moderate, and strong
`inversion. As just discussed, a gate—source voltage greater than th results in an
`inverted channel, and drain—source current can flow. However, as the gate—source
`voltage is increased, the channel does not become inverted (i.e., n-region) suddenly,
`but rather gradually. Thus, it is useful to define three regions of channel inversion
`with respect to the gate-source voltage. In most circuit applications, noncutoff MOS-
`FET transistors are operated in strong inversion, with Veff > 100 mV (many prudent
`circuit designers use a minimum value of 200 mV). As the name suggests, strong
`inversion occurs when the channel is strongly inverted. It should be noted that all the
`equation models in this section assume strong inversion operation. Weak inversion
`occurs when VGS is approximately 100 mV or more below Vtn and is discussed as
`subthreshold operation in Section 1.3. Finally, moderate inversion is the region
`between weak and strong inversion.
`
`
`
`
`
`
`
`
`Large-Signal Modelling
`
`The triode region equation for a MOS transistor relates the drain current to the gate—
`source and drain-source voltages. It can be shown (see Appendix) that this relation-
`ship is given by
`
`ID = uncox[f]l(vGS — th)VDS _ _2
`
`W
`
`Vés
`
`(165)
`
`As VDS increases, ID increases until the drain end of the channel becomes pinched off,
`and then ID no longer increases. This pinch-off occurs for VDG = —Vm, or approxi-
`mately,
`
`VDS = VGS — th = Veff
`
`(1-66)
`
`Right at the edge of pinch-off, the drain current resulting from (1.65) and the drain
`current in the active region (which, to a first-order approximation, is constant with
`
`
`
`

`

`respect to VDS) must have the same value. Therefore, the active region equation can
`be found by substituting (1.66) into (1.65), resulting in
` u C x W
`
`ID =
`
`"2° [t](VGS_th)2
`
`1.2 M03 Transistors
`
`25
`
`(1'67)
`
`For 'VDs > V9”, the current stays constant at the value given by (1.67), ignoring
`second-order effects such as the finite output impedance of the transistor. This equation
`is perhaps the most important one that describes the large-signal operation of a MOS
`transistor. It should be noted here that (1.67) represents a squared current-voltage
`relationship for a MOS transistor in the active region. In the case of a B]T transistor, an
`exponential current-voltage relationship exists in the active region.
`As just mentioned, (1.67) implies that the drain current, ID, is independent of the
`drain-source voltage. This independence is only true to a first-order approximation.
`The major source of error is due to the channel length shrinking as VDS increases. To
`see this effect, consider Fig. 1.15, which shows a cross section of a transistor in the
`active region. A pinched-off region with very little charge exists between the drain and
`the channel. The voltage at the end of the channel closest to the drain is fixed at
`VGS — Vtn = Vefl. The voltage difference between the drain and the near end of the
`channel lies across a short depletion region often called the pinch-0]? region. As VDS
`becomes larger than Veff ,
`this depletion region surrounding the drain junction
`increases its width in a square-root relationship with respect to VDS. This increase in
`the width of the depletion region surrounding the drain junction decreases the effective
`channel length. In turn, this decrease in effective channel length increases the drain
`current, resulting in what is commonly referred to as channel-length modulation.
`To derive an equation to account for channel-length modulation, we first make
`use of (1.11) and denote the width of the depletion region by Xd, resulting in
`
`where
`
`Xd 5 deA/VD-ch + q’0
`
`kds _
`#
`
`
`|I2KS€0
`'l'rl q N A
`
`VGs > Vin
`
`(1.68)
`
`1.69
`
`)
`
`(
`
`
`
`Depletion region
`
`AL °< VDS — Veff + (Do
`
`Pinch-off region
`
`Fig. 1.15 Channel length shortening for VDS > Veff.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`

`

` 26
`
`Chapter 1
`
`0 Integrated-Circuit Devices and Modelling
`
`and has units of rim/V. Note that N A is used here since the n—type drain region is
`more heavily doped than the p—type channel (i.e., ND >> N A). By writing a Taylor
`approximation for ID around its operating value of VDs = VGS — th = Veff, we
`find ID to be given by
`
`ID = ID-sat+ a—LD
`
`31
`
`
`BL
`
`aVDs
`
`)AVDS E ID-saJl
`
`(v _v )
`k
`+——
`2L Noe. + Vtn + (DO
`
`d8
`
`D8
`
`e”
`
`J
`
`(1-70)
`
`where 10.5,“ is the drain current when VDS = Ve" , or equivalently, the drain current
`when the channel-length modulation is ignored. Note that in deriving the final equa-
`tion of (1.70), we have used the relationship BL/BVDS = —8Xd/3VDS. Usually,
`(1.70) is written as
`
`
`= HnCox
`2
`
`Io
`
`W[IJEVGs—mell +7L(VDS‘Veff)]
`
`where 71. is the output impedance constant (in units of V") given by
`
`kds
`k
`x = __"5____ = —___
`L./VDG+Vm+(I)0
`2L./VDS—Veff+tl)0
`
`(1-7\1)
`
`(1.72)
`
`Equation (1.71) is accurate until VDs is large enough to cause second-order effects,
`often called short-channel eflects. For example, (1.71) assumes that current flow
`down the channel is not velocity-saturated (i.e., increasing the electric field no longer
`increases the carrier speed). Velocity saturation commonly occurs in new technolo—
`gies that have very short channel lengths and therefore large electric fields. If VDS
`becomes large enough so short-channel effects occur, ID increases more than is pre-
`dicted by (1.71). Of course, for quite large values of VDS, the transistor will eventu-
`ally break down.
`A plot of ID versus Vos for different values of VGS is shown in Fig. 1.16. Note
`that in the active region, the small (but nonzero) slope indicates the small dependence
`Of ID on VD S .
`
`D
`
`I
`
`Vos = (VGS ‘ Vin)
`
`riode
`region
`
`.
`'
`
`'
`Active
`region
`
`. T
`
`Short-channel
`effects
`
`Tlncreasing VGS
`
`VGS > th
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Fig. 1.16 ID versus Vos for different values of Ves-
`
`
`
`