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`v-
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`’V
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`Circuits, Vol. 43, Issue 12, December 2008.
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`S. Jeon et al., "A Scalable 6-to-l8 GHz Concurrent Dual-Band Quad-
`Beam Phased-Array Receiver in CMOS”, IEEE Journal of Solid-State
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`Array Receiver in CMOS” was published in IEEE Journal of Solid-State Circuits,
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`Vol. 43, Issue 12. IEEE Journal of Solid-State Circuits, Vol. 43, Issue 12 was
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`ii
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`(cid:4)(cid:100)(cid:100)(cid:4)(cid:18)(cid:44)(cid:68)(cid:28)(cid:69)(cid:100)(cid:3)(cid:4)(cid:3)
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`ATTACHMENT A
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`5/23/2018
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`Abstract:
`This paper reports a 6-to-18 GHz integrated phased- array receiver implemented in 130-nm CMOS. The receiver is easily scalable to build a very
`large-scale phased-array system. It concurrently forms four independent beams at two different frequencies from 6 to 18 GHz. The nominal
`conversion gain of the receiver ranges from 16 to 24 dB over the entire band while the worst-case cross-band and cross-polarization rejections are
`achieved 48 dB and 63 dB, respectively. Phase shifting is performed in the LO path by a digital phase rotator with the worst-case RMS phase error
`and amplitude variation of 0.5deg and 0.4 dB, respectively, over the entire band. A four-element phased-array receiver system is implemented
`based on four receiver chips. The measured array patterns agree well with the theoretical ones with a peak-to-null ratio of over 21.5 dB.
`
`Published in: IEEE Journal of Solid-State Circuits ( Volume: 43, Issue: 12, Dec. 2008 )
`
`Page(s): 2660 - 2673
`
` INSPEC Accession Number: 10416766
`
`Date of Publication: 12 December 2008
`
`DOI: 10.1109/JSSC.2008.2004863
`
` ISSN Information:
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`Publisher: IEEE
`
`Sponsored by: IEEE Solid-State Circuits Society
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`I. Introduction
`Phased arrays steer the beam direction electronically, bringing many benefits such as high
`directivity, interference rejection, signal-to-noise ratio improvement, and fast scanning response
`[1]–[4]. for this reason, phased arrays have been extensively employed in radar and
`communication systems in the area of military, space, and radio astronomy since their advent in the
`1950s [5], [6]. Recently, substantial attention is also drawn in civil applications including high-speed
`point-to-point communications and car radars [4], [7].
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`2660
`
`IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 12, DECEMBER 2008
`
`A Scalable 6-to-18 GHz Concurrent Dual-Band
`Quad-Beam Phased-Array Receiver in CMOS
`
`Sanggeun Jeon, Member, IEEE, Yu-Jiu Wang, Student Member, IEEE, Hua Wang,
`Florian Bohn, Student Member, IEEE, Arun Natarajan, Aydin Babakhani, Member, IEEE, and
`Ali Hajimiri, Member, IEEE
`
`Abstract—This paper reports a 6-to-18 GHz integrated phased-
`array receiver implemented in 130-nm CMOS. The receiver is
`easily scalable to build a very large-scale phased-array system.
`It concurrently forms four independent beams at two different
`frequencies from 6 to 18 GHz. The nominal conversion gain
`of the receiver ranges from 16 to 24 dB over the entire band
`while the worst-case cross-band and cross-polarization rejections
`are achieved 48 dB and 63 dB, respectively. Phase shifting is
`performed in the LO path by a digital phase rotator with the
`worst-case RMS phase error and amplitude variation of 0.5
`and 0.4 dB, respectively, over the entire band. A four-element
`phased-array receiver system is implemented based on four re-
`ceiver chips. The measured array patterns agree well with the
`theoretical ones with a peak-to-null ratio of over 21.5 dB.
`Index Terms—CMOS, concurrent, large-scale phased arrays,
`multi-band, multi-beam, phased arrays, scalable, tritave.
`
`I. INTRODUCTION
`
`P HASED arrays steer the beam direction electronically,
`
`bringing many benefits such as high directivity, inter-
`ference rejection, signal-to-noise ratio improvement, and fast
`scanning response [1]–[4]. For this reason, phased arrays have
`been extensively employed in radar and communication sys-
`tems in the area of military, space, and radio astronomy since
`their advent in the 1950s [5], [6]. Recently, substantial atten-
`tion is also drawn in civil applications including high-speed
`point-to-point communications and car radars [4], [7].
`Benefits of phased arrays increase with the number of ele-
`ments combined in the array. This gives rise to the desire to
`make very large-scale phased arrays (up to 10 elements) for
`high-precision radars, long-range sensors, or high-directivity
`communication systems. One of the major obstacles in imple-
`menting large-scale phased arrays lies in the high complexity
`and cost to assemble the whole array system. Traditionally,
`phased-array systems have been built using a module-based
`approach. Most
`transmitter/receiver components, such as
`
`Manuscript received April 17, 2008; revised June 24, 2008. Current version
`published December 10, 2008. This work was supported by the Office of Naval
`Research under Contract N00014-04-C-0588.
`S. Jeon is with the School of Electrical Engineering, Korea University,
`Seongbuk-gu, Seoul, Korea (e-mail: sgjeon@korea.ac.kr).
`Y.-J. Wang, H. Wang, F. Bohn, A. Babakhani, and A. Hajimiri are with
`the Department of Electrical Engineering, California Institute of Technology,
`Pasadena, CA 91125 USA.
`A. Natarajan is with the IBM T. J. Watson Research Center, Yorktown
`Heights, NY 10598 USA.
`Digital Object Identifier 10.1109/JSSC.2008.2004863
`
`low-noise amplifiers (LNAs), power amplifiers, phase shifters,
`attenuators, filters, mixers, and LO sources, are implemented
`in separate modules and then interconnected to each other
`externally [3], [6]. This approach not only increases the as-
`sembly size and cost, but also degrades the system reliability
`due to the complicated configuration. Furthermore, several
`transmit/receive module components have been implemented
`using expensive compound semiconductors such as GaAs,
`which takes a substantial portion of the overall system cost [6],
`[8]. Thus, the size of phased arrays has been limited to a certain
`number of elements (10 or 10 at most), making it difficult to
`take full advantage of very large-scale array systems.
`Integrated CMOS solutions offer an opportunity for dramatic
`reduction in cost and size of such systems. The high yield and
`repeatability of silicon ICs allows the entire transmitter and/or
`receiver to be integrated on a single chip. For example, there
`have been reported a CMOS RF front-end [9], a fully integrated
`Si-based phased-array receiver [10] and a CMOS phased-array
`transmitter [11], all at 24 GHz and a fully integrated Si-based
`phased-array transceiver at 77 GHz [12]. This single-chip ap-
`proach in silicon reduces the overall system cost substantially,
`compared to the conventional module-based counterpart in
`compound semiconductors.
`There is a trend in radar and communication systems that the
`transceiver operates concurrently in multiple modes and mul-
`tiple bands [13]. Furthermore, many applications require the
`transceiver to operate in a wide range of RF frequencies [14].
`These trends also apply to phased arrays when multiple tar-
`gets must be tracked at the same time in radars and electronic
`countermeasure systems or when multi-point communications
`are desired at multiple frequencies in a wide bandwidth. The
`high integration capability of CMOS offers a promising solu-
`tion to achieve the wideband phased arrays with multiple func-
`tionalities. Several wideband phased (or timed) array receivers
`[15], [16] and transceiver [17] have been reported in silicon.
`However, none of the previous work has implemented a con-
`current multi-band multi-beam phased-array receiver operating
`in a wide range of RF frequencies.
`In this work, we integrated RF front-end components of a
`concurrent dual-band quad-beam phased-array receiver ele-
`ment on a single CMOS chip. The receiver is programmable to
`concurrently receive two RF frequencies between 6 and 18 GHz
`(a tritave) while forming four independently-controlled beams
`with separate phase shifting operation. The receiver is also
`easily scalable toward very large-scale phased arrays because
`additional receiver chips can be added to increase the number
`
`0018-9200/$25.00 © 2008 IEEE
`
`

`

`JEON et al.: SCALABLE 6-TO-18 GHz CONCURRENT DUAL-BAND QUAD-BEAM PHASED-ARRAY RECEIVER IN CMOS
`
`2661
`
`gain than a single element receiver. When the signals are com-
`bined in the amplitude domain (current or voltage) with a same
`output load, the array gain is given by
`
`(3)
`
`is the
`is the gain of each single element and
`where
`number of array elements. Again, undesired signals such as the
`interference or jammers arriving at other incident angles are in-
`herently rejected according to the established array pattern.
`Furthermore, the signal integrity is enhanced at the array
`output
`through an effective improvement of
`the output
`.
`signal-to-noise ratio (SNR) by a factor of
`This is because noise generated from each element is uncor-
`related with one another while the desired signal is combined
`coherently [10].
`Finally, since phase arrays steer the beam direction electron-
`ically, it is able to receive multiple beams arriving at different
`incident angles simultaneously. Also, the beam can be steered
`in a faster and more reliable way than that of a mechanically
`steered antenna system.
`
`C. Large-Scale Phased-Array System
`
`The benefits of phased arrays given in Section II-B are more
`noticeable as we increase the number of array elements. For in-
`stance, if we combine the signals from one million
`el-
`ements without any loss and phase distortion, then the array
`gain given in (3) and the output SNR will be improved by a
`factor of 120 dB and 60 dB, respectively. Although the improve-
`ment factor will be degraded in a practical array system due to
`the non-ideal signal distribution and combining, it will enhance
`the sensitivity of the receiver to a substantial degree. The capa-
`bility of rejecting undesired signals will also be reinforced with
`a larger number of elements because the main beam narrows
`and a more number of null positions are presented in the array
`pattern.
`In spite of the apparent advantages of large-scale phased ar-
`rays, their applications have been limited due to several dif-
`ficulties, mainly, the prohibitive complexity and cost. Fig. 2
`shows one of the conventional ways of building a large-scale
`phased-array receiver system. In order to combine a very large
`number of elements efficiently, several elements are grouped to-
`gether into a sub-array, and then several sub-arrays are com-
`bined by a RF distribution network to present a single output
`for down-conversion. It is noteworthy that for active phased ar-
`rays [1], every single element contains an independent receiver
`module which includes a filter, a LNA, a phase shifter, and an
`attenuator. Usually, these receiver components are implemented
`in separate chips or packages, interconnected to each other, and
`then assembled into a sub-array system by external transmission
`lines such as microstrips, cables, or waveguides. Therefore, as
`the number of array elements increases, the cost and complexity
`will also rise dramatically to assemble these components into a
`system. Furthermore, the design of the low-loss RF distribution
`network will be challenging with a large number of elements
`for two reasons. The first reason is that the number of sub-ar-
`rays is also increased accordingly, which requires more depth
`of the signal distribution (or combining) network. The other is
`
`Fig. 1. Basic phased-array receiver configuration.
`
`of array elements with relatively lower cost and complexity. To
`the authors’ best knowledge, this is the first reported concurrent
`tritave phased-array receiver implemented in CMOS.
`The paper is organized as follows. Section II briefly reviews
`phased arrays and a conventional approach to implement large-
`scale phased arrays. Section III presents a proposed concurrent
`array system architecture as well as the associated advantages.
`In Section IV, the architecture and frequency plan of the CMOS
`phased-array receiver chip is described. Section V presents the
`detailed circuit block design. Section VI provides the exper-
`imental results of the receiver chip and a four-element array
`system that combines four receiver chips.
`
`II. PHASED ARRAYS
`
`A. Overview
`
`Phased-array receivers consist of multiple antenna elements
`and a following separate
`spaced with a certain distance
`phase shifter per each element for the electronic beamforming
`in space (Fig. 1). When a RF wave
`at a given incident angle
`arrives at the antenna elements, the arrival time of wavefront is
`different between two adjacent elements by
`
`(1)
`
`where
`is the speed of light. In the narrowband circumstances,
`the arrival time difference results in a phase delay of the received
`signal between two adjacent elements, given by
`
`(2)
`
`is the wavelength of the incoming wave. Thus, the fol-
`where
`lowing phase shifter adjusts the phase delay in such a way that
`output signals from each element are all in-phase with one an-
`other. By summing the signals from each element, a coherent
`output signal can be obtained with a large array gain. On the
`other hand, other incoming waves at different incident angles
`will not be summed coherently and thus will be significantly at-
`tenuated at the array output.
`
`B. Benefits of Phased Array
`
`Since a phased array combines several in-phase signals co-
`herently at the array output, it can achieve an effectively higher
`
`

`

`2662
`
`IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 12, DECEMBER 2008
`
`Fig. 2. A conventional way of building a large-scale phased-array receiver
`system (in the active array configuration) that supports multiple beams.
`
`Fig. 3. A proposed 6–18 GHz phased-array receiver system that receives four
`beams at two frequencies concurrently and is easily scalable toward a very large-
`scale array.
`
`that the signal is distributed (or combined) in the RF domain
`before down-conversion, which gives rise to higher loss than if
`the distribution (or combining) were to be performed in the IF
`or baseband domain.
`Another challenge in large-scale phased arrays is the high
`cost of active circuit components, most of which are fabricated
`usually in expensive compound semiconductors such GaAs.
`Although the cost of monolithic microwave integrated circuits
`(MMICs) in GaAs decreased recently due to the process matu-
`rity, it still takes a large portion of the total array system cost
`[6], [8], making a very large-scale array practically difficult to
`implement.
`Even more challenge arises when the array must receive mul-
`tiple beams at the same time. Since each beam requires a sep-
`arate receiver module and a distribution network for the inde-
`pendent beamforming capability, the associated complexity and
`cost will be further exacerbated.
`
`III. PROPOSED LARGE-SCALE PHASED-ARRAY
`SYSTEM ARCHITECTURE
`To deal with the challenges discussed in Section II-C, we pro-
`pose an efficient way of building large-scale phased-array re-
`ceiver systems, as shown in Fig. 3. With a single CMOS chip (a
`shaded block in Fig. 3), we integrate all receiver module com-
`ponents on the same die except for the antenna and front-end
`LNA. The CMOS receiver includes the tunable concurrent am-
`plifiers (TCAs), down-conversion mixers, phase shifters, fre-
`quency synthesizers, and baseband buffers [18]. This integrated
`solution avoids the costly large number of separate component
`modules and their complicated interconnection for large-scale
`arrays, which results in a dramatic cost reduction. More impor-
`tantly, the chip is implemented in CMOS, which will bring an-
`other substantial cost reduction compared with its compound-
`semiconductor counterpart.
`The CMOS receiver has two input ports to receive two dif-
`ferent polarization signals fed from an active antenna module,
`i.e., horizontal polarization (HP) and vertical polarization (VP),
`
`respectively. On the other hand, each input port is able to re-
`ceive a dual-band signal containing two different frequencies
`concurrently, one in the low band (LB) from 6 to 10.4 GHz
`and the other in the high band (HB) from 10.4 to 18 GHz. The
`dual-band signal is then split into two separate signals on-chip,
`one for each band. Subsequently, each signal is down-converted
`with the independent phase-shifting operation to provide sep-
`arate beamforming. Therefore, the proposed array system can
`receive and steer four different beams at two different frequen-
`cies concurrently.
`The baseband outputs from each array element are combined
`off-chip in the current domain, providing the back-end proces-
`sors with one combined baseband signal per beam. Since the
`signal combining is performed at the baseband rather than the
`RF frequency, it alleviates the difficulty in designing a low-loss
`combining network for large-scale arrays.
`It is also noteworthy that the only feed signal which needs
`to be distributed among the elements other than DC supplies is
`a 50 MHz reference signal for on-chip frequency synthesizers.
`Due to its low frequency, the reference can be simply distributed
`without adding extra complexity. It also makes the proposed
`array architecture easily scalable.
`The LO signals generated by the on-chip frequency synthe-
`sizers may have relatively higher phase noise than those pro-
`vided by off-chip low-noise sources. However, when combining
`elements (or
`chips) in the array, the phase noise origi-
`nating from the on-chip components of each element is uncor-
`related with one another and thus adds up in power. On the
`other hand, the carrier signal is combined in amplitude in the
`current domain. Therefore, the phase-noise performance at the
`as long
`array output improves by a factor of
`as the phase noise is dominated by on-chip sources, not by an
`off-chip reference signal. This improvement also makes the in-
`tegrated solution including on-chip frequency synthesizers suit-
`able for large-scale phased arrays without degrading the array
`performance.
`
`

`

`JEON et al.: SCALABLE 6-TO-18 GHz CONCURRENT DUAL-BAND QUAD-BEAM PHASED-ARRAY RECEIVER IN CMOS
`
`2663
`
`Fig. 4. Architecture of the tunable concurrent dual-band quad-beam phased-array receiver in CMOS.
`
`In the complete array system, a separate active antenna
`module, consisting of a broadband antenna and a GaN LNA,
`will be employed in front of the CMOS receiver.
`
`IV. CMOS PHASED-ARRAY RECEIVER ELEMENT
`In this section, the architecture and frequency plan of the
`CMOS concurrent phased-array receiver element is discussed
`in detail. It should be noted that a single receiver chip operates
`as one receiver element in the array system, as shown in Fig. 3.
`
`A. Receiver Architecture
`A block diagram of the receiver architecture is presented in
`Fig. 4. Since it is a concurrent dual-band receiver, the incoming
`RF signal contains two frequencies at LB and HB respectively,
`and feeds a front-end tunable concurrent amplifier (TCA). The
`TCA amplifies, filters, and finally splits the RF signal into two
`separate outputs; one at LB and the other at HB. Each of the
`two signals goes through separate double down-conversion by
`subsequent RF and IF mixers. The IF mixers generate the and
`components of the baseband signal for digital demodulation
`capability. The baseband VGAs adjust the baseband amplitude
`and drive the output load differentially.
`There are two sets of RF input (HP RF input and VP RF input
`in Fig. 4) which are down-converted by two same sets of the
`RF signal-path circuitry, respectively. Therefore, the receiver
`presents a total of eight differential baseband outputs, one for
`each combination of two different polarizations (HP and VP),
`.
`two different frequency bands (LB and HB), and and
`
`The receiver includes two on-chip programmable frequency
`synthesizers in order to support the separate down-conversion
`of the LB and HB signals, respectively. The frequency synthe-
`sizers generate the first LO LO signal between 5–7 GHz for
`LB and between 9–12 GHz for HB with a frequency step of
`200 MHz. The LO signal drives the RF mixers for two po-
`larizations. The second LO LO signal, driving the phase ro-
`tators and IF mixers, is generated by three static divide-by-2
`dividers and a 2:1 multiplexer. According to the receiver fre-
`quency scheme discussed in Section IV-B, the LO frequency
`is selected as either one half or one eighth of the LO frequency
`and
`com-
`by the multiplexer. The LO signal carries the
`ponents separately to feed the phase rotators in quadrature. A
`50 MHz reference signal for the phase-locked loops (PLLs) is
`generated by an off-chip crystal oscillator.
`The LO phase-shifting architecture is adopted in this phased-
`array receiver in order to circumvent the challenge of designing
`high-resolution wideband phase shifters in the RF signal path
`[19]. The phase shifting is performed in the LO signal by a
`10-bit digital phase rotator. Each IF mixer is driven by a separate
`phase rotator to maximize the flexibility of the receiver. This
`not only provides the independent beamforming capability to
`the signals of different bands and polarizations, but also helps
`and mismatch of the quadrature baseband
`to minimize the
`outputs.
`The receiver includes an on-chip digital serial-bus control
`unit that programs 170 bits to configure the dual RF frequen-
`cies, LO frequencies, phase-shifting angles, baseband gains, and
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`Fig. 5. Frequency scheme.
`
`Fig. 6. Schematic of the TCA with a single input and a dual output.
`
`other functionalities of the receiver. Bias voltages are generated
`by on-chip bandgap reference circuitry.
`
`B. Receiver Frequency Scheme
`The receiver supports a concurrent dual-band RF signal, such
`that two receive frequencies are tunable simultaneously and in-
`dependently, one from 6 to 10.4 GHz (LB) and the other from
`10.4 to 18 GHz (HB). As shown in Fig. 5, each band is further
`divided into two sub-bands depending on the corresponding IF
`frequency. Accordingly, the LO frequency switches between
`1/2 and 1/8 of the LO frequency. For instance, a RF signal be-
`tween 5.625–7.875 GHz is down-converted to the IF between
`0.625–0.875 GHz by the LO between 5–7 GHz. The LO is
`then selected as 1/8 of LO to down-convert the IF to the base-
`band. On the other hand, for a RF signal between 7.5–10.5 GHz,
`the LO is selected as 1/2 of LO to down-convert the IF be-
`tween 2.5–3.5 GHz to the baseband. In this way, the entire RF
`frequencies for LB (6–10.4 GHz) are covered without disconti-
`nuity and so are those for HB as well.
`With the dual-IF frequency scheme, the required VCO tuning
`range is reduced from 54% to 33% and 29% for LB and HB, re-
`spectively. This relaxed tuning range enables us to further opti-
`mize the other VCO performance such as phase noise and power
`consumption [20].
`
`The RF channel spacing depends on which LO frequency
`scheme is selected at the given LO frequency step (200 MHz).
`The channel spacing is 225 MHz when operating in the 1/8 LO
`scheme and 300 MHz in the 1/2 LO scheme.
`
`V. CIRCUIT IMPLEMENTATION
`The detailed circuit design of the CMOS receiver is presented
`in this section. Most circuit blocks including the mixers, base-
`band VGAs, VCOs, LO distribution buffers, and phase rota-
`tors use differential signaling while the TCA amplifies a single-
`ended signal.
`
`A. Tunable Concurrent Amplifier (TCA)
`is split
`Since the incoming concurrent dual-band signal
`on-chip before the down-conversion, the front-end TCA must
`provide a single input and a dual output. Important design
`parameters in the TCA are the wideband input matching,
`noise figure, frequency tunability, and isolation between two
`different outputs. The single input port should provide a good
`input matching performance over the entire tritave, from 6 to
`18 GHz. The two output ports present two separate signals well
`filtered at the desired frequencies that should be tunable over
`the entire LB and HB frequencies, respectively. Also, good
`isolation is needed between the two output ports in terms of
`
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`
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`
`Fig. 8. Baseband VGA.
`
`Fig. 7. Schematic of the RF mixer and IF buffer for (a) LB and (b) HB.
`
`Fig. 9. Schematic of the wideband VCO.
`
`signal and noise. Note that the noise figure requirement of the
`TCA is relaxed to a significant degree due to the low-noise
`active antenna module that will be deployed in front of the
`CMOS receiver in the array system (Fig. 3).
`Through an in-depth investigation of several potential topolo-
`gies, the TCA is implemented in a parallel cascode configura-
`tion with an active termination [21], as shown in Fig. 6. The
`cascode amplifiers not only enhance the isolation between the
`two output signals, but also minimize the crosstalk of noise pro-
`duced by the active blocks.
`is achieved by an ac-
`The wideband input matching to 50
`tive termination with shunt resistive feedback and an impedance
`transformation network. The active termination contributes less
`noise to the subsequent blocks than a simple shunt resistive ter-
`mination [22].
`
`The RF signals at two frequencies are then selectively am-
`–
`,
`–
`plified by two separate cascode amplifiers
`that have tunable LC output loads. A 3-bit switched capacitor
`bank at each output load is tuned to cover the entire LB and
`HB frequencies. This allows for the digital tuning of the ampli-
`fier so that it can provide the maximum gain at the desired fre-
`quency while attenuating out-of-band signals prior to the first
`down-conversion.
`
`B. Mixers
`
`Four different mixer designs are presented in the receiver; RF
`and IF mixers, each for LB and HB, respectively. The current-
`commutating double-balanced topology is adopted for all the
`mixers in order to minimize the LO-to-IF feedthrough. Fig. 7(a)
`shows the schematic of the RF mixer and IF buffer for LB. A
`shunt-peaking inductor (3.3 nH) is used to extend the IF 3-dB
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`Fig. 10. Block diagram of the programmable PLL.
`
`Fig. 11. LO distribution and buffers.
`
`bandwidth up to over 3.5 GHz. Since the TCA provides a single-
`ended RF signal to the differential RF mixers, one RF input
`terminal is terminated to a bias voltage by a 2-k resistor and a
`bypass capacitor.
`The HB RF mixer employs a tunable LC load with a 3-bit
`switched capacitor bank at the IF output, as shown in Fig. 7(b).
`The resonant frequency of the LC load is tuned in such a way
`that the conversion gain is maximized at the desired IF fre-
`quency. The common-mode feedback circuitry ensures a given
`set for the subsequent buffer block.
`bias voltage
`The schematic of the IF mixers for LB and HB are similar to
`that of the LB RF mixer. The difference is that the IF mixers em-
`ploy no shunt-peaking inductors and are degenerated by source
`resistors to improve linearity of the baseband signal.
`
`C. Baseband Variable-Gain Amplifier (VGA)
`The VGA combines five transconductance amplifiers in the
`current domain with digitally switched bias voltages (Fig. 8).
`and
`,
`and
`are identical pairs that con-
`stitute current-commutating cells by digital switches (
`
`). Each transconductance amplifier has a differential
`and
`common-source topology with resistive degeneration. Since the
`output port is configured with open drains, the output signals
`from each array element can be easily combined in the current
`domain using a passive network which imposes little additional
`impact on the nonlinearity performance. The open-drain output
`requires an external DC supply of 1.5 V. The VGA achieves a
`nominal gain of 7 dB with a 11 dB gain variation in five steps
`differential output load.
`when driving a 100-
`
`D. Voltage-Controlled Oscillator (VCO)
`
`Two separate LC VCOs are implemented to generate the LO
`signals for LB and HB, respectively. Th