NEMEee
`
`DAVID A. JOHNS
`KEN MARTIN
`
`

`

`
`
`

`

`080 732
`
`wuiieiiaaiio
`
`38
`
`

`

` ANALOG INTEGRATED
`
`CIRCUIT DESIGN
`
`me
`
`David Johns
`Ken Martin
`
`University of Toronto
`
`
`
`John Wiley & Sons, Inc.
`+ Brisbane
`New York
`« Chichester
`Toronto
`» Singapore
`»* Weinheim
`
`
`
`

`

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`Acquisitions Editor
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`ication Services and printed and bound
`This book was set in Times Roman by Publ
`nted by Lehigh Press.
`by R.R. Donnelley/Crawfordsville. The cover was pri
`
`f preserving what has beenwritten,it isa
`Recognizing the importance 0
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`e paper, and we exert our best
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`|
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`I
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`j
`
`;
`
`Copyright © 1997, by John Wiley & Sons, Inc.
`All rights reserved. Published simultaneously in Canada.
`
`Reproduction or translation of any part of
`this work beyond that permitted by Sections
`107 and 108 ofthe 1976 United States Copyright
`Act without the permission of the copyright
`owneris unlawful. Requests for permission
`or further information should be addressed to
`the Permissions Department, John Wiley & Sons, Inc.
`
`
`
`
`
`
`
`
`
`Johns, David, 1958-
`Analogintegrated circuit design
`p.
`cm.
`Includes bibliographical references.
`ISBN 0-471-14448-7 (cloth : alk. paper)
`1. Linear integrated circuits—Design and construction.
`1. Martin, Kenneth W. (Kenneth W.) 1952—__. IL. Title.
`TK7874.J65 1996
`
`96-34365
`621.3815—dc20
`CIP
`
`
`ISBN 0-471-14448-7
`Printed in the United States of America
`
`
`
`
`Library ofCongress Cataloging-in-Publication Data:
`
`/ David Johns, Ken Martin.
`
`1098765432
`
`

`

`
`
`Contents
`
`CHAPTER 1
`
`
`
`
`
`Gq
`
`INTEGRATED-CIRCUIT DEVICES AND MODELLING
`1.1
`Semiconductors and pn Junctions
`1
`1.2 MOSTransistors
`16
`1.3. Advanced MOS Modelling
`1.4 Bipolar-Junction Transistors
`56
`1.5 Device Model Summary
`1.6 SPICE-Modelling Parameters
`
`1.7 Appendix
`65
`
`1.8 References
`78
`
`1.9 Problems
`78
`
`
` CHAPTER 2
`
`PROCESSING AND LAYOUT
`
`82
`2.1
`CMOSProcessing
`2.2 Bipolar Processing
`95
`
`2.3.
`CMOSLayout and Design Rules
`
`2.4 Analog Layout Considerations
`
`2.5 Latch-Up
`118
`
`2.6 References
`121
`
`2.7 Problems.
`121
`
`
`
`
`BASIC CURRENT MIRRORS AND SINGLE-STAGE AMPLIFIERS
`CHAPTER 3.
`
`3.1
`Simple CMOS Current Mirror
`125
`
`
`3.2.
`Common-Source Amplifier
`128
`
`3.3.
`Source-Follower or Common-Drain Amplifier
`
`3.4
`Common-Gate Amplifier
`132
`
`3.5
`Source-Degenerated Current Mirrors
`
`3.6
` High-Output-Impedance Current Mirrors
`
`3.7.
`Cascode Gain Stage
`140
`
`38
`MOSDifferential Pair and Gain Stage
`
`3.9
`Bipolar Current Mirrors
`146
`
`Bipolar Gain Stages
`
`
`39
`42
`
`61
`
`96
`105
`
`129
`
`135
`
`137
`
`142
`
`149
`
`
`
`

`

` Contents=Xi
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`154
`Frequency Response
`3.11
`3.12 SPICE Simulation Examples
`3.13 References
`176
`3.14 Problems
`176
`
`169
`
`CHAPTER 4
`
`NOISE ANALYSIS AND MODELLING
`
`181
`
`4.1 Time-Domain Analysis
`186
`4.2 Frequency-Domain Analysis
`4.3 Noise Models for Circuit Elements
`4.4 Noise Analysis Examples
`204
`4.5 References
`216
`4.6 Problems
`217
`
`196
`
`CHAPTER 5
`
`BASIC OPAMP DESIGN AND COMPENSATION
`
`221
`5.1 Two-Stage CMOS Opamp
`5.2 Feedback and Opamp Compensation
`5.3.
`SPICE Simulation Examples
`251
`5.4 References
`252
`5.5 Problems
`23
`
`232
`
`181
`
`221
`
`CHAPTER 6
`
`ADVANCED CURRENT MIRRORS AND OPAMPS
`
`256
`
`256
`Advanced Current Mirrors
`6.1
`266
`Folded-Cascode Opamp
`6.2
`273
`Current-Mirror Opamp
`6.3
`Linear Settling Time Revisited
`6.4
`280
`Fully Differential Opamps
`6.5
`Common-Mode Feedback Circuits
`6.6
`Current-Feedback Opamps
`291
`6.7
`SPICE Simulation Examples
`295
`6.8
`References
`299
`6.9
`6.10 Problems
`300
`
`278
`
`287
`
`CHAPTER 7
`
`COMPARATORS
`
`304
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Using an Opampfor a Comparator
`7A
`7.2
`Charge-Injection Errors
`308
`73
`Latched Comparators
`3i7
`Examples of CMOS and BiCMOS Comparators
`74
`75
`Examples of Bipolar Comparators
`328
`7.6
`References
`330
`iT
`
`Problems 331
`
`304
`
`321
`
`
`
`

`

`
`
`xii
`
`Contents
`
`CHAPTER 8
`
`CHAPTER 9
`
`DISCRETE-TIME SIGNALS
`373
`Overview of Some Signal Spectra
`Laplace Transforms of Discrete-Time Signals
`z-Transform
`377
`Downsampling and Upsampling
`Discrete-Time Filters
`382
`Sample-and-Hold Response
`References
`BO
`Problems
`391
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`9.1
`
`92,
`9.3
`
`9.4
`9.5
`
`9.6
`
`9.7
`
`9.8
`
`
`SWITCHED-CAPACITORCIRCUITS
`;
`CHAPTER 10
`Basic Building Blocks
`394
`
`10.1
`Basic Operation and Analysis
`
`10.2
`First-Order Filters
`409
`10.3
`
`415
`Biquad Filters
`
`10.4
`423
`Charge Injection
`10.5
`
`427
`Switched-Capacitor Gain Circuits
`10.6
`
`Correlated Double-Sampling Techniques
`
`10.7
`434
`Other Switched-Capacitor Circuits
`
`10.8
`References
`44)
`10.9
`
`Q Problems
`443
`
`10.1
`
`
`
`DATA CONVERTER FUNDAMENTALS
`CHAPTER 11
`11.1.
`Ideal D/A Converter
`445
`
`11.2
`Ideal A/D Converter
`447
`
`11.3 Quantization Noise
`448
`
`
`452
`
`
`SAMPLE AND HOLDS, VOLTAGE REFERENCES,
`AND TRANSLINEARCIRCUITS
`Performance of Sample-and-Hold Circuits
`MOSSample-and-Hold Basics
`336
`Examples of CMOS S/H Circuits
`343
`Bipolar and BiCMOS Sample and Holds
`Bandgap Voltage Reference Basics
`353)
`Circuits for Bandgap References
`357
`Translinear Gain Cell
`364
`Translinear Multiplier
`366
`References
`368
`Problems
`370
`
`8.1
`8.2
`8.3
`8.4
`8.5
`8.6
`8.7
`8.8
`8.9
`8.10
`
`379
`
`389
`
`398
`
`334
`
`334
`
`349
`
`373
`
`374
`
`433
`
`11.4. Signed Codes
`
`

`

`
`—Xilil
`
`
`
`
`
`
`
`
`
`
`
`
`
`463
`
`Contents
`
`11.5 Performance Limitations
`11.6 References
`461
`11.7. Problems
`461
`
`454
`
`NYQUIST-RATE D/A CONVERTERS
`463
`12.1 Decoder-Based Converters
`469
`12.2 Binary-Scaled Converters
`12.3. Thermometer-Code Converters
`12.4 Hybrid Converters
`481
`12.5 References
`484
`12.6 Problems
`484
`
`475
`
`NYQUIST-RATE A/D CONVERTERS
`13.1
`Integrating Converters
`487
`13.2.
`Successive-Approximation Converters
`13.3.
`Algorithmic (or Cyclic) A/D Converter
`13.4
`Flash (or Parallel) Converters
`507
`13.5
`Two-Step A/D Converters
`513
`13.6
`Interpolating A/D Converters
`516
`519
`13.7.
`Folding A/D Converters
`523
`13.8
`Pipelined A/D Converters
`13.9
`Time-Interleaved A/D Converters
`13.10 References
`527
`13.11
`Problems
`528
`
`526
`
`492
`504
`
`OVERSAMPLING CONVERTERS
`14.1
`Oversampling without Noise Shaping
`14.2
` Oversampling with Noise Shaping
`14.3.
`System Architectures
`547
`551
`14.4
`Digital Decimation Filters
`355
`14.5
`Higher-Order Modulators
`14.6
`Bandpass Oversampling Converters
`14.7
`Practical Considerations
`559
`14.8 Multi-Bit Oversampling Converters
`14.9
`Third-Order A/D Design Example
`14.10 References
`571
`14.11
`Problems
`572
`
`531
`538
`
`557
`
`565
`568
`
`CHAPTER 12
`
`CHAPTER13
`
`CHAPTER 14
`
`CHAPTER 15
`
`CONTINUOUS-TIMEFILTERS
`15.1
`Introduction to G,,-C Filters
`15.2
`Bipolar Transconductors
`
`575
`584
`
`487
`
`531
`
`574
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`

`

`
`xiv—_Contents
`
`597
`15.3.
`CMOSTransconductors Using Triode Transistors
`
`607
`15.4.
`CMOSTransconductors Using Active Transistors
`
`15.5
`BiCMOS Transconductors
`616
`
`15.6
`MOSFET-CFilters
`620
`
`15.7.
`Tuning Circuitry
`626
`
`15.8
`Dynamic Range Performance
`
`15.9
`References
`643
`
`15.10 Problems
`645
`
`
`635
`
`CHAPTER 16
`
`648
`
`PHASE-LOCKED LOOPS
`648
`16.1 Basic Loop Architecture
`16.2 PLLs with Charge-Pump Phase Comparators
`16.3 Voltage-Controlled Oscillators
`670
`16.4 Computer Simulation of PLLs
`680
`16.5 Appendix
`689
`16.6 References
`692
`16.7 Problems
`693
`
`663
`
`
`
`
`
`
`
`
`
`
`
`

`

`sometimes usedin digital circuits, where the circle indicates that a low voltage on the
`gate turnsthe transistor on, as opposed to a high voltage for an n-channeltransistor
`(Fig. 1.7(a@)). The symbols of Fig. 1.8(d) or Fig. 1.8(e) might be usedin largercircuits
`where manytransistors are present, to simplify the drawing somewhat. They will not
`be usedinthis text.
`
`19
`
`Basic Operation
`
`
`
` 1.2. MOSTransistors
`
`
`
`
`
`
`
`The basic operation of MOStransistors will be described with respect to an n-channel
`transistor. First, consider the simplified cross sections shown in Fig. 1.9, where the
`source, drain, and substrate are all connected to ground.In this case, the MOStransis-
`tor operates similarly to a capacitor. The gate acts as one plate of the capacitor, and
`the surface ofthe silicon, just underthe thin insulating SiO,,acts as the otherplate.
`If the gate voltage is very negative, as shownin Fig. 1.9(a), positive charge will
`be attracted to the channel region. Since the substrate was originally doped p, this
`negative gate voltage has the effect of simply increasing the channel doping to p*,
`
`
`Source Vg << 0
`
`
`
`SiO,
`Drain
`
`
`
`
`
`Drain
` - Channel
`Depletion region yf
`
`
`
`
`Depletion region
`p” substrate
`Lt
`
`- Accumulation region
`
`
`
`Source
`
`Vg>>o0
`
`SiO,
`
`
`
`psubstrate
`
`(b)
`
`Fig. 1.9 An n-channel MOStransistor. (a) Vg << 0, resulting in an accu-
`mulated channel(no currentflow}; (b) Vg >> 0, and the channelis present
`(current flow possible from drain to source).
`
`

`

`
`
`Chapter 1
`
`© Integrated-Circuit Devices and Modelling
`
`20
`
`
`
`
`
`resulting in whatis called an accumulated channel. The n* source and drain regions
`are separated from the p*-channel region by depletion regions, resulting in the equiva-
`lent circuit of two back-to-back diodes. Thus, only leakage current will flow even if
`one of the source or drain voltages becomeslarge (unless the drain voltage becomes
`so large as to cause the transistor to break down).
`In the case of a positive voltage being applied to the gate, the opposite situation
`occurs, as shown in Fig. 1.9(b). For small positive gate voltages, the positive carriers
`in the channel under the gate are initially repulsed and the channel changes froma p-
`doping level to a depletion region. As a more positive gate voltage is applied, the gate
`attracts negative charge from the source and drain regions, and the channel becomes
`an N region with mobile electrons connecting the drain and source regions.” In short, a
`sufficiently large positive gate-source voltage changes the channel beneath the gate to
`an n region, and the channelis said to be inverted.
`The gate-source voltage, for which the concentration of electrons under the gate
`is equal to the concentration of holes in the p~ substrate far from the gate, is com-
`monly referred to as the transistor threshold voltage and denoted V,,, (for n-channel
`transistors). For gate-source voltages larger than Vj,, there is an n-type channel
`present, and conduction between the drain and the source can occur. For gate-source
`voltagesless than Vip, it is normally assumed that the transistor is off and no current
`flows between the drain and the source. However,it should be notedthat this assump-
`tion of zero drain-source currentfor a transistor thatis off is only an approximation.In
`fact, for gate voltages around Vj,there is no abrupt current change, and for gate-
`source voltages slightly less than V,,, small amounts of subthreshold current can
`flow, as discussed in Section 1.3.
`Whenthegate-source voltage, Vgg_, is larger than Vip, the channelis present. As
`Vsis increased,the density of electronsin the channelincreases. Indeed,the carrier
`density, and therefore the charge density, is proportional to Vas — Vin» which is often
`called the effective gate-source voltage and denoted Vet: Specifically, define
`Ver = Vas~ Vin
`
`(1.54)
`
`The charge density of electronsis then given by
`Qn = Cox(Vas— Vin) = CoxVett
`
`Here, C,, is the gate capacitance per unit area andis given by
`
`i Pony
`tox
`
`(1,35)
`
`(1.56)
`
`where K,, is the relative permittivity of SiO. (approximately 3.9) and t,, is the
`thickness of the thin oxide under the gate. A point to note here is that (1.55) is only
`accurate when both the drain and the source voltagesare zero.
`
`5, The drain and source regions are sometimescalled diffusion regions or junctions for historical reasons.
`This use of the wordjunction is not synonymouswith our previous use, in which it designated a pn inter-
`face of a diode.
`
`

`

`
`
`To obtain the total gate capacitance, (1.56) should be multiplied by the effective
`gate area, WL, where W is the gate width and L is the effective gate length. These
`
`dimensionsare shownin Fig. 1.10. Thusthe total gate capacitance, Cy, is given by
`Cys = WLC,,
`(1.57)
`
`
`andthetotal charge of the channel, Qr.,, is given by
`
`(1.58)
`Qtr = WLC,,(Vas— Vin) = WLC,Vert
`
`Thegate capacitance, Cg, , is one of the major load capacitances that circuits must be
`capable of driving. Gate capacitances are also important when one is calculating
`charge injection, which occurs when a MOS transistor is being turned off because the
`
`channel charge, Qy.,, must flow from under the gate out through the terminals to
`otherplaces in the circuit.
`Next, if the drain voltage is increased above 0 V,a drain-source potential differ-
`ence exists. This difference results in current flowing from the drain to the source.°
`
`The relationship between Vpg and the drain-source current, Ip, is the same as for a
`resistor, assuming Vpgis small. This relationship is given [Sze, 1981] by
`
`Ww
`(1.59)
`Ip = nQn7Vos
`
`where LL, = 0.06 m’/Vsis the mobility of electronsnear the silicon surface, and Q,
`is the charge concentration of the channel per unit area (looking from the top down).
`Notethat as the channel length increases, the drain-source current decreases, whereas
`
`this current increases as either the charge density or the transistor width increases.
`Using (1.58) and (1.59) results in
`
`
`Ww
`Ww
`Ip = HnCox7(Vas — Vin)Vos oa HnCoxyVerVos
`
`
`1.2. MOSTransistors
`
`21
`
`
`
`(1.60)
`
`SiO,
`
`/
`
`
`
`
`n channel
`
`Fig. 1.10 The important dimensions of a MOStransistor.
`
`6. Thecurrentis actually conducted by negative carriers (electrons) flowing from the source to the drain.
`Negative carriers flowing from source to drain results in a positive current from drain to source, Ipg .
`
`
`
`
`
`
`

`

`
`
`Chapter 1
`
`¢ Integrated-Circuit Devices and Modelling
`
`where it should be emphasized that this relationship is only valid for drain-source
`voltages near zero (i.e., Vpg much smaller than V¢4).
`As the drain-source voltage increases, the channel charge concentration decreases
`at the drain end. This decreaseis due to the smaller gate-to-channelvoltage difference
`across the thin gate oxide as one movescloser to the drain. In Other words, since the
`drain voltage is assumedto be at a higher voltage than the source, there is an increasing
`voltage gradient from the source to the drain, resulting in a smaller gate-to-channel
`voltage nearthe drain. Since the charge density at a distance x from the source end of
`the channel
`is proportional to Vg—Ven(X)— Vin, aS Vg—Ven(x) decreases,
`the
`charge density also decreases.’ This effectis illustrated in Fig. 1.11.
`Note that at the drain end of the channel, we have
`(1.61)
`Ve—-Ven(L) = Veo
`For small Vpg, we saw from (1.60) that I, waslinearly related to Vps. However, as
`Vpg increases, and the charge density decreases near the drain, the relationship
`becomes nonlinear.In fact, the linear relationship for Ip versus Vpgflattensfor larger
`Vps,as shownin Fig. 1.12.
`
`Va >> Vin
`°
`
`Vp>0
`
`Q,(0)
`
`|
`
`Fig. 1.11 The channel charge density for Vpg > 0.
`Ww
`Ip< UnCoxT Vas — Vin)Vos
`.>
`‘
`Ba.
`
`=
`
`
`
`Z
`Ip = aCe Weg Vin)Vbs
`the
`
`Vos
`
`For Vpg notclose to zero, the
`Fig. 1.12
`Ip versus Vpgrelationship is no longer
`linear.
`
`
`
`is the gate-to-channel voltage drop at distance x from the source end, with Vg being the
`7. Vg—Veon(X)
`same everywhere in the gate, since the gate material is highly conductive.
`
`
`
` ‘
`
`|
`
`.
`
`Increasing x Q,(L) = Cox(Ven - Vin)
`|
`Cox(Ves— Vin)
`Q,(x) = Cox(Vas — Ven(X) — Vin)
`
`

`

`Asthe drain voltage is increased, at some point the gate-to-channel voltage at the
`drain end will decrease to the threshold value V,,—the minimum gate-to-channel
`voltage needed for n carriers in the channelto exist. Thus, at the drain end, the chan-
`nel becomes pinched off, as shownin Fig. 1.13. This pinch-off occurs at Ven = Vin»
`since the channel voltage at the drain end is simply equal to Vp. Thus, pinch-off
`occurs for
`
`Vp >—Vin
`
`(1.62)
`
`Denoting Vpg.sat a5 the drain-source voltage when the channel becomespinched off,
`we can substitute Vpg = Vpg— Vag into (1.62) and find an equivalent pinch-off
`expression
`
`Vos > Vos-sat
`
`(1.63)
`
`where Vpg.sat is given® by
`Vos-sat = Ves— Vin = Vert
`(1.64)
`_ The electron carriers travelling through the pinched-off drain region are velocity
`saturated, similar to a gas underpressure travelling through a very small tube. If the
`drain-gate voltage rises abovethis critical pinch-off voltage of —V,,,, the charge con-
`centration in the channel remains constant (to a first-order approximation) and the
`drain current no longer increases with increasing Vpg. The result is the current-
`voltage relationship shownin Fig. 1.14 for a given gate-source voltage. In the region
`of operation where Vpg > Vps-sat> the drain current is independent of Vpg and is
`called the active region.’ The region where Ip changes with Vpgis called the triode
`region. When MOStransistors are used in analog amplifiers, they almost always are
`biased in the active region. Whenthey are usedin digital logic gates, they often oper-
`ate in both regions.
`
`Vs = 0
`
`Ve >> Vin
`
`Depletion region
`
`
`
`Pinch-off for
`Veo < Vin
`
`Fig. 1.13 When Vpgis increased so that Vgp < Vin, the channel becomespinchedoffatthe drain end.
`
`
`
`
`
`
`
`
`
`
`
`
`1.2 MOS Transistors
`
`23
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`8. Because of the body effect, the threshold voltageat the drain endofthe transistor is increased,resulting
`in the true value of Vpg_gqt being slightly lower than V4¢,.
`9. Historically, the active region wascalled the saturation region, but this led to confusion becausein the
`case ofbipolar transistors, the saturation region occurs for small Vog , whereas for MOStransistorsit
`occurs for large Vpg. The renamingofthe saturation regionto the active region is becoming widely
`accepted.
`
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`

`

` 24
`
`Chapter 1
`
`© Integrated-Circuit Devices and Modelling
`
`2
`
`
`UnCoxW
`WwW
`Vv
`2 Tas = Vink
`Ip =
`Ip = HCox|(Ves -Vin)Vos - al
`Ip DP pita Ves constant
`
`fo
`
`i
`
`;
`
`Active
`region
`
`fr
`“ Triode
`#
`region
`
`Vos-sat = Vert
`/YW
`Ip = HnCox7-(Vas ~ Vin)Vos
`
`Ip versus Vpg curve for an ideal MOS transistor. For
`Fig. 1.14 The
`Vos > Vos.sat» Lp is approximately constant.
`
`Before proceeding, it is worth discussing the terms weak, moderate, and strong
`inversion. As just discussed, a gate-source voltage greater than V,,
`results in an
`inverted channel, and drain-source current can flow. However, as the gate-source
`voltage is increased, the channel does not becomeinverted(i.e., n-region) suddenly,
`but rather gradually. Thus, it is useful to define three regions of channel inversion
`with respect to the gate-source voltage. In most circuit applications, noncutoff MOS-
`FETtransistors are operated in strong inversion, with V4, > 100 mV (many prudent
`circuit designers use a minimum value of 200 mV). As the name suggests, strong
`inversion occurs when the channelis strongly inverted. It should be noted that all the
`equation models in this section assume strong inversion operation. Weak inversion
`occurs when Vgg is approximately 100 mV or more below V,,, and is discussed as
`subthreshold operation in Section 1.3. Finally, moderate inversion is the region
`between weak andstrong inversion.
`
`
`
`
`
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`
`
`
`
`Large-Signal Modelling
`
`Thetriode region equation for a MOStransistor relates the drain current to the gate-
`source and drain-source voltages. It can be shown (see Appendix) that this relation-
`ship is given by
`
`
`
`
`
`
`Ip = tnCof|Vas—Vin)Vbs- >
`
`W
`
`Vos
`
`(1.65)
`
`As Vpg increases,Ip increases until the drain end of the channel becomespinchedoff,
`and then Ip no longerincreases. This pinch-off occurs for Vpg = —Vtn, or approxi-
`mately,
`
`Vos = Vas—Vin = Vers
`
`(1.66)
`
`Right at the edge of pinch-off, the drain current resulting from (1.65) and the drain
`current in the active region (which,to a first-order approximation, is constant with
`
`

`

`
`
`
`
`
`
`respect to Vpg ) must have the same value. Therefore, the active region equation can
`be found by substituting (1.66) into (1.65), resulting in
`
`1.2. MOS Transistors
`
`25
`
`Co.fW
`
`Ip = eaeven—Va
`
`(1.67)
`
`For Vpg > Ver, the current stays constant at the value given by (1.67), ignoring
`second-order effects such as the finite output impedanceofthe transistor. This equation
`is perhaps the most importantone that describes the large-signal operation of a MOS
`transistor. It should be noted here that (1.67) represents a squared current-voltage
`relationship for a MOStransistorin the active region.In the case of a BJT transistor, an
`exponential current-voltage relationship exists in the active region.
`Asjust mentioned, (1.67) implies that the drain current, Ip, is independentof the
`drain-source voltage. This independenceis only trueto a first-order approximation.
`The major sourceof error is due to the channel length shrinking as Vpg increases. To
`see this effect, consider Fig. 1.15, which showsa cross section ofa transistor in the
`active region. A pinched-off region with very little charge exists between the drain and
`the channel. The voltage at the end of the channel closest to the drain is fixed at
`Vos—Vin = Verr- The voltage difference between the drain and the near endof the
`channellies across a short depletion region often called the pinch-off region. As Vpg
`becomes larger than V,4;,
`this depletion region surrounding the drain junction
`increases its width in a square-root relationship with respect to Vpg. This increasein
`the width ofthe depletion region surroundingthe drain junction decreases the effective
`channel length. In turn, this decrease in effective channel length increases the drain
`current, resulting in what is commonly referred to as channel-length modulation.
`To derive an equation to account for channel-length modulation, we first make
`use of (1.11) and denote the width of the depletion region by Xg, resulting in
`
`
`
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`
`
`
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`
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`
`
`where
`
`Xg = Kas Vp-ch + Po
`
`Kas¥Vpa + Vin + Po
`
`ds
`
`=
`
` [2K5€
`N q N A
`
`Ves > Vin
`
`(1.68)
`
`1.69
`
`Vos > Vas-Vin
`
`
`
`Depletion region AL JVpg—Ver+®o—Pinch-off region
`
`Fig. 1.15 Channel length shortening for Vpg > Vert -
`
`
`
`

`

` 26
`
`© Integrated-Circuit Devices and Modelling
`and has units of m/./V. Note that Na is used here since the n-type drain region is
`more heavily doped than the p-type channel (i.e., Np >> Na). By writing a Taylor
`approximation for I, around its operating value of Vpg = Veg— Vin = Ver, we
`find Ip to be given by
`
`Chapter 1
`
`
`
`alyVa kas(Vos - Vert)
`
`OL
`\AVps
`. a Wie * Vi, +85
`
`Ip = Ib-sat+ — sar,Vos = loan +Ss (1.70)
`
`
`
`
`
`
`where A. is the output impedanceconstant (in units of V~') given by
`
`y=—Kes
`(1.72)
`2L/Vpet Vint Po
` 2L4/Vog— Ve+ Po
`
`
`where Ipsat is the drain current when Vpg = Vo4;, or equivalently, the drain current
`when the channel-length modulation is ignored. Note that in deriving the final equa-
`tion of (1.70), we have used the relationship 0OL/OVps5 = —dXy/dVps. Usually,
`(1.70) is written as
`
`= UnCox
`2
`
`Ip
`
`WwWF| Vig=Vin)(14Vong—Viel!
`
`(1.7)
`
`Equation (1.71) is accurate until Vpg is large enough to cause second-order effects,
`often called short-channel effects. For example, (1.71) assumes that current flow
`downthe channelis not velocity-saturated(i.e., increasing the electric field no longer
`increases the carrier speed). Velocity saturation commonly occurs in new technolo-
`gies that have very short channel lengths and therefore large electric fields. If Vps
`becomeslarge enoughso short-channel effects occur, Ip increases more thanis pre-
`dicted by (1.71). Of course, for quite large values of Vpg, the transistor will eventu-
`ally break down.
`A plot of Ip versus Vpg for different values of Vgg is shown in Fig. 1.16. Note
`that in the active region, the small (but nonzero) slope indicates the small dependence
`of Ip on Vos.
`
`Ip
`
`Vos = (Ves — Vin)
`
`region
`
`'
`\
`
`Active
`region
`
`Short-channe!
`effects
`
` Triode
`
`
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`
`fincreasing Vegs
`
`Vas > Vin
`
`Fig. 1.16 I, versus Vpg fordifferent values of Veg.
`
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