(19) United States
`(12) Patent Application Publication (10) Pub. No.: US 2011/0217945 A1
`(43) Pub. Date:
`Sep. 8, 2011
`Uehara et a].
`
`US 20110217945A1
`
`(54) DUAL CARRIER AMPLIFIER CIRCUITS AND
`METHODS
`
`(76) Inventors:
`
`(21) APPL NO.
`
`Gregory Uehara, Austin, TX (US);
`X' h F A t' TX S
`m0 “a an’ us 1n’
`(U )
`13/038,778
`
`(22) Filed;
`
`Man 2, 2011
`
`Related US, Application Data
`_
`_
`_
`_
`(60) PrOVlslOnal apphcanon NO‘ 61/309,810’ ?led on Mar‘
`2’ 2010'
`
`_
`_
`_
`_
`Pubhcatlon Classl?catlon
`
`(51) Int, Cl,
`H04B 1/16
`G06G 7/12
`H03F 1/22
`
`(200601)
`(200601)
`(2006,01)
`
`(52) US. Cl. ........................ .. 455/341; 327/355; 455/334
`
`ABSTRACT
`(57)
`In one embodiment, the present disclosure includes a circuit
`comprising ?rst and second transconductance stages that
`receive an RF signal and a current combiner circuit. The
`current combiner circuit couples current from the ?rst
`transconductance stage to (i) one of a ?rst output path or a
`second output path or (ii) both the ?rst output path and second
`output path. The current combiner circuit decouples current
`from the second transconductance stage from both the ?rst
`output path and second output path When the ?rst transcon
`ductance stage couples current to one of the ?rst output path
`or the second output path. The current combiner circuit
`couples current from the second transconductance stage to
`both the ?rst output path and the second output path When the
`?rst transconductance stage couples current to both the ?rst
`output path and the second output path.
`
`200B
`
`\/-253
`
`VP
`
`224
`
`222
`
`| -------------------------------- - -
`
`- - - - ----------------------------- - - |
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`|
`|
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`I
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`V229 —||:,225
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`I
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`VNAux -I—| E/ZO9V—| @205 2075 vN1211\/:_||— VNAux
`I
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`|
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`I
`VP2
`VPAuX —| \/‘230 _||:/~226
`
`228\/:|
`
`i
`I:| I
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`: VPAuX
`OUT2
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`VNAux —||__;/21oV£| @206 208V] |?2212v3 I VNAux
`I
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`|
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`|
`|
`|
`|
`|
`
`201
`
`203
`
`250\/
`
`INTEL 1003
`
`

`

`Patent Application Publication
`
`Sep. 8, 2011 Sheet 1 0f 5
`
`US 2011/0217945 A1
`
`1 0
`
`101
`
`IN
`
`Gm1 —>
`
`—> OUT1
`
`Current
`Combiner
`Circuit
`
`Gm2 —>
`
`—> OUT2
`
`102
`
`103
`
`Fig. 1
`
`

`

`Patent Application Publication
`
`Sep. 8, 2011 Sheet 2 0f 5
`
`US 2011/0217945 A1
`
`BN5
`
`NON
`
`wow
`
`<coN
`
`<~ at
`
`

`

`Patent Application Publication
`
`Sep. 8, 2011 Sheet 3 0f 5
`
`US 2011/0217945 A1
`
`5N5
`
`NON
`
`wow
`
`mm at
`
`

`

`Patent Application Publication
`
`Sep. 8, 2011 Sheet 4 0f 5
`
`US 2011/0217945 A1
`
`350
`
`351
`
`352
`
`301
`
`L0
`304
`'
`
`306
`
`.
`
`—
`
`Fllter
`
`Ntwk
`
`Gm1 _
`
`Current
`Combiner
`
`_
`
`— Clrcult
`
`Gm2 —
`
`x
`
`X
`
`X
`
`X
`
`OUT1
`
`OUT2
`
`Z
`302
`
`Z
`303
`
`305 307
`L02
`
`Fig. 3
`
`M
`402
`
`SW1
`
`401
`
`SW3
`
`403A
`
`404A
`I
`
`405A
`\
`
`406
`_\_
`
`4P7
`\
`
`450
`g
`
`RF Transceiver
`
`_
`SAW1 — Matchlng —— LNA —
`_ Network __ _ Down Converslon
`Baseband Procecssing
`—
`
`{ 4038
`
`{4045
`
`{4058
`
`2
`
`403C
`y
`
`\M 472
`M
`U
`4
`4046
`.
`f 050 X
`y
`_ Matching __ _ Down Convers|on
`SAW3 _ Network __ LNA _ Baseband Procecssing
`
`\M 471
`
`{403D
`
`{404D
`
`{405D
`
`— Fi|ter(s) —> ADC
`
`SW4
`
`— Matching —— — \y
`SAW4 _ Network __ LNA __ K 481
`
`\y
`482
`
`1
`408
`
`Fig. 4
`
`

`

`Patent Application Publication
`
`Sep. 8, 2011 Sheet 5 0f 5
`
`US 2011/0217945 A1
`
`500
`
`N Receive RF Signal in first transconductance
`5'01
`stage including impedance matching
`
`502“
`
`Receive RF Signal in second
`transconductance stage
`
`503A‘ Combine Currents in Current Combiner Circuit
`
`Single Carrier
`
`Dual Carrier
`
`V
`Couple currents from first
`transconductance stage to output
`path and decouple currents from
`505
`second transconducance stage from
`output path
`‘N
`
`V
`506“ Couple currents from first and
`second transconductance stages to
`two output paths
`
`Fig. 5
`
`

`

`US 2011/0217945 A1
`
`Sep. 8, 2011
`
`DUAL CARRIER AMPLIFIER CIRCUITS AND
`METHODS
`
`CROSS REFERENCE TO RELATED
`APPLICATIONS
`
`[0001] The present disclosure claims the bene?t of priority
`from US. ProvisionalApplication No. 61/309,810, ?led Mar.
`2, 2010, the disclosure of Which is incorporated herein by
`reference in its entirety.
`
`BACKGROUND
`
`[0002] The present disclosure relates to dual carrier ampli
`?er circuits and methods.
`[0003] Unless otherWise indicated herein, the approaches
`described in this section are not prior art to the claims in this
`application and are not admitted to be prior art by inclusion in
`this section.
`[0004] Ampli?er circuits are basic building blocks of many
`electronic systems. Ampli?er circuits (or “ampli?ers”) are
`used to increase a particular characteristic of a signal, such as
`voltage, current, or poWer, for example. One type of ampli?er
`is the transconductance ampli?er. In a transconductance
`ampli?er, an input voltage signal is converted into a current
`output signal. The relationship betWeen the input voltage
`signal and current output signal is the transconductance
`(“Gm”) of the ampli?er. Transconductance is described by
`the folloWing equation:
`
`[0005] One issue With transconductance ampli?ers is the
`variation of ampli?er characteristics across different loads.
`For example, different loads may draW different amounts of
`current from the output of the transconductance ampli?er,
`thereby changing the characteristics of the ampli?er.
`[0006] Wireless receivers use loW noise ampli?ers
`(“LNAs”) to amplify radio frequency (“RF”) signals received
`from an antenna. In some Wireless applications, an RF signal
`may include multiple channels With multiple carrier frequen
`cies. To process such signals, an LNA may send the ampli?ed
`RF signal to different signal paths. If a transconductance
`ampli?er Were used for the LNA, the different signal paths
`Would alter the loading on the transconductance ampli?er
`output, thereby resulting in signal degradation and a reduced
`signal-to-noise ratio (“SNR”).
`[0007] Particular embodiments described beloW provide
`improved ampli?ers for driving different signal paths. Par
`ticular embodiments further provide processing for dual or
`multi-carrier signals, such as in a Wireless receiver.
`
`SUMMARY
`
`[0008] Embodiments of the present disclosure include dual
`carrier ampli?er circuits and methods. One embodiment
`includes a circuit comprising a ?rst transconductance stage
`having an input to receive a signal, a second transconductance
`stage having an input to receive the signal, and a current
`combiner circuit coupled to an output of the ?rst transcon
`ductance stage and an output of the second transconductance
`stage. The current combiner circuit forms a path from the ?rst
`transconductance stage to (i) one of a plurality of output paths
`or (ii) multiple output paths of the plurality of output paths.
`The current combiner circuit severs the second transconduc
`tance stage from the plurality output paths When the ?rst
`transconductance stage forms a path to one of the plurality of
`
`output paths. The current combiner circuit forms a path from
`the second transconductance stage to multiple output paths
`When the ?rst transconductance stage forms a path to multiple
`output paths.
`[0009] In one embodiment, the current combiner circuit
`couples current from the ?rst transconductance stage to (i)
`one of a ?rst output path or a second output path or (ii) both
`the ?rst output path and second output path. Additionally, the
`current combiner circuit decouples current from the second
`transconductance stage to both the ?rst output path and sec
`ond output path When the ?rst transconductance stage couples
`current to one of the ?rst output path or the second output
`path. Further, the current combiner circuit couples current
`from the second transconductance stage to both the ?rst out
`put path and the second output path When the ?rst transcon
`ductance stage couples current to both the ?rst output path
`and the second output path.
`[0010] In one embodiment, the current combiner circuit
`comprises cascode transistors con?gured betWeen the output
`of the second transconductance stage and the ?rst output path
`and the second output path.
`[0011] In one embodiment, the ?rst transconductance stage
`further comprises a ?rst inductance con?gured betWeen the
`source of the ?rst transistor and a reference voltage and a
`second inductance con?gured betWeen the source of the sec
`ond transistor and the reference voltage.
`[0012] In one embodiment, the signal is an RF signal.
`[0013] In one embodiment, the input of the ?rst transcon
`ductance stage and the input of the second transconductance
`stage are coupled to an antenna.
`[0014] Another embodiment includes an apparatus com
`prising an RF receiver, Wherein the RF receiver comprises
`one or more circuits having multiple transconductance stages
`and current combiner circuits as described herein. In one
`embodiment, the one or more multi-transconductance cir
`cuits are a plurality of loW noise ampli?ers. The RF receiver
`further comprising a ?rst doWn conversion circuit, the ?rst
`doWn conversion circuit having a ?rst input coupled to each of
`the loW noise ampli?ers and a second input coupled to receive
`a ?rst oscillating signal having a ?rst frequency, and a second
`doWn conversion circuit, the second doWn conversion circuit
`having a ?rst input coupled to each of the loW noise ampli?ers
`and a second input coupled to receive a second oscillating
`signal having a second frequency.
`[0015] Another embodiment includes a method comprising
`receiving a signal in a ?rst transconductance stage, receiving
`the signal in a second transconductance stage, and forming
`paths from the ?rst transconductance stage and the second
`transconductance stage to (i) one of a plurality of output paths
`or (ii) multiple output paths of the plurality of output paths.
`The second transconductance stage is severed from the plu
`rality output paths When the ?rst transconductance stage
`forms a path to one of the plurality of output paths. Further,
`the second transconductance stage forms a path to the mul
`tiple output paths of the plurality of output paths When the ?rst
`transconductance stage forms the path to the multiple output
`paths of the plurality of output paths.
`[0016] In one embodiment, current from the ?rst transcon
`ductance stage is coupled to (i) one of a ?rst output path or a
`second output path or (ii) both the ?rst output path and second
`output path, and current from the second transconductance
`stage is decoupled from both the ?rst output path and the
`second output path When the ?rst transconductance stage
`couples current to one of the ?rst output path or the second
`
`

`

`US 2011/0217945 A1
`
`Sep. 8, 2011
`
`output path. Additionally, current is coupled from the second
`transconductance stage to both the ?rst output path and the
`second output path When the ?rst transconductance stage
`couples current to both the ?rst output path and the second
`output path.
`[0017] In one embodiment, current combining comprises
`selectively enabling cascode transistors con?gured betWeen
`the output of the second transconductance stage and the ?rst
`output path and the second output path.
`[0018] In one embodiment, current combining comprises
`selectively enabling cascode transistors con?gured betWeen
`the output of the ?rst transconductance stage and the ?rst
`output path and the second output path to selectively couple
`current from the ?rst transconductance stage to (i) the ?rst
`output path or the second output path or (ii) both the ?rst
`output path and the second output path.
`[0019] In one embodiment, the signal is a differential RF
`voltage signal, and the method further comprises converting
`?rst and second differential components of the RF signal to
`?rst and second currents in corresponding ?rst and second
`differential transistors, converting the ?rst and second differ
`ential components of the RF signal to third and fourth currents
`in corresponding third and fourth differential transistors,
`selectively coupling the ?rst current through a ?fth transistor
`and the third current through a sixth transistor to a ?rst output
`path, and selectively coupling the second current through a
`seventh transistor and the fourth current through a eighth
`transistor to a second output path.
`[0020] In one embodiment, the signal is an RF signal, and
`the RF signal is received by the ?rst transconductance stage
`and the second transconductance stage from an antenna.
`[0021] The folloWing detailed description and accompany
`ing draWings provide a better understanding of the nature and
`advantages of the present invention.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`[0022] FIG. 1 illustrates an ampli?er circuit according to
`one embodiment.
`[0023] FIG. 2A shoWs an ampli?er circuit according to one
`embodiment.
`[0024] FIG. 2B shoWs an ampli?er circuit according to one
`embodiment.
`[0025] FIG. 3 shoWs another ampli?er circuit according to
`one embodiment.
`[0026] FIG. 4 shoWs an system using an ampli?er circuit
`according to one embodiment.
`[0027] FIG. 5 illustrates a process according to one
`embodiment.
`
`DETAILED DESCRIPTION
`
`[0028] Described herein are techniques for dual carrier
`ampli?er circuits and methods. In the folloWing description,
`for purposes of explanation, numerous examples and speci?c
`details are set forth in order to provide a thorough understand
`ing of particular embodiments. The circuits and methods
`disclosed herein may be used in a variety of electronic sys
`tems. Further, the circuits and methods describe herein may
`be implemented on an integrated circuit (IC). Particular
`embodiments as de?ned by the claims may include some or
`all of the features in these examples alone or in combination
`With other features described beloW, and may further include
`modi?cations and equivalents of the features and concepts
`described herein.
`
`[0029] FIG. 1 illustrates an ampli?er circuit 100 according
`to one embodiment. Ampli?er circuit 100 includes a
`transconductance stage 101, transconductance stage 102, and
`a current combiner circuit 103. Transconductance stages
`receive an input voltage and generate an output current.
`Transconductance stages are commonly referred to as “Gm
`stages,” Where “gm” is the transconductance (or voltage-to
`current gain) of the stage. Accordingly, in FIG. 1, transcon
`ductance stage 101 is labeled “Gml” and transconductance
`stage 102 is labeled “Gm2.” Transconductance stages 101 and
`102 have inputs to receive a signal “IN.” The IN signal may be
`an RF signal from an antenna, for example, as described in
`more detail beloW.
`[0030] Current combiner circuit 103 is coupled to an output
`of transconductance stage 101 and to an output of transcon
`ductance stage 102. Current combiner circuit 103 couples
`current from the transconductance stages to different output
`paths (e.g., OUT1 and/or OUT2). In some applications, it
`may be desirable to send an output signal from ampli?er
`circuit 100 to only output path OUT1 under some conditions,
`only output path OUT2 under other conditions, or to multiple
`output paths OUT1 and OUT2 under yet other conditions.
`Current combiner circuit 103 may selectively couple current
`from the different transconductance stages 101 and 102 to
`maintain consistent circuit characteristics, such as gain,
`across different output loads.
`[0031] For example, current combiner circuit 103 may be
`con?gured to couple current from transconductance stage
`101 to one of output path OUT1 or output path OUT2 or both
`output path OUT1 and output path OUT2. To maintain con
`sistent circuit characteristics, When transconductance stage
`101 couples current to one of output path OUT1 or output
`path OUT2, current combiner circuit 103 decouples current
`from transconductance stage 102 from both output path
`OUT1 and output path OUT2. Accordingly, in single carrier
`mode, for example, transconductance stage 101 is on and
`transconductance stage 102 is off, and transconductance
`stage 101 couples current to OUT1 or OUT2.
`[0032] HoWever, in one embodiment, transconductance
`stage 101 couples current to both output path OUT1 and
`output path OUT2. In this case, Which may be a dual carrier
`mode, current combiner circuit 103 compensates for the addi
`tional loading by coupling current from transconductance
`stage 102 to both output path OUT1 and output path OUT2. In
`another embodiment, in dual carrier mode, for example, both
`transconductance stages 101 and 102 are on, and transcon
`ductance stage 101 drives either OUT1 or OUT2 and
`transconductance stage 102 drives the output path not driven
`by transconductance stage 101.
`[0033] By incorporating one or more additional “Gm”
`stages When driving multiple output paths, the performance
`of the ampli?er circuit 100 may be maintained across differ
`ent output loads. Speci?cally, When driving tWo output paths
`simultaneously, a second transconductance stage is enabled
`to maintain substantially similar gain, Noise Figure (“NF”),
`linearity, and input impedance matching. In this example, the
`current generated by ampli?er circuit is increased by approxi
`mately tWo-times (2x) When driving both output paths OUT1
`and OUT2. HoWever, When current combiner circuit 103 is
`con?gured to couple current from transconductance stage
`101 to one of output path OUT1 or output path OUT2, second
`transconductance state 102 may be turned off. Accordingly, in
`this con?guration performance is similar to single output
`LNA and current is saved since the second transconductance
`
`

`

`US 2011/0217945 A1
`
`Sep. 8, 2011
`
`stage 102 is turned off. As illustrated in an example below,
`cascode devices may be turned off to disconnect current from
`transconductance stage 102 to OUT1 and OUT2, for
`example. Further, transconductance stage 101 may provide
`input matching. An example of input matching is described
`beloW.
`[0034] FIG. 2A shoWs an ampli?er circuit 200A according
`to one embodiment. Ampli?er circuit 200A is an NMOS LNA
`architecture With selectively enabled cascode output transis
`tors that route currents to either or both of output paths OUT1
`and OUT2. While an NMOS example is shoWn in FIG. 2A, it
`is to be understood that PMOS implementations are also
`possible. Ampli?er circuit 200A includes input transistors
`201-204 that act as parallel transconductance stages. For
`instance, gates of transistors 201 and 202 receive a differen
`tial signal having a ?rst component VN+ and a second com
`ponent VN—, respectively. Sources of transistors 201 and 202
`are coupled to a reference voltage (V ss) through inductors
`250 and 251, respectively. Transistors 201 and 202 convert
`VN+ and VN- to corresponding currents that are output on
`the drains of transistors 201 and 202. Transistors 201-202
`make up one transconductance stage to convert a differential
`input signal into corresponding currents. Inductors 250-251
`provide source degeneration and input matching to external
`?lters, for example. Inductors 250-251 may be a single induc
`tor With a center tap, for example.
`[0035] Analogously, gates of transistors 203 and 204 may
`receive the differential signal VN+ and VN—. Sources of
`transistors 203 and 204 are coupled to a reference voltage
`(Vss). Transistors 203 and 204 convert VN+ and VN- to
`corresponding currents that are output on the drains of tran
`sistors 203 and 204. Transistors 203-204 make up another
`transconductance stage to convert the differential input signal
`into corresponding currents.
`[0036] In this example, currents from the transconductance
`stages are received by a current combiner circuit 270A. Cur
`rent combiner circuit 270A is implemented With selectively
`enabled cascode NMOS transistors 205-212 to selectively
`couple currents from the transconductance stage transistors to
`either or both of output paths OUT1 and OUT2. Transistors
`205-206 have sources coupled to transistor 201. The drain of
`transistor 205 is coupled to output path OUT1 and the drain of
`transistor 206 is coupled to output path OUT2. Similarly,
`transistors 207-208 have sources coupled to transistor 202.
`The drain of transistor 207 is coupled to output path OUT1
`and the drain of transistor 208 is coupled to output path
`OUT2. Cascode transistors 205 and 207 may be selectively
`turned on or off by controlling voltage VN1 at the gate of
`transistor 205 and the gate of transistor 207, thereby coupling
`or decoupling current from transistors 201 and 202 from
`output path OUT1. Likewise, cascode transistors 206 and 208
`may be selectively turned on or off by controlling voltage
`VN2 at the gate of transistor 206 and the gate of transistor
`208, thereby coupling or decoupling current from transistors
`201 and 202 from output path OUT2.
`[0037] Current from the other transconductance stage tran
`sistors 203-204 may be similarly routed to the output paths
`OUT1 and OUT2. In this example, transistors 209-210 have
`sources coupled to transistor 203. The drain of transistor 209
`is coupled to output path OUT1 and the drain of transistor 210
`is coupled to output path OUT2. Similarly, transistors 211
`212 have sources coupled to transistor 204. The drain of
`transistor 211 is coupled to output path OUT1 and the drain of
`transistor 212 is coupled to output path OUT2.
`
`[0038] Particular embodiments couple current from
`transconductance stage transistors 203-204 to both output
`paths OUT1 and OUT2 When the ampli?er circuit is con?g
`ured to provide an output on both output paths OUT1 and
`OUT2.Accordingly, in this example, cascode transistors 209
`212 may be selectively turned on or off together by control
`ling voltage VNAux at the gate of each transistor 209-212,
`thereby coupling or decoupling current from transistors 203
`and 204 to or from output path OUT1 and output path OUT2.
`[0039] Speci?cally, transconductance stage transistors
`201-202 may be con?gured to couple current to both output
`paths OUT1 and OUT2 by providing VN1 andVN2 to turn on
`transistors 205-208. In this con?guration, VNAux is provided
`to turn on transistors 209-212 so that transconductance stage
`transistors 203-204 provides current to both output paths
`OUT1 and OUT2.
`[0040] Alternatively, VN1 and VN2 may be con?gured to
`selectively couple current from transistors 201-202 to either
`one of output path OUT1 or OUT2 (e.g., but not both). When
`only one output path is coupled to the transconductance stage
`transistors 201-202, NVAux is con?gured to turn off transis
`tors 209-212 to decouple current from transconductance tran
`sistors 203-204 from output paths OUT1 and OUT2.
`[0041] FIG. 2B shoWs an ampli?er circuit 200B according
`to one embodiment. Ampli?er circuit 200B is a “push-pull”
`LNA architecture With selectively enabled cascode output
`transistors that route currents to either or both of output paths
`OUT1 and OUT2. Ampli?er circuit 200B includes NMOS
`transistors 201-212 as described in FIG. 2A. Ampli?er circuit
`200B further includes PMOS transistors 221-232. Input tran
`sistors 221-224 that act as parallel transconductance stages.
`For instance, gates of transistors 221 and 222 receive a dif
`ferential signal having a ?rst component VP+ and a second
`component VP—, respectively. Sources of transistors 221 and
`222 are coupled to a reference voltage (V dd) through induc
`tors 252 and 253, respectively. Transistors 221 and 222 con
`vert VP+ and VP- to corresponding currents that are output
`on the drains of transistors 221 and 222.
`[0042] Transistors 221-222 make up one transconductance
`stage to convert a differential input signal into corresponding
`currents. Inductors 252-253 provide source degeneration and
`input matching for the circuit as described above With refer
`ence to inductors 250 and 251. Inductors 252-253 may be a
`single inductor With a center tap, for example. Analogously,
`gates of transistors 223 and 224 receive VP+ and VP—.
`Sources of transistors 223 and 224 are coupled to a reference
`voltage (Vdd). Transistors 223 and 224 convert VP+ and VP
`to corresponding currents that are output on the drains of
`transistors 223 and 224. Transistors 223-224 make up another
`transconductance stage to convert the differential input signal
`into corresponding currents.
`[0043] Currents from the NMOS and PMOS transconduc
`tance stages are received by a current combiner circuit 270B.
`In this example, current combiner circuit 270B is imple
`mented With selectively enabled cascode NMOS transistors
`205-212 as described in FIG. 2A and cascode PMOS transis
`tors 225-232 to selectively couple currents from the transcon
`ductance stage transistors to either or both of output paths
`OUT1 and OUT2. In this example, current from transistors
`221 and 222 is selectively routed to different output paths
`OUT1 and OUT2 using cascode transistors 225-228. For
`example, transistors 225-226 have sources coupled to tran
`sistor 221. The drain of transistor 225 is coupled to output
`path OUT1 and the drain of transistor 226 is coupled to output
`
`

`

`US 2011/0217945 A1
`
`Sep. 8, 2011
`
`path OUT2. Similarly, transistors 227-228 have sources
`coupled to transistor 222. The drain of transistor 227 is
`coupled to output path OUT1 and the drain of transistor 228
`is coupled to output path OUT2. Cascode transistors 225 and
`227 may be selectively turned on or off by controlling voltage
`VP1 at the gate of transistor 225 and the gate of transistor 227,
`thereby coupling or decoupling current from transistors 221
`and 222 from output path OUT1. Likewise, cascode transis
`tors 226 and 228 may be selectively turned on or off by
`controlling voltage VP2 at the gate of transistor 226 and the
`gate of transistor 228, thereby coupling or decoupling current
`from transistors 221 and 222 from output path OUT2.
`[0044] Current from the other PMOS transconductance
`stage transistors 223-224 may be similarly routed to the out
`put paths OUT1 and OUT2. In this example, transistors 229
`230 have sources coupled to transistor 223. The drain of
`transistor 229 is coupled to output path OUT1 and the drain of
`transistor 230 is coupled to output path OUT2. Similarly,
`transistors 231-232 have sources coupled to transistor 224.
`The drain of transistor 231 is coupled to output path OUT1
`and the drain of transistor 232 is coupled to output path
`OUT2.
`[0045] Particular embodiments couple current from
`transconductance stage transistors 203-204 and 223-224 to
`both output paths OUT1 and OUT2 When the ampli?er circuit
`is con?gured to provide an output on both output paths OUT1
`and OUT2. Accordingly, in this example, cascode transistors
`209-212 may be selectively turned on or off together by
`controlling voltage VNAux at the gate of each transistor 209
`212 as described above With regard to FIG. 2A. Likewise,
`cascode transistors 229-232 may be selectively turned on or
`off together by controlling voltage VPAux at the gate of each
`transistor 229-232, thereby coupling or decoupling current
`from transistors 223 and 224 to or from output path OUT1 and
`output path OUT2. Transconductance stage transistors 221
`222 may be con?gured to couple current to both output paths
`OUT1 and OUT2 by providing VP1 and VP2 to turn on
`transistors 225-228. In this con?guration, VPAux is provided
`to turn on transistors 229-232 so that transconductance stage
`transistors 223-224 provides current to both output paths
`OUT1 and OUT2.
`[0046] Alternatively, VP1 and VP2 may be con?gured to
`selectively couple current from transistors 221-222 to either
`one of output path OUT1 or OUT2 (e.g., but not both). When
`only one output path is coupled to the transconductance stage
`transistors 221-222, PNAux is con?gured to turn off transis
`tors 229-232 to decouple current from transconductance tran
`sistors 223-224 from output paths OUT1 and OUT2.
`[0047] FIG. 3 shoWs another ampli?er circuit according to
`one embodiment. In this example a loW noise ampli?er
`(LNA) includes tWo transconductance stages 301 and 302 and
`a current combiner circuit 303 that operate as described
`above. In this example, an RF signal is received on antenna
`350. Antenna 350 is coupled to the inputs of transconductance
`stages 301 and 302 through a ?lter 351 and a matching net
`Work 352. The RF signal may include tWo channels encoded
`around tWo different carrier frequencies (i.e., dual carriers),
`for example. The dual carrier signal may be ampli?ed by
`transconductance stages 301 and 302 and coupled to tWo
`mixers 304 and 305 on tWo different output paths by current
`combiner circuit 303. Mixer 304 may receive the dual carrier
`signal and a local oscillator signal having a frequency equal to
`one of the tWo carriers in the RF signal (i.e., LOl). Accord
`ingly, mixer 304 doWn converts one of the channels of the RF
`
`signal to baseband. Similarly, mixer 305 may receive the dual
`carrier signal and another local oscillator signal having
`another frequency equal to the other of the tWo carriers in the
`RF signal (i.e., L02). Accordingly, mixer 305 doWn converts
`the other channel of the RF signal to baseband. In this
`example, mixers 304 and 305 are quadrature mixers having
`four outputs each. Mixer 304 outputs differential in-phase (I)
`and quadrature (Q) signals on output path 306 (OUT1) and
`mixer 305 outputs differential I and Q signals on output path
`307 (OUT2).
`[0048] FIG. 4 shoWs a system 400 using an ampli?er circuit
`according to one embodiment. System 400 is an example of
`an implementation of an Evolved EDGE Wireless system.
`Enhanced Data rates for GSM Evolution (“EDGE”) (also
`knoWn as Enhanced GPRS (EGPRS) or Enhanced Data rates
`for Global Evolution) is a digital mobile phone technology
`that enables data transmission across Wireless netWorks such
`as GSM. In this example, system 400 includes an antenna 401
`to receive a dual carrier RF signal. The RF signal is routed to
`one of four input channels using sWitches 402. Each input
`channel includes a ?lter 403A-D, such as a surface acoustic
`Wave (SAW) ?lter, matching netWork 404A-D, and LNA
`405A-D. Each LNA provides the appropriate input imped
`ance match to the matching netWork and ?lters (e.g., 50
`Ohms). For example, Gm1 of each LNA provides input
`matching to an external SAW ?lter. The four different chan
`nels depicted in FIG. 4 may correspond to GSM850,
`GSM900, DCS, and PCS technologies, for example, With
`each channel con?gured to support the particular dual carrier
`frequencies corresponding to each technology.
`[0049] Outputs of LNAs 405A-D are multiplexed to tWo
`different doWn conversion and baseband processing circuits
`407 and 408. Multiplexer (“MUX”) 406 illustrates the selec
`tive coupling of LNA outputs to the tWo doWn converters
`using the current combiner circuits of each LNA as illustrated
`above, for example. DoWn conversion and baseband process
`ing circuits 407 and 408 may include additional ?lters 471
`and 481, respectively, and analog-to-digital converters
`(ADCs) 472 and 482, respectively, for translating the infor
`mation in each channel of the RF signal into digital data. As
`illustrated in FIG. 4, the LNAs 405A-D and doWn conversion
`and baseband processing circuits 407-408 may be imple
`mented on an RF transceiver integrated circuit 450, for
`example.
`[0050] FIG. 5 illustrates a process according to one
`embodiment. At 501, an RF signal is received in a ?rst
`transconductance stage. At 502, the RF signal is received in a
`second transconductance stage. At 503, the currents from the
`transconductance stage are combined in a current combiner
`circuit. The RF signal may include one or tWo channels (i.e.,
`single or dual carrier) as illustrated at 504. If the RF signal is
`a single carrier, then the process couples currents from the
`?rst transconductance stage to a particular output path and
`decouples currents from the second transconductance stage
`from the particular output path at 505. As mentioned above,
`decoupling current may include turning the second transcon
`ductance stage off, for example. If the RF signal is a dual
`carrier, then the process couples currents from the ?rst and
`second transconductance stages to tWo output paths for fur
`ther processing at 506.
`[0051] The above description illustrates various embodi
`ments of the present invention along With examples of hoW
`aspects of the present invention may be implemented. The
`above examples and embodiments should not be deemed to
`
`

`

`US 2011/0217945 A1
`
`Sep. 8, 2011
`
`be the only embodiments, and are presented to illustrate the
`?exibility and advantages of the present invention as de?ned
`by the following claims.
`[0052] For example, While the some of the above embodi
`ments have been disclosed using PMOS and NMOS, other
`embodiments may use other types of transi