` A0 120 Rev. OS/IO
`
`REPORT ON THE
`
`
`T0
`Mail Stop 8
`FILING OR DETERMINATION OF AN
`'
`Director of the US. Patent and Trademark Office
`ACTION REGARDING A PATENT OR
`
`
`P.O. Box 1450
`TRADEMARK
`
`
`Alexandria, VA 22313-1450
`
`
`
`In Compliance with 35 U.S.C. § 290 and/or l5 U.S.C. § ll 16 you are hereby advised that a court action has been
`filed in the U.8. District Court
`The Eastern District of Texas, Marshall Division
`on the following
`E] Trademarks or M Patents.
`( E] thepatent action involve5735 U.S.C. § 292.):
`
`DOCKET NO.
`DATE FILED
`U.S. DISTRICT COURT
`2:15-00948
`6/5/2015
`The Eastern District of Texas, Marshall Division
`
`
`
`
`PLAINTIFF
`DEFENDANT
`KONINKLIJKE KPN N.V.
`SAMSUNG ELECTRONICS CO, LTD..
`
`
`SAMSUNG ELECTRONICS AMERICA, INC., &
`SAMSUNG TELECOMMUNICATIONS AMERICA, INC.
`
`
`TRADEMARK NO.
`OR TRADEMARK
`PATENT OR
`DATE OF PATENT
`1 9,014,667
`
`.‘
`
`e
`
`HOLDER OI PATENT OR TRADEMARK
`Koninklijke KPN N.V.
`
`.
`
`
`
`1n the above—(entitled case, the following patcnttsy trademarkts) have been included:
`
`DATE INCLUDED
`
`PATENT OR
`
`TRADEMARK NO.
`
`INCLUDED BY
`
`El Amendment
`OR TRADEMARK
`
`DATE OF PATENT
`
`I] Answer
`[I Cross Bill
`C] Other Pleading
`HOLDER OI" PATENT OR TRADEMARK
`
`.
`
`In the aboverrrrrrrentitled case, the following decision has been rendered or judgement issued:
`DECISION/JUDGEMENT
`
`Order dismissed case with prejudice
`
`
`
`
`DAT3/23/16
` (BY) DEPUTY CLERK
`
`ch
`
`Copy l—Upon initiation of action, mail this copy to Director Copy 3—Upon termination of action, mail this copy to Director
`Copy 2—Upon filing document adding patent(s), mail this copy to Director Copy 4-—Case file copy
`
`Page 1 of 778
`
`HTC EXHIBIT 1002
`
`1
`
`HTC EXHIBIT 1002
`
`Page 1 of 778
`
`
`
`Case 1:17-cv-00082-LPS-CJB Document 3 Filed 01/30/17 Page 1 of l PageID #: 90
`A0 120 (Rev. 0-710“;
`
`TO:
`
`Mail Stop 8
`Director of the U.8. Patent and Trademark Office
`RU. Box 1450
`Alexandria, VA 22313-1450
`
`TRADER/{ARK
`
`REPORT ON THE
`FILING OR DETERNHENATION OF AN
`ACTION REGARDING A PATENT OR
`
`i6 you are hereby advised that a court action has been
`in Compliance with 35 US$11 § 290 and/or i5 USE. § 1
`
`filed in the US, District Court
`FOR THE DiSTRiCT OF DELAWARE
`on the following
`
`E 'i‘rademanis or E Potentst
`
`( C the patent action involves 35 U.S.C. § 292.}:
`
`DOCKET NO.
`
`l’LAlNTEFF
`
`DATE FELED
`1/30/2017
`
`' US. DISTRICT COURT
`.
`FOR THE DESTRSCT OF DELAWARE
`DEFENDANT
`
`36 LiCENSlNG, 3A., and KONlNKLiJKE KF’N NV.
`
`BLACKBERRY Liivil'i'ED AND BLACKBERRY
`CORPORATEON
`
`PATENT DR
`TRADEMARK ND.
`
`DATE OF PATENT
`OR TRADEMARK
`
`‘F
`I,‘
`.
`HOLDER OF PATENT OR T
`
`I
`
`EMARK
`
`DATE INCLUDED
`
`In the ahoy'eientitled case, the following pate11t(3)/ trademarfls) have been included:
`INCLUDED BY
`
`PATENT OR
`TRADEMARK NO.
`
`DATE OF PATENT
`
`E Cross Bi‘il
`
`C] Other Pleading
`
`
`QR TRADEMARK
`
`
`in the abm'ewrentitled case. the following decision has been rendered or judgement issued:
`DECISION/JUDG EMENT
`
`CLERK
`
`(B Y) DEPUTY CLERK
`
`DATE
`
`Copy i—---Upon initiation of action. mail this: copy to Director Copy 3------Upon termination oi’action, moii this copy to Director
`Copy 2-----Llpon filing document adding potenti'sfi mail this copy to Director Copy 4----- Case fiie copy
`
`Page 2 of 778
`
`2
`
`2
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`Page 2 of 778
`
`
`
`Case 1:17-cv-00083-LPS-CJB Document 3 Filed 01/30/17 Page 1 of l PageID #: 90
`A0 120 (Rev. 0-710“;
`
`'10:
`
`Mail Stop 8
`Director of the U.8. Patent and Trademark Office
`HO. Box 1450
`Alexandria, VA 22313-1450
`
`TRADER/{ARK
`
`REPORT ON THE
`FILING OR DETERNHENATION OF AN
`ACTION REGARDING A PATENT OR
`
`i6 you are hereby advised that a court action has been
`in Compliance with 35 US$11 § 290 and/or i5 USE. § 1
`
`filed in the US, District Court
`FOR THE DiSTRiCT OF DELAWARE
`on the following
`
`E 'i‘rademanis or E Potentst
`
`( C the patent action involves 35 U.S.C. § 292.}:
`
`DOCKET NO.
`
`PLAINTEFF
`
`DATE EELED
`1/30/2017
`
`. Us. DlSTRlCT COURT
`.
`FOR THE DESTRSCT OF DELAWARE
`DEFEN DANT
`
`36 LiCENSlNG, 8A., and KONlNKLiJKE KF’N NV.
`
`HTC CORPORATTON and HTC AMERECA, ENC.
`
`PATENT DR
`TRADEMARK ND.
`
`DATE OF PATENT
`OR TRADEMARK
`
`‘F
`I,‘
`.
`HOLDER OF PATENT OR T
`
`I
`
`EMARK
`
`DATE INCLUDED
`
`In the ahoy'eientitled case, the following pate11t(3)/ trademarfls) have been included:
`INCLUDED BY
`
`PATENT OR
`TRADEMARK NO.
`
`DATE OF PATENT
`
`E Cross Bi‘il
`
`C] Other Pleading
`
`
`QR ‘T‘RADEM ARK
`
`
`in the abm'ewrentitled case. the following decision has been rendered or judgement issued:
`DECISION/JUDG EMENT
`
`CLERK
`
`(B Y) DEPUTY CLERK
`
`DATE
`
`Copy i—---Upon initiation of action. mail this: copy to Director Copy 3------Upon termination oi’action, moii this copy to Director
`Copy 2-----Llpon filing document adding potenti'sfi mail this copy to Director Copy 4----- Case fiie copy
`
`Page 3 of 778
`
`3
`
`3
`
`Page 3 of 778
`
`
`
`Case 1:17-cv-00084-LPS-CJB Document 3 Filed 01/30/17 Page 1 of l PageID #: 91
`A0 120 (Rev. 0-710“;
`
`'10:
`
`Mail Stop 8
`Director of the U.8. Patent and Trademark Office
`HO. Box 1450
`Alexandria, VA 22313-1450
`
`TRADER/{ARK
`
`REPORT ON THE
`FILING OR DETERNHENATION OF AN
`ACTION REGARDING A PATENT OR
`
`i6 you are hereby advised that a court action has been
`in Compliance with 35 US$11 § 290 and/or i5 USE. § 1
`
`filed in the US, District Court
`FOR THE DiSTRiCT OF DELAWARE
`on the following
`
`E 'i‘rademanis or E Potentst
`
`( C the patent action involves 35 U.S.C. § 292.}:
`
`DOCKET NO.
`
`l’LAlNTEFF
`
`DATE FELED
`1/30/2017
`
`' US. DISTRICT COURT
`.
`FOR THE DESTRSCT OF DELAWARE
`DEFENDANT
`
`36 LiCENSlNG, 8A., and KONlNKLiJKE KF’N N.V.
`
`LENOVO GROUP LTD, LENOVO HOLDENG CO, and
`LENOVO (UNETED STATES) iNC.
`
`PATENT DR
`TRADEMARK ND.
`
`DATE OF PATENT
`OR TRADEMARK
`
`‘F
`I,‘
`.
`HOLDER OF PATENT OR T
`
`I
`
`EMARK
`
`
`QR TRADEMARK
`
`
`DATE INCLUDED
`
`In the ahoy'eientitled case, the following pate11t(3)/ trademarfls) have been included:
`INCLUDED BY
`
`PATENT OR
`TRADEMARK NO.
`
`DATE OF PATENT
`
`E Cross Bi‘il
`
`C] Other Pleading
`
`in the abm'ewrentitled case. the following decision has been rendered or judgement issued:
`DECISION/ll_lDG EMENT
`
`CLERK
`
`(B Y) DEPUTY CLERK
`
`DATE
`
`Copy i—---Upon initiation of action. mail this: copy to Director Copy 3------Upon termination oi’action, moii this copy to Director
`Copy 2-----Llpon filing document adding potenti'sfi mail this copy to Director Copy 4----- Case fiie copy
`
`Page 4 of 778
`
`4
`
`4
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`Page 4 of 778
`
`
`
`Case 2:15-cv-00948-JRG Document 22 Filed 09/23/16 Page 1 of 1 PagelD #: 80
`A0 120 (Rev. 3I’M}
`
`TO:
`
`Mail Stop 8
`Director {If the US. Patent and Trademark ()ffiee
`RU. Box 1450
`Alexandria, VA 2213134450
`
`'I‘RKDE'MARK
`
`REPORT ON THE
`F! L! NG OR I) E'I'ERIM EN ATEGN 0F AN
`ACTION REGARDING A PATENT OR
`
`III (Umpiianee VV!I211 35 T SC$290 and/0r 1517SC. § 1! 16 yIIu areiIHereby ad‘viseti that a (mm at:EIOI. has been
`
`fliedII] the US DistIICt Court
`The Eastern District Of Texas, Marsha“ Division
`011 the following
`
`D Trademarks (Ir
`
`MPatems.
`
`( E the patent action Involves 35 U.S.C. § 292.):
`
`DOCKET NO.
`2115430948
`PLAINTIFF
`
`“
`DATE FILED
`SKI/201::
`
`I US. DISTRICT COURT
`.
`The Eastern District of Texas, Marsha” Division
`DEFENDANT
`
`KONINKLIJKE KPN N.V.
`
`SAMSUNG ELECTRONICS CO, LTD..
`3 SAMSUNG ELECTRONECS AMERICA. WC, 8:
`SAMSUNG TELECOMMUNICATEONS AMERICA, INC.
`
`PATENT OR
`TRADEMARK Nt')
`
`D’XTF OF PATFNT
`OR TRADEMARK
`
`m
`HOLDER OF PA ENT OR T
`
`R E
`
`EMAR
`
`9, 0: 4, 667
`
`4"21/20’15
`
`Koninkiijke KPN NV
`
`INCLUDED BY
`
`1: Amendment
`
`1: Answer
`
`I: Cress Bill
`
`D Other PieaIIII‘Ig
`
`In the abI‘I.e-----eIII-ItIed case the fOHOWIIzg deI':iSIOi] has been reIIdeed 01' i-IIdgemeutIssuwed
`DECISION/KIDS EMENT
`
`Order dismissed case with prejudice
`
`DATF9/23/16
`
`(BY! DEPUTY CLERK
`gh
`
`(‘1pr 3------Ugmn termination of aetirm, maii this crspy m Directm‘
`Copy i—---Upam initiation (If actiam, maii this eaypy tn Direemr
`(‘Iipy 2 -----Upon filing decument adding pzatentfls), wait this eepy t0 Direetuur Cepy 4------Case fiIe C(Ipy
`
`Page 5 of 778
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`5
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`5
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`Page 5 of 778
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`
`
`us to. 0v
`Trials
`571-272-7822
`
`Paper 17
`Entered: September 28, 2016
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`SAMSUNG ELECTRONICS CO., LTD.,
`
`MICRON TECHNOLOGY, INC., and
`
`SK HYNIX, INC,
`
`Petitioner,
`
`V.
`
`ELM 3DS INNOVATIONS, LLC,
`Patent Owner.
`
`Case [PR2016-00708
`
`Patent 8,907,499 B2
`
`Before GLENN J. PERRY, BARBARA A. BENOIT, and
`FRANCES L. IPPOLITO, Administrative Patent Judges.
`
`PERRY, Administrative Patent Judge.
`
`DECISION
`
`Institution of Inter Partes Review
`
`37 CFR. § 42.108
`
`Page 6 of 778
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`6
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`6
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`Page 6 of 778
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`
`
`IPR2016-00708 ’
`
`Patent 8,907,499 B2
`
`1. INTRODUCTION
`
`This is a preliminary proceeding to decide whether‘interpartes review
`
`of US. Patent No. 8,907,499 B2 (Ex. 1001, “the ’499 patent” or “the
`
`challenged patent”) should be instituted under 35 U.S.C. §314(a). Upon
`consideration of the Petition and the Preliminary Response, we conclude the.
`information presented demonstrates that there is a reasonable likelihood that ,
`Petitioner would prevail in establishing the unpatentability of at least one of .
`
`the challenged claims of the challenged patent. This is not a final written
`I
`
`decision under 35 U.S.C § 318(a) and 37 C.F.R. § 42.73.
`
`A
`
`A. Procedural Posture
`
`Samsung Electronics, Inc., Micron Technology, Inc. and SK Hynix
`Inc. (collectively “Petitioner”) filed a Petition (Paper 4, “Pet.”) seeking inter
`partes review of claims 1 and 49 of the "499 patent. Patent Owner, Elm 3DS
`Innovations, LLC, filed a Preliminary Response to the Petition (Paper 14,
`“Prelim. Resp”). We have jurisdiction under 35 U.S.C. § 314(a), which
`
`provides that inter partes review may not be instituted “unless .
`
`.
`
`. the
`
`information presented in the petition .
`.
`. and any response .
`.
`. shows that
`there is a reasonable likelihood that the petitioner would prevail with respect
`
`to at least 1 of the claims challenged in the petition.”
`
`' B. Related Proceedings ‘
`
`I
`
`As required by 37 C.F.R. § 42.8(b)(2), each party identifies various
`
`judicial or administrative matters that would affect or be affected by a
`
`Page 7 of 778
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`7
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`Page 7 of 778
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`
`
`[PR2016-00708
`
`.Patent 8,907,499 B2
`
`decision in this proceeding. Pet. 1—2; Paper 6 (Patent Owner’s Mandatory
`
`Notices). Petitioner indicates that Patent Owner has asserted the challenged
`
`patent against Petitioner in the following United States District Court
`
`proceedings: Elm 3DS Innovations, LLC v. Samsung Elecs. Co., No. 1:14-
`
`cv-01430 (D. Del.); Elm 3DS Innovations, LLC v. Micron Tech, Inc., No.
`1:14-cv-01431 (D. Del.); and Elm 3DS Innovations, LLC v. SK hynix Inc,
`No. 1:14-cv-01432 (D. Der). {Pet. 1.
`Petitioner also indicates that Patent Owner has asserted related US.
`
`Patent Nos. 7,193,239; 7,474,004; 7,504,732; 8,035,233; 8,410,617;
`8,653,672; 8,791,581; 8,629,542; 8,841,778; 8,496,862; 8,928,119; and
`
`8,933,570 in one or more of these actions. Pet. 2
`Petitioner further indicates that it has already requested interpartes
`review of the following patents: 7,193,239 (IPR2016-00388 and IPR2016-
`
`00393); 7,504,732 (IPR2016-00395); 8,629,542 (IPR2016—00390);
`
`8,035,233 ([PR2016-00389); 8,410,617 (IPR2016—00394); 8,653,672
`
`([PR2016-00386); 8,796,862 (IPR201_6-00391); 8,841,778 (IPR2016- -
`00387); 8,928,119 (IPR2016-00687); and 7,474,004 (IPR2016—00691). Id.
`
`Petitioner also indicates that Micron Technology, Inc. and SK Hynix
`
`Inc. have already requested inter partes review of 8,791,581 (IPR2016—
`
`00703 and IPR2016-00706). Id.
`
`Petitioner further indicates that it is also concurrently filing another
`
`petition requesting inter partes review for other claims of the ’499 patent. .
`\
`
`Pet. 2.
`
`Page 8 of 778
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`8
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`Page 8 of 778
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`
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`IPR2016-00708
`
`Patent 8,907,499 B2
`
`C. The Challenged Patent
`
`1. Described Invention
`
`The ’499 patent relates generally to a three-dimensional structure
`
`(3DS) for integrated circuits that allows for physical separation of memory
`
`circuits and control logic circuits on different layers. Ex. 1001, Abstract.
`
`Figure 1a is reproduced below.
`
`
`
`Figure 1a
`
`Figure 1a shows three-dimensional memory device 100 having a stack
`
`of integrated circuit layers with a “fine—grain inter-layer vertical
`
`interconnect” between all circuit layers. Id. at 424—18. Layers shown
`
`include controller circuit layer 101 and memory array circuit layers 103. Id.
`
`at 4:25—27. The challenged patent discloses that “each memory array circuit
`
`layer is a thinned and substantially flexible circuit with net low stress, less
`
`than 50 [um] and typically less than 10 [pm] in thickness.” Id. at 4:30—33.
`
`The challenged patent further discloses that the “thinned (substantially
`
`4
`
`Page 9 of 778
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`9
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`Page 9 of 778
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`IPR2016-00708
`
`Patent 8,907,499 B2
`
`flexible) substrate circuit layers are preferably made with dielectrics in low
`
`stress (less than 5X108 dynes/cmz) such as low stress silicon dioxide and
`
`silicon nitride dielectrics as opposed to the more commonly used higher
`
`stress dielectrics of silicon oxide and silicon nitride used in conventional
`
`memory circuit fabrication.” Id at 8:54—59.
`
`Figure 1b is reproduced below.
`
`H5:
`
`(I, Ill
`'II [III ’A
`10‘
`
`
`
`
`(I [Ill
`7 [III/5, A
`'\.___m.
`
`
`A
`
`VIII/ll
`Illllllllnllm
`””llllllllnl
`VIII/ll
`
`
`
`
`
`’Illl’llll’IlIll.
`W’ll’l
`”Ill" llllllllllllll.‘
`
`
`
`:(u
`
`Figure 113
`
`Figure lb of the challenged patent shows a cross-section of a three-
`
`dimensional integrated circuit with metal bonding interconnect between
`
`thinned circuit layers. Id. at 3:45—47. Bond and interconnect layers 105a,
`
`105b, 105c are shown between circuit layers 103a and 103b. Id. at Fig. lb.
`
`The challenged patent discloses that pattern 107a, 107b, 1070 in the bond
`
`and interconnect layers 105a, 105b, 1050 defines the vertical interconnect
`
`contacts between the integrated circuit layers and serves to electrically
`
`isolate these contacts from each other and the remaining bond material. Id
`
`at 4:19—24. Additionally, the challenged patent teaches that the pattern takes
`
`Page 10 of 778
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`10
`
`10
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`Page 10 of 778
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`
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`IPR2016—00708
`
`Patent 8,907,499 B2
`
`the form of voids or dielectric filled spaces in the bond layers. Id. at 4:22—
`
`24.
`
`Further, the challenged patent teaches that the “term fine-grained
`
`inter-layer vertical interconnect is used to mean electrical conductors that
`
`pass through a circuit layer with or without an intervening device element
`
`and have a pitch of nominally less than 100 [um]. .
`
`. .” Id. at 4:7—10. The
`
`fine-grain inter—layer vertical interconnect functions to bond together various
`
`circuit layers. Id. at 4:13—14.
`
`2. Illustrative Claim
`
`Of the challenged claims, claim 1 is independent and claim 49
`
`depends from claim 1. Claim 1 is illustrative of the claimed subject matter:
`
`1. A thin and substantially flexible structure comprising:
`
`flexible monocrystalline
`substantially
`and
`thin
`a
`semiconductor layer of one piece; and
`
`a silicon-based dielectric layer
`semiconductor
`layer
`and having a
`5 x 108 dynes/cm2 tensile.
`
`formed on the thin
`stress of
`less
`than
`
`Ex. 1001, 12:62—67.
`
`D. The Asserted Grounds of Unpatentabilz'ty
`
`Petitioner contends that challenged claims are unpatentable under
`
`35 U.S.C. § 103 based on the following specific grounds (Pet. 3—4, 21—60):
`
`Page 11 of 778
`
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`
`11
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`Page 11 of 778
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`
`
`IPR2016- 00708
`
`r
`
`Patent 8, 907,499 B2
`
`
`
`
`
`Claim
`
`Hsu and Leedy ’6952
`Hsu, Leedy ’695 and Sakuta3
`
`Bertin ’945,4 Leedy ’695, and Poole5
`
`Bertin ’945, Leedy ’695, and Poole, and
`Sakuta
`
`. Hsu and Kowa,6
`
`
`
`
`
`
`
`
`Hsu, Kowa and Sakuta
`
`Bertin ’945 and Leedy ’695
`
`Bertin ’945, Leedy ’695, and Sakuta
`
`
`
`11. DISCUSSION
`
`A. Claim Constniction
`
`
`
`
`
`We interpret claims of an unexpired patent using the “broadest
`
`- reasonable construction in light of the Specification of the patent in which
`
`[the claims] appear[]-.” 37 C.F.R. § 42.100(b); see Cuozzo Speed Techs.,
`cLLC v. Lee, 136 S. Ct. 2131, 2144 (2016) (concluding the broadest
`
`reasonable construction “regulation represents a reasonable exercise of the
`
`1 US Patent No. 5,627,106, issued May 6, 1997 (Ex. 1008, “Hsu”).
`2 US. Patent No. 5,354,695, issued Oct. 11, 1994 (Ex. 1006, “Leedy ’695”).
`3 US. Patent No. 5,208,782, issued May 4, 1993 (Ex. 1067, “Sakuta et a1”).
`4 US. Patent No. 5,731,945, issued Mar. 24, 1998 (Ex. 1073, “Bertin et
`al. ’945”).
`5 US. Patent No. 5,162,251, issued Nov. 10, 1992 (Ex. 1005, “Poole et al.”).
`6 JP Patent Application Publication No. H3-151637, published June 27, 1991
`(EX. 1007, “Kowa et al.”). Petitioner has provided a certified English
`translation. Ex. 1007, 13.
`
`7
`
`Page 12 of 778
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`IPR2016-00708
`
`Patent 8,907,499 B2
`
`‘
`
`_'
`
`‘
`
`rulemaking authOrity that Congress delegated to the Patent Office”). Under
`
`that standard, claim terms are presumed to be given their ordinary and
`
`customary meaning as would be understood by one of ordinary skill in the
`
`- art in the context of the entire disclosure. In addition, the Board may not
`
`“construe claims during inter partes review so broadly that its constructions
`
`are unreasonable under general claim construction principles.” Microsoft
`
`Corp. v. Proxyconn, Inc, 789 F.3d 1292, 1298 (Fed. Cir. 2015).
`
`1. “substantiallyflexible monocrystalline semiconductor layer ”
`
`Petitioner suggests that in light of the specification and intrinsic
`
`record of the ’499 patent, the broadest reasonable construction of -
`
`< “substantially flexible” when used to modify “semiconductor layer” is “a
`
`semiconductor layer that has been thinned to a thickness of less than 50 um
`
`and subsequently polished or smoothed.” Pet. 8—1 1.
`
`In light of the Specification of the ’499 patent, we preliminarily
`
`construe “substantially flexible monocrystalline semiconductor layer”
`
`consistent with our prior preliminary construction of “substrate is
`
`substantially flexible” (see IPR2016-00390, Paper 13, 9—1 1) as “a
`monocrystalline semiconductor layer that has been thinned to a thickness of
`less than 50 um.”
`
`2. ”substantiallyflexible structure ”
`
`Petitioner suggests that we construe “substantially flexible structure”
`
`as “a structure having a semiconductor substrate that has been thinned to a
`
`Page 13 of 778
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`
`13
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`thickness of less than 50 um and subsequently polished or smoothed, and
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`where the dielectric material used in processing the semiconductor substrate
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`must have a stress of 5X 108 dynes/cm2 tensile or less.” Pet. 12—14.
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`Patent Owner argues that Petitioner’s proposed construction is
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`“irrelevant” to this proceeding in that Petitioner asserts that the two
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`challenged claims are unpatentable under both Petitioner’s construction and
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`Patent Owner’s likely construction. Pet. at 14. Thus, Petitioner has
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`acknowledged that this claim term is not determinative of unpatentability.
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`Prelim. Resp. 9. We are, therefore, urged by Patent Owner to decline to
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`construe this term and to give it its plain and ordinary meaning for purposes
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`of this proceeding. Prelim. Resp. 10.
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`In light of the Specification of the ’499 patent, we preliminarily
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`construe “substantially flexible structure” consistent with our prior
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`preliminary construction of “substrate is substantially flexible” (see e. g.
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`IPR2016-00390) as “a structure having a semiconductor substrate that has
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`been thinned to a thickness of less than 50 um.”
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`B. Principles ofLaw
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`A claim is unpatentable under 35 U.S.C. § 103 (a) if the differences
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`between the subject matter sought to be patented and the prior art are such
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`that the subject matter as a whole would have been obvious at the time the
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`invention was made to a person having ordinary skill in the art to which said
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`subject matter pertains. KSR Int ’1 Co. v. Teleflex Inc., 550 US. 398, 406
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`(2007). The question of obviousness is resolved on the basis of underlying
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`factual determinations, including: (1) the scope and content of the prior art;
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`"
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`(2) any differences between the claimed subject matter and the prior art;
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`. (3) the level of skill in'the art; and (4) objective evidence of nonobviousness,
`i.e., secondary considerations. See Graham v. John Deere Co., 383 U.S. 1,
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`I
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`17—18 (1966). We analyze the challenge presented in the Petition in
`accordance withthese principles.
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`C. Level of Ordinary Skill in the Art
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`In determining whether an invention would have been obvious at the
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`I
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`time it was made, we consider the level of ordinary skill in the pertinent art
`at the time of the invention. Graham, 383 U.S. at 17. “The importance of
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`resolving the level of ordinary skill in the art lies in the necessity of
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`_
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`maintaining objectivity in the obviousness inquiry.” Ryko Mfg. Co. v. Nu-
`Star, Inc, 950 F.2d 714, 718 (Fed. Cir. 1991).
`-
`Petitioner’s declarant, Paul D. Franzon, PhV.D.,' opines that one of
`ordinary skill in the art relevant to the challenged patent l‘would have had at
`least a B.S. degree in electrical engineering, material science, or equivalent
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`I
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`thereof, and at least 3—5 years of experience in the relevant field, e. g.,
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`semiconductor processing.” Ex. 1002 11 58; see Pet. 6—7 (relying on
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`BX. 1002 11 58). Patent Owner does not offer any contrary explanation"
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`regarding who would qualify as a person of ordinary skill in the art relevant
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`to the challenged patent. See generally Prelim. Resp.
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`Based on our review of the challenged patent, the types of problems
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`i and solutions described in the challenged patent and cited prior art, and the
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`Q
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`testimony of Petitioner’s Declarant, we adopt and apply Petitioner’s
`definition of a person of ordinary skill in the art at the time of the claimed
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`invention. We note that the applied prior art reflects the appropriate level of
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`. skill at the time of the claimed invention. See Okajima v. Bourdeau, 261
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`F.3d 1350, 1355 (Fed. Cir. 2001).
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`D. Summaries ofthe Prior Art References
`Our understanding of the various prior art references relied upon by
`H
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`Petitioner is set forth in the following summaries.
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`1. Summary ofHsu (Ex. 1008)
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`Hsu is a United States patent that relates generally to a “method of
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`connecting three-dimensional integrated circuit chips using trench
`~ technology.” Ex._ 1008, Abstract, 1:8—1 1. Referring to Figures 2—8, Hsu’s
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`fabrication process starts with etching deep trenches 16 on silicon
`substrate 10,1which Hsu indicates can be composed of monocrystalline
`silicon. Id. at 2:50—61. I-lsu’s integrated circuits consist of “one master chip
`and some subordinate chips.” Id. at 1:20—21. According Hsu, the master
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`chip and subordinate chip each consist of a semiconductor substrate,
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`preferably composed of monocrystalline silicon. Id. at 2:51—54, 3:42—45.
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`These chips can be “stacked by interconnection through [a] ,pad.window
`[. .
`.] during integrated circuit processing.” Id. at 1:28—31. Hsu further
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`describes that the “bottom surface of the [subordinate] substrate is ground
`and polished so that only a thin portion of the substrate remains.“ Id.
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`at 3:21-23.
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`2. Summary ofLeedy ’695 (Ex. 1006)
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`Leedy ’695 is a United States patent that describes fabrication of
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`integrated circuits and interconnect metallization structures from membranes
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`of dielectric and semiconductor materials. Ex. 1006, 1:38—41. In its
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`Abstract, Leedy indicates that the disclosed integrated circuits are fabricated
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`from flexible membranes “formed of very thin low stress dielectric
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`materials, such as silicon dioxide or silicon nitride, and semiconductor
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`layers.” Id. at Abstract. Leedy describes forming a “tensile low stress
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`dielectric membrane” on a semiconductor layer as part of its integrated
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`circuit structure. Id. at 1:53—58. Leedy defines “[l]ow stress .
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`.
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`. relative to
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`the silicon dioxide and silicon nitride deposition made with the Novellus
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`equipment as being less than 8 x 108 dynes/cm2 (preferably 1 x 107
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`dynes/cmz) in tension.” Id. at .l 1 :33—37. Additionally, Leedy discloses two
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`chemical vapor deposition (CVD) process recipes for manufacturing
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`“structurally enhanced low stress dielectric circuit membranes.” Id. at
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`l 1 :51—65.
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`Referring to Figure 8, Leedy discloses a three dimensional circuit
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`membrane. Id. at 4:43. Figure 8 is reproduced below.
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`Leedy ’695, Figure 8 shows a three dimensional
`circuit membrane. EX. 1006, 4:42.
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`Figure 8 shows the vertical bonding of two or more circuit membranes
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`to form a three dimensional circuit structure. Id. at 16:3 8—40.
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`Interconnection between circuit membranes 160a, 160b, 160c including SDs
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`162, 164, 166 is by compression bonding of circuit membrane surface
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`electrodes 168a, 1681), 1680, 168d (pads). Id. at 16:40—43. Bonding 170
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`between MDI circuit membranes is achieved by aligning bond pads 1680,
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`168d (typically between 4 um and 25 um in diameter) on the surface of two
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`circuit membranes 160b, 1600 and using a mechanical or gas pressure source
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`to press bond pads 1680, 168d together. Id. at 16:43—49.
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`3. Summary ofSakuta (Ex. 1067)
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`Sakuta is a United States patent that describes a semiconductor
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`integrated circuit memory structure that uses “macro-cellulated circuit
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`blocks.” Ex. 1067, Abstract, 1:11—17, 2:34—37, 5:52—54. Two
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`embodiments of Sakuta’s semiconductor circuit blocks are shown below in
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`Figures 1 and 3.
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`
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`Figure 1 shows one embodiment of dynamic random access memory or
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`RAM7 constructed such that macro-cellulated memory blocks are arranged
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`in a matrix form. Id. at 5:35—36, 5:52—59. As shown in Figure 1, RAM
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`having 64 Mbit storage capacity consists of sixteen macro—cellulated
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`memory blocks arranged in four rows and in four columns. Id. at 5:3 5—37,
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`5:52—59. Sakuta indicates that “the memory blocks specified [in Figure 1]
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`are matrix-arranged together with the above-specified control circuit (i.e.,
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`the timing and address generator).” Id. at 5:68—63. “This control circuit
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`exchanges signals with individual memory blocks through signal buses.” Id.
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`at 623—5.
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`7 Ex. 1067, 1:14—1 5 (indicating “dynamic RAM (i.e., Random Access
`Memory)”).
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`By contrast, Sakuta’s embodiment shown in Figure 3 “is not equipped
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`with the aforementioned control circuit which is commonly used for the
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`plural memory blocks.” Id. at 8:5 5—57. Rather, “each memory block of this
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`embodiment is equipped with the address selection circuit, the input/output
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`circuit, and the control circuit.” Id. at 8:58—60.
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`I
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`4. Summary ofBertin ’945 (Ex. 1073)
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`.
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`Bertin ’945 is a United States patent that relates generally “to
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`fabrication of three—dimensional multichip structures, and more particularly,
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`to consolidation of circuit functions within such structures.” Ex. 1073,
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`‘ 1:18—20. Figure 1b of Bertin ’945 is reproduced below.
`
`
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`fig. 1b
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`As depicted in Figure 1b, multichip semiconductor/stack 20 includes
`
`. memory chips 10 and an “endcap chip 22.” Id. at 619—12, Fig. 1b; see id. at
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`4:18—20. In some embodiments, chip 22 is a logic chip that includes all
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`input/output (I/O) circuit functions for memory chips 10 in the multichip
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`semiconductor stack. Id. at 6:14—16. Bertin ’945 indicates “circuits for row
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`' address strobe/column address strobe (RAS/CAS) function, memory
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`read/write control, [and] refresh controls” are examples of I/O function
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`circuitry. Id. at 5:34—37.
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`5. Summary ofPoole (Ex. 1005)
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`Poole is a United States patent that describes making thinned charge-
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`coupled devices. Ex. 1005, [54] Title. It describes a two-step method for
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`thinning the backside of a silicon semiconductor substrate that includes
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`integrated circuitry previously formed on the front side. Ex. 1005, Abstract,
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`1:7—18, 3112—6. First, “[t]he bulk silicon is thinned to 75 pm with a 700
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`micro-grit aluminum oxide abrasive” (id. at 3:21—25; see also id. at Abstract,
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`3:33—34, 5:60—6:35), and “is then thinned and polished to 10 pm using 80
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`nm grit colloidal silica” (id. at 3:21—25; see also id. at Abstract, 3:33—34,
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`6:37—46). The result is a surface “almost totally free of work damage.” Id.
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`at 5:64—65; see also id. at 3:44—46.
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`6. Summary ofKowa (Ex. 1007)
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`.
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`Kowa is a Japanese unexamined patent application filed by Applicant
`
`Kowa Creator K.K. and published by the Japanese Patent Office as Japanese
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`Laid-open No. H3-151637. It describes a manufacturing method of a
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`semiconductor device having a controlled stress direction achieved by
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`controlling a plasma chemical vapor deposition (“CVD”) technique used to
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`apply silicon nitride thin films. Ex. 1007, 7.
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`E. Challenges to Claim 1
`
`Petitioner’s challenges to claim 1 rely upon substituting a different
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`dielectric (Leedy ’695) meeting the tensile strength limitation of claim 1, for
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`the dielectric actually used in the primary references (Hsu or Bertin as
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`modified by Poole), alleged to describe or at least suggest the structural
`
`. limitations of claim 1.
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`'
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`'
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`'
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`-
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`'
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`'
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`For reasons stated below we find that Petitioner has shown a
`
`reasonable likelihood of success in establishing that claim 1 is unpatentable.
`
`I. Petitioner’s Contentions Regarding Hsu and Leedy ’695
`Petitioner provides a detailed analysis of the combinations of Hsu and
`
`Leedy ’695 at Petition pages 26—32. Petitioner supports its contentions with
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`' citations to the references and with declaration testimony of Dr. Franzon
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`(Ex. 1002).
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`\
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`Petitioner contends that Hsu expressly discloses “all but a few of the
`
`features recited in claims .1 and 49.” Pet. 26. Petitioner points to Hsu’s
`description of polishing and thinning the subordinate chip to less than 50
`
`microns. Id. Hsu discloses stacked chips each having a silicon dioxide film
`
`' formed on the surface of the substrate. Id. Petitioner acknowledges that Hsu
`
`does not explicitly disclose that the dielectric layer 18 constitutes a “low
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`stress” dielectric characterized by a tensile stress of about 5 x 108 dynes/cm2
`
`or less, as recited in the challenged claims. Id.
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`‘
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`Petitioner argues that- it would have been obvious to one of ordinary
`
`skill to modify the processes and device in Hsu such that the dielectric layer
`
`18 constitutes a dielectric characterized by a tensile stress of about
`
`,
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`'
`
`5 x 108 dynes/cm2 or less, based on the disclosure of Leedy ”695. Id. I
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`(citing Ex. 1002 1111 107—120, 155).
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`‘
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`According to Petitioner, Leedy ’695 provides express motivations to
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`incorporate low tensile stress dielectric into Hsu. Pet. 27—29.
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`2. Petitioner is Contentions re Bertin ’945, Zeedy ’695, and Poole
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`.
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`Petitioner provides a detailedanalysis of the combination of Bertin
`’945 (as modified by Poole) and Leedy ’695 at Petition pages 41—51, making
`frequent reference to the Franzon Declaration. Petitioner notes that Bertin
`’945 discloses a plurality of memory layers (memory array chips 10) and a
`logic layer (chip 22); Pet. 41—42 (citing Figure 1b of Bertin ’945 and Ex.
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`I
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`1073, 5:62—63, 6:15—17. These memory layers are instacked relationship
`with the logic layer. Pet. 42.
`’
`Petitioner acknowledges that Bertin ’945 does not describe a dielectric
`
`that has a stress of 5>< 108 dynes/cm2 tensile or less. Pet. 43. However,
`Leedy ’695 describes depositing silicon oxide or silicon nitride dielectric
`material having a tensile stress of preferably 1><107 dynes/cm2 for insulating
`
`circuit devices and vertical interconnect metallization. Id. (citing Ex. 1006,
`
`-
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`1:53—62, 2:9—31, 11:33—37, 45:49—46:26, 46:46—47:33, Fig. 32b).
`Petitioner concludes that one of ordinary skill would have been
`motivated to modify the processes and device ofBertin ’945' such that the
`
`dielectric layer and interconnect insulators have a stress of 5><108 dynes/cm2
`
`tensile or less, based on the disclosure of Leedy ’695. Pet. 43 (citing Ex.
`
`1002 ‘|['[[ 115—120). Petitioner argues that one of ordinary skill would have
`
`expected success in combining these teachings. Pet. 44 (citing Ex. 1002 11
`
`119). The alleged motivation to combine is derived in part because Bertin
`
`’945 and Leedy ’695 are in the same technology field of three—dimensional ‘
`
`.
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`integration and address similar challenges. Pet. 44 (citing Ex. 1002 W 115—
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`120).
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`Petitioner relies on Poole as describing a two-step thinning and
`,
`polishing CMP process. Pet. 44 (citing Ex. 1002 1] 158)..
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`3. Patent Owner ’3 Contentions
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`Patent Owner argues against the combinations of Hsu and Leedy ’695;
`
`and against Bertin ’945 (as modified by Pool