`IN THE UNITED STATES DISTRICT COURT
`FOR THE EASTERN DISTRICT OF VIRGINIA
`ALEXANDRIA DIVISION
` SRC LABS, LLC & SAINT REGIS
` Case No. 1:17-cv-01172 (LO/JFA)
`MOHAWK TRIBE,
`
`Plaintiffs,
`JURY TRIAL DEMANDED
` v.
` MICROSOFT CORPORATION,
`
`Defendant.
`PLAINTIFFS’ PRELIMINARY INFRINGEMENT CONTENTIONS
`Pursuant to Joint Proposed Discovery Plan, Plaintiffs hereby provide their preliminary
`infringement contentions. No discovery or claim construction has taken place yet in this
`case. As a result, Plaintiffs reserve the right to amend its contentions after claim
`construction and discovery has taken place.
`A. Identification of accused products, systems, or methods.
`The following table shows all products currently accused of infringing each asserted
`claim.
`Patent Number Asserted Claims Accused Products
`6,076,152
`1-7, 11, 12, 15, 21 Office 365, Bing, and Azure
`6,247,110
`1-7, 11, 12, 15, 21 Office 365, Bing, and Azure
`6,434,687
`1-5, 10-13, 18, 25 Office 365, Bing, and Azure
`7,225,324
`1, 8, 9, 17, 18, 21,
`Bing and Microsoft’s Deep
`22, 23
`Convolution Neural Networks
`7,421,524
`1, 2, 13, 15
`Office 365, Bing, and Azure
`7,620,800
`1, 8, 9, 17, 18, 21,
`Bing and Microsoft’s Deep
`22, 23
`Convolution Neural Networks
`
`
`
`
`Petitioner Microsoft Corporation - Ex. 1013, p. 1
`
`
`
`
`IN THE UNITED STATES DISTRICT COURT
`FOR THE EASTERN DISTRICT OF VIRGINIA
`ALEXANDRIA DIVISION
` SRC LABS, LLC & SAINT REGIS
` Case No. 1:17-cv-01172 (LO/JFA)
`MOHAWK TRIBE,
`
`Plaintiffs,
`JURY TRIAL DEMANDED
` v.
` MICROSOFT CORPORATION,
`
`Defendant.
`PLAINTIFFS’ PRELIMINARY INFRINGEMENT CONTENTIONS
`Pursuant to Joint Proposed Discovery Plan, Plaintiffs hereby provide their preliminary
`infringement contentions. No discovery or claim construction has taken place yet in this
`case. As a result, Plaintiffs reserve the right to amend its contentions after claim
`construction and discovery has taken place.
`A. Identification of accused products, systems, or methods.
`The following table shows all products currently accused of infringing each asserted
`claim.
`Patent Number Asserted Claims Accused Products
`6,076,152
`1-7, 11, 12, 15, 21 Office 365, Bing, and Azure
`6,247,110
`1-7, 11, 12, 15, 21 Office 365, Bing, and Azure
`6,434,687
`1-5, 10-13, 18, 25 Office 365, Bing, and Azure
`7,225,324
`1, 8, 9, 17, 18, 21,
`Bing and Microsoft’s Deep
`22, 23
`Convolution Neural Networks
`7,421,524
`1, 2, 13, 15
`Office 365, Bing, and Azure
`7,620,800
`1, 8, 9, 17, 18, 21,
`Bing and Microsoft’s Deep
`22, 23
`Convolution Neural Networks
`
`
`
`
`Petitioner Microsoft Corporation - Ex. 1013, p. 1
`
`
`
`
`B. Claim charts identifying how Plaintiffs contend each accused instrumentality meets
`the requirements of each asserted claim.
`The claim charts are attached as Exhibits G-L to the Complaint. Dkts. 1-7, 1-8, 1-9, 1-
`10, 1-11, 1-12, incorporated herein by reference. Nothing in these claim charts is intended to
`prevent Plaintiffs from presenting additional evidence of infringement at trial. Plaintiffs
`reserve the right to amend or supplement these charts based on information received in
`discovery and/or claim construction rulings by the Court.
`C. Whether each limitation is alleged to be literally present or present under the doctrine
`of equivalents.
`The doctrine of equivalents may apply to the following limitations:
`Patent Number Claim
`Term
`6,076,152
`1, 3, 11
`Memory bank
`6,247,110
`1, 3, 11
`Memory bank
`7,421,524
`1, 15
`Memory module bus
` All other claim elements are currently alleged to be literally present. Plaintiffs reserve the
`right to amend or supplement this answer after the Court rules on claim construction.
`D. Identification of Direct Infringers for claims of indirect infringement.
`Plaintiffs currently assert claims of indirect infringement of U.S. Patent Nos. 7,225,324
`and 7,620,800. The direct infringers for the claims are Yahoo! and Apple.
`E. Identification of each claim element Plaintiffs contend is governed by 35 U.S.C. §
`112(6) and corresponding structure disclosed in the specification.
`Plaintiffs do not currently believe that any claim elements are governed by 35 U.S.C. §
`112(6).
`F. The Priority date each asserted claim is entitled.
`Priority Date
`Patent Number Asserted Claims
`1-7, 11, 12, 15, 21 December 17, 1997
`6,076,152
`1-7, 11, 12, 15, 21 December 17, 1997
`6,247,110
`June 22, 2001
`6,434,687
`1-5, 10-13, 18, 25
`2
`Petitioner Microsoft Corporation - Ex. 1013, p. 2
`
`
`
`
`October 31, 2002
`1, 8, 9, 17, 18, 21,
`7,225,324
`22, 23
`December 17, 1997
`1, 2, 13, 15
`7,421,524
`October 31, 2002
`1, 8, 9, 17, 18, 21,
`7,620,800
`22, 23
`
`G. Document Productions.
`The file histories of each asserted patent were produced as Bates numbers
`SRC_MSFT000126 – SRC_MSFT001046 and SRC_MSFT001063 – SRC_MSFT002321.
`Agreements to license or otherwise convey rights to the patents-in-suit have been
`produced as Bates numbers SRC_MSFT001047 – SRC_MSFT001062 and
`SRC_MSFT002443 – SRC_MSFT002453.
`
`
`3
`
`Petitioner Microsoft Corporation - Ex. 1013, p. 3
`
`
`
`
`DATED: January 19, 2018
`
`
`
`
`
`
`
`
`
`
`/s/Christopher L. Evans
`Charles B. Molster, III, Virginia Bar No. 23613
`cmolster@molsterlaw.com
`LAW OFFICES OF CHARLES B. MOLSTER, III PLLC
`2141 Wisconsin Ave, N.W., Ste. M
`Washington, D.C. 20007
`Telephone: (703) 346-1505
` Michael W. Shore, Texas Bar No. 18294915*
`mshore@shorechan.com
`Alfonso Garcia Chan, Texas Bar No. 24012408*
`achan@shorechan.com
`Christopher L. Evans, Texas Bar No.24058901*
`cevans@shorechan.com
`Andrew M. Howard, Texas Bar No. 24059973*
`ahoward@shorechan.com
` SHORE CHAN DEPUMPO LLP
`901 Main Street, Suite 3300
`Dallas, Texas 75202
`Telephone: 214-593-9110
`Facsimile: 214-593-9111
`* Admitted pro hac vice
` ATTORNEYS FOR PLAINTIFFS
`SRC LABS, LLC AND
`SAINT REGIS MOHAWK TRIBE
`
`
`4
`
`Petitioner Microsoft Corporation - Ex. 1013, p. 4
`
`
`
`Petitioner Microsoft Corporation - Ex. 1013, p. 6
`
`
`
`EXHIBIT G
`
`
`
`Case 1:17-cv-01172-LO-JFA Document 1-7 Filed 10/18/17 Page 1 of 27 PageID# 169
`
`
`
`Petitioner Microsoft Corporation - Ex. 1013, p. 7
`(F)
`
`(G)
`
`1
`
`Source:Adrian M. Caulfield et al.: A Cloud-Scale Acceleration Architecture, Microsoft Corporation, IEEE Computer Society, October 15, 2016
`
`(P)
`
`(D)
`
`(H)
`
`algorithm processorswithin(H) individually addressable portions of said memory bank;
`bus and an address busconnected to said at least one data processor, the improvement comprising: a plurality of (G) memory
`data in accordance with application program instructions, said computer system having at least one (F) memory bankwith a (D) data
`In a (A) computer systemhaving at least one (B) data processorfor executing an (P) application program by operating on user
`Claim 1
`Exhibit G -US 6,076,152 SRC Labs (cid:177)Microsoft Catapult V2
`
`Case 1:17-cv-01172-LO-JFA Document 1-7 Filed 10/18/17 Page 2 of 27 PageID# 170
`
`(B)
`
`(A)
`
`
`
`Petitioner Microsoft Corporation - Ex. 1013, p. 8
`
`2
`
`Source:Doug Burger @ Microsoft Research NExT: (Re)Configurable Clouds and the Dawn of a New Era, FPL Keynote, August 30, 2016
`
`(G)
`
`(D)
`processorswithin individually addressable portions of said memory bank;
`and an address busconnected to said at least one data processor, the improvement comprising: a plurality of (G) memory algorithm
`accordance with application program instructions, said computer system having at least one (F) memory bankwith a (D) data bus
`In a computer system having at least one (B) data processorfor executing an application programby operating on user data in
`Claim 1
`
`Case 1:17-cv-01172-LO-JFA Document 1-7 Filed 10/18/17 Page 3 of 27 PageID# 171
`
`Exhibit G -US 6,076,152 SRC Labs (cid:177)Microsoft Catapult V2
`
`(F)
`
`(B)
`
`
`
`Petitioner Microsoft Corporation - Ex. 1013, p. 9
`
`3
`
`Source:Adrian M. Caulfield et al.: A Cloud-Scale Acceleration Architecture, Microsoft Corporation, IEEE Computer Society, October 15, 2016
`
`(G)
`
`(MC)
`
`(B)
`
`(D)
`least one data processor executes said application program; and
`said plurality of memory algorithm processors are individually memory addressable by said at least one (B) data processor as said at
`(MC) means connecting said plurality of (G) memory algorithm processorsto said (D) data bus and said address bussuch that
`Claim 1
`
`Case 1:17-cv-01172-LO-JFA Document 1-7 Filed 10/18/17 Page 4 of 27 PageID# 172
`
`Exhibit G -US 6,076,152 SRC Labs (cid:177)Microsoft Catapult V2
`
`
`
`Petitioner Microsoft Corporation - Ex. 1013, p. 10
`
`4
`
`Source:Adrian M. Caulfield et al.: A Cloud-Scale Acceleration Architecture, Microsoft Corporation, IEEE Computer Society, October 15, 2016
`
`data processor executes said application program; and
`memory algorithm processors are (H) individually memory addressable by said at least one (B) data processor as said at least one
`means connecting said plurality of (G) memory algorithm processorsto said data bus and said address bus such that said plurality of
`Claim 1
`
`Case 1:17-cv-01172-LO-JFA Document 1-7 Filed 10/18/17 Page 5 of 27 PageID# 173
`
`Exhibit G -US 6,076,152 SRC Labs (cid:177)Microsoft Catapult V2
`
`(B)
`(H)
`(G)
`
`
`
`Petitioner Microsoft Corporation - Ex. 1013, p. 11
`(H)
`
`5
`
`Source:Andrew Putnam (cid:177)Microsoft: Large Scale Reconfigurable Computing in a Microsoft datacenter, Hot Chips 26 (cid:177)Aug 12, 2014
`
`(B)
`
`(Q)
`(X)
`memory bank by said at least one (B) data processor.
`said data processing being performed on at least one (X) operandthat is received as a result of a (W) write operation to said
`memory addressedto perform data processing related to said application program in accordance with an (Q) identified algorithm,
`said plurality of (G) memory algorithm processorsbeing (I) configured as individual data processing machines that can be (H)
`Claim 1
`
`Case 1:17-cv-01172-LO-JFA Document 1-7 Filed 10/18/17 Page 6 of 27 PageID# 174
`
`(W)
`
`(G)
`
`(I)
`
`Exhibit G -US 6,076,152 SRC Labs (cid:177)Microsoft Catapult V2
`
`
`
`Petitioner Microsoft Corporation - Ex. 1013, p. 12
`(X)
`
`6
`
`Source:Adrian M. Caulfield et al.: A Cloud-Scale Acceleration Architecture, Microsoft Corporation, IEEE Computer Society, October 15, 2016
`
`(G)
`
`programmable gate array.
`The improvement of claim 1 wherein each of said plurality of (G) memory algorithm processorscomprises a (X) field
`Claim 2
`Case 1:17-cv-01172-LO-JFA Document 1-7 Filed 10/18/17 Page 7 of 27 PageID# 175
`
`Exhibit G -US 6,076,152 SRC Labs (cid:177)Microsoft Catapult V2
`
`
`
`Petitioner Microsoft Corporation - Ex. 1013, p. 13
`
`7
`
`Source:Adrian M. Caulfield et al.: A Cloud-Scale Acceleration Architecture, Microsoft Corporation, IEEE Computer Society, October 15, 2016
`
`gate array.
`The improvement of claim 1 wherein each of said plurality of memory algorithm processors comprises a (X) field programmable
`Claim 2
`
`(X)
`Case 1:17-cv-01172-LO-JFA Document 1-7 Filed 10/18/17 Page 8 of 27 PageID# 176
`
`Exhibit G -US 6,076,152 SRC Labs (cid:177)Microsoft Catapult V2
`
`
`
`Petitioner Microsoft Corporation - Ex. 1013, p. 14
`
`8
`
`Source:Adrian M. Caulfield et al.: A Cloud-Scale Acceleration Architecture, Microsoft Corporation, IEEE Computer Society, October 15, 2016
`(HI)
`(B)
`(H)
`(G)
`
`addresssaid memory bank (HI) independent of said at least one (B) data processor.
`The improvement of claim 1 wherein each of said plurality of (G) memory algorithm processorsis operative to (H) memory
`Claim 3
`
`Case 1:17-cv-01172-LO-JFA Document 1-7 Filed 10/18/17 Page 9 of 27 PageID# 177
`
`Exhibit G -US 6,076,152 SRC Labs (cid:177)Microsoft Catapult V2
`
`
`
`Petitioner Microsoft Corporation - Ex. 1013, p. 15
`
`9
`
`Source:Adrian M. Caulfield et al.: A Cloud-Scale Acceleration Architecture, Microsoft Corporation, IEEE Computer Society, October 15, 2016
`
`(K)
`
`(G)
`
`algorithm processors.
`The improvement of claim 1 wherein an (K) identified algorithmis preprogrammed into each of said plurality of (G) memory
`Claim 4
`
`Case 1:17-cv-01172-LO-JFA Document 1-7 Filed 10/18/17 Page 10 of 27 PageID# 178
`
`Exhibit G -US 6,076,152 SRC Labs (cid:177)Microsoft Catapult V2
`
`
`
`Petitioner Microsoft Corporation - Ex. 1013, p. 16
`10
`
`Source:Adrian M. Caulfield et al.: A Cloud-Scale Acceleration Architecture, Microsoft Corporation, IEEE Computer Society, October 15, 2016
`
`(M)
`
`(K)
`
`(G)
`
`associated with said plurality of (G) memory algorithm processors.
`The improvement of claim 4 wherein a plurality of (K) identified algorithmsare preprogrammed into a (M) memory device that is
`Claim 5
`
`Case 1:17-cv-01172-LO-JFA Document 1-7 Filed 10/18/17 Page 11 of 27 PageID# 179
`
`Exhibit G -US 6,076,152 SRC Labs (cid:177)Microsoft Catapult V2
`
`
`
`Petitioner Microsoft Corporation - Ex. 1013, p. 17
`11
`
`Source:Adrian M. Caulfield et al.: A Cloud-Scale Acceleration Architecture, Microsoft Corporation, IEEE Computer Society, October 15, 2016
`
`(M)
`
`(R)
`
`The improvement of claim 5 wherein said (M) memory device comprises at least one (R) read only memory device.
`Claim 6
`Case 1:17-cv-01172-LO-JFA Document 1-7 Filed 10/18/17 Page 12 of 27 PageID# 180
`
`Exhibit G -US 6,076,152 SRC Labs (cid:177)Microsoft Catapult V2
`
`
`
`Petitioner Microsoft Corporation - Ex. 1013, p. 18
`12
`(W)
`
`Source:Andrew Putnam (cid:177)Microsoft: Large Scale Reconfigurable Computing in a Microsoft datacenter, Hot Chips 26 (cid:177)Aug 12, 2014
`
`(Q)
`(X)
`memory algorithm processors.
`a data processing resultof an (X) operandthat has been processed by an (Q) identified algorithm to another of said plurality of
`The improvement of claim 1 wherein any given one of said plurality of (G) memory algorithm processors is(W) operative to pass
`Claim 7
`
`(G)
`Exhibit G -US 6,076,152 SRC Labs (cid:177)Microsoft Catapult V2
`
`Case 1:17-cv-01172-LO-JFA Document 1-7 Filed 10/18/17 Page 13 of 27 PageID# 181
`
`
`
`Petitioner Microsoft Corporation - Ex. 1013, p. 19
`13
`
`Source:Adrian M. Caulfield et al.: A Cloud-Scale Acceleration Architecture, Microsoft Corporation, IEEE Computer Society, October 15, 2016
`
`(W)
`
`(G)
`
`algorithm processors.
`a data processing resultof an operand that has been processed by an identified algorithm to another of said plurality of memory
`The improvement of claim 1 wherein any given one of said plurality of (G) memory algorithm processors is(W) operative to pass
`Claim 7
`
`Case 1:17-cv-01172-LO-JFA Document 1-7 Filed 10/18/17 Page 14 of 27 PageID# 182
`
`Exhibit G -US 6,076,152 SRC Labs (cid:177)Microsoft Catapult V2
`
`
`
`Petitioner Microsoft Corporation - Ex. 1013, p. 20
`14
`(F)
`
`(G)
`
`Source:Adrian M. Caulfield et al.: A Cloud-Scale Acceleration Architecture, Microsoft Corporation, IEEE Computer Society, October 15, 2016
`
`(P)
`
`(D)
`
`(H)
`
`bankat a plurality of individual (H) memory addressable memory locations;
`address bus connected to said plurality of data processors; a plurality of (G) memory algorithm processorswithin said memory
`program by operating on user data in accordance with program instructions; a (F) memory bank having a (D) data bus and an
`A(A) multiprocessor computer systemcomprising: a plurality of (B) data processorsfor executing at least one (P) application
`Claim 11
`
`(B)
`
`(A)
`
`Case 1:17-cv-01172-LO-JFA Document 1-7 Filed 10/18/17 Page 15 of 27 PageID# 183
`
`Exhibit G -US 6,076,152 SRC Labs (cid:177)Microsoft Catapult V2
`
`
`
`Petitioner Microsoft Corporation - Ex. 1013, p. 21
`15
`
`Source:Doug Burger @ Microsoft Research NExT: (Re)Configurable Clouds and the Dawn of a New Era, FPL Keynote, August 30, 2016
`
`plurality of individual memory addressablememory locations;
`connected to said plurality of data processors; a plurality of (G) memory algorithm processorswithin said memory bank at a
`operating on user data in accordance with program instructions; a (F) memory bank having a (D) data bus and an address bus
`A multiprocessor computer systemcomprising: a plurality of (B) data processorsfor executing at least one application programby
`Claim 11
`
`Case 1:17-cv-01172-LO-JFA Document 1-7 Filed 10/18/17 Page 16 of 27 PageID# 184
`
`Exhibit G -US 6,076,152 SRC Labs (cid:177)Microsoft Catapult V2
`
`(G)
`
`(F)
`
`(D)
`
`(B)
`
`
`
`Petitioner Microsoft Corporation - Ex. 1013, p. 22
`16
`
`Source:Adrian M. Caulfield et al.: A Cloud-Scale Acceleration Architecture, Microsoft Corporation, IEEE Computer Society, October 15, 2016
`
`(G)
`
`(MC)
`
`(D)
`
`(B)
`
`processors; and
`said plurality of individual memory algorithm processors being individually memory addressable by all of said plurality of (B) data
`(MC) means couplingsaid plurality of individual (G) memory algorithm processorsto said (D) data bus and to said address bus;
`Claim 11
`
`Case 1:17-cv-01172-LO-JFA Document 1-7 Filed 10/18/17 Page 17 of 27 PageID# 185
`
`Exhibit G -US 6,076,152 SRC Labs (cid:177)Microsoft Catapult V2
`
`
`
`Petitioner Microsoft Corporation - Ex. 1013, p. 23
`17
`
`Source:Adrian M. Caulfield et al.: A Cloud-Scale Acceleration Architecture, Microsoft Corporation, IEEE Computer Society, October 15, 2016
`
`(B)
`(H)
`(G)
`data processors; and
`said plurality of individual memory algorithm processors being individually (H) memory addressable by all of said plurality of (B)
`means coupling said plurality of individual (G) memory algorithm processorsto said data bus and to said address bus;
`Claim 11
`Case 1:17-cv-01172-LO-JFA Document 1-7 Filed 10/18/17 Page 18 of 27 PageID# 186
`
`Exhibit G -US 6,076,152 SRC Labs (cid:177)Microsoft Catapult V2
`
`
`
`Petitioner Microsoft Corporation - Ex. 1013, p. 24
`18
`
`Source:Andrew Putnam (cid:177)Microsoft: Large Scale Reconfigurable Computing in a Microsoft datacenter, Hot Chips 26 (cid:177)Aug 12, 2014
`
`(B)
`
`(Q)
`(X)
`(I)
`least one data processor executes said at least one application program.
`an(X) operandthat is received from a (W) write operation by said at least one(B) data processorto said memory bank as said at
`said plurality of (G) memory algorithm processorsbeing (I) individually configurable to perform an (Q) identified algorithm on
`Claim 11
`
`(W)
`
`(G)
`
`Case 1:17-cv-01172-LO-JFA Document 1-7 Filed 10/18/17 Page 19 of 27 PageID# 187
`
`Exhibit G -US 6,076,152 SRC Labs (cid:177)Microsoft Catapult V2
`
`
`
`Petitioner Microsoft Corporation - Ex. 1013, p. 25
`19
`
`Source:Adrian M. Caulfield et al.: A Cloud-Scale Acceleration Architecture, Microsoft Corporation, IEEE Computer Society, October 15, 2016
`
`(G)
`
`memory addressable by all of said plurality of (B) data processors.
`The(A) multiprocessor computer systemof claim 11 wherein all of said plurality of (G) memory algorithm processorsare
`Claim 12
`
`Case 1:17-cv-01172-LO-JFA Document 1-7 Filed 10/18/17 Page 20 of 27 PageID# 188
`
`(B)
`
`Exhibit G -US 6,076,152 SRC Labs (cid:177)Microsoft Catapult V2
`
`(A)
`
`
`
`Petitioner Microsoft Corporation - Ex. 1013, p. 26
`20
`
`Source:Adrian M. Caulfield et al.: A Cloud-Scale Acceleration Architecture, Microsoft Corporation, IEEE Computer Society, October 15, 2016
`
`(B)
`(H)
`(G)
`
`addressable by all of said plurality of (B) data processors.
`The multiprocessor computer system of claim 11 wherein all of said plurality of (G) memory algorithm processorsare(H) memory
`Claim 12
`
`Case 1:17-cv-01172-LO-JFA Document 1-7 Filed 10/18/17 Page 21 of 27 PageID# 189
`
`Exhibit G -US 6,076,152 SRC Labs (cid:177)Microsoft Catapult V2
`
`
`
`Petitioner Microsoft Corporation - Ex. 1013, p. 27
`21
`
`Source:Adrian M. Caulfield et al.: A Cloud-Scale Acceleration Architecture, Microsoft Corporation, IEEE Computer Society, October 15, 2016
`
`(M)
`
`(K)
`
`(G)
`
`loaded (K) identified algorithms.
`at least one (M) memory device associated with said plurality of (G) memory algorithm processors for storing a plurality of pre
`The multiprocessor computer system of claim 11 including:
`Claim 15
`
`Case 1:17-cv-01172-LO-JFA Document 1-7 Filed 10/18/17 Page 22 of 27 PageID# 190
`
`Exhibit G -US 6,076,152 SRC Labs (cid:177)Microsoft Catapult V2
`
`
`
`Petitioner Microsoft Corporation - Ex. 1013, p. 28
`22
`
`Source:Adrian M. Caulfield et al.: A Cloud-Scale Acceleration Architecture, Microsoft Corporation, IEEE Computer Society, October 15, 2016
`
`(K)
`
`(G)
`
`(K) identified algorithms.
`at least one memory device associated with said plurality of (G) memory algorithm processors for storing a plurality of pre loaded
`The multiprocessor computer system of claim 11 including:
`Claim 15
`
`Case 1:17-cv-01172-LO-JFA Document 1-7 Filed 10/18/17 Page 23 of 27 PageID# 191
`
`Exhibit G -US 6,076,152 SRC Labs (cid:177)Microsoft Catapult V2
`
`
`
`Petitioner Microsoft Corporation - Ex. 1013, p. 29
`23
`(X)
`
`Source:Adrian M. Caulfield et al.: A Cloud-Scale Acceleration Architecture, Microsoft Corporation, IEEE Computer Society, October 15, 2016
`
`(G)
`
`(A)
`comprises a (X) field programmable gate array.
`The(A) multiprocessor computer systemof claim 11 wherein each of said plurality of (G) memory algorithm processors
`Claim 18
`Case 1:17-cv-01172-LO-JFA Document 1-7 Filed 10/18/17 Page 24 of 27 PageID# 192
`
`Exhibit G -US 6,076,152 SRC Labs (cid:177)Microsoft Catapult V2
`
`
`
`Petitioner Microsoft Corporation - Ex. 1013, p. 30
`24
`
`Source:Adrian M. Caulfield et al.: A Cloud-Scale Acceleration Architecture, Microsoft Corporation, IEEE Computer Society, October 15, 2016
`
`programmable gate array.
`The multiprocessor computer system of claim 11 wherein each of said plurality of memory algorithm processors comprises a (X) field
`Claim 18
`
`(X)
`Case 1:17-cv-01172-LO-JFA Document 1-7 Filed 10/18/17 Page 25 of 27 PageID# 193
`
`Exhibit G -US 6,076,152 SRC Labs (cid:177)Microsoft Catapult V2
`
`
`
`Petitioner Microsoft Corporation - Ex. 1013, p. 31
`25
`
`Source:Andrew Putnam (cid:177)Microsoft: Large Scale Reconfigurable Computing in a Microsoft datacenter, Hot Chips 26 (cid:177)Aug 12, 2014
`
`(H)
`
`(H) pass a result of a processed operand to another memory algorithm processor.
`The multiprocessor computer system of claim 11 wherein each of said plurality of (G) memory algorithm processors is operative to
`Claim 21
`
`Case 1:17-cv-01172-LO-JFA Document 1-7 Filed 10/18/17 Page 26 of 27 PageID# 194
`
`(G)
`Exhibit G -US 6,076,152 SRC Labs (cid:177)Microsoft Catapult V2
`
`
`
`Petitioner Microsoft Corporation - Ex. 1013, p. 32
`26
`
`Source:Adrian M. Caulfield et al.: A Cloud-Scale Acceleration Architecture, Microsoft Corporation, IEEE Computer Society, October 15, 2016
`
`(H)
`
`(G)
`
`(H)pass a result of a processed operand to another memory algorithm processor.
`The multiprocessor computer system of claim 11 wherein each of said plurality of (G) memory algorithm processors is operative to
`Claim 21
`
`Case 1:17-cv-01172-LO-JFA Document 1-7 Filed 10/18/17 Page 27 of 27 PageID# 195
`
`Exhibit G -US 6,076,152 SRC Labs (cid:177)Microsoft Catapult V2
`
`
`
`Petitioner Microsoft Corporation - Ex. 1013, p. 33
`
`EXHIBIT H
`
`Case 1:17-cv-01172-LO-JFA Document 1-8 Filed 10/18/17 Page 1 of 28 PageID# 196
`
`
`
`Petitioner Microsoft Corporation - Ex. 1013, p. 34
`(F)
`
`(G)
`
`1
`
`Source:Adrian M. Caulfield et al.: A Cloud-Scale Acceleration Architecture, Microsoft Corporation, IEEE Computer Society, October 15, 2016
`
`(P)
`
`(D)
`
`(H)
`
`reconfigurable (G) memory algorithm processorswithin(H) individually addressable portions of said (F) memory bank,
`data bus and an address bus connected to said at least one (B) data processor, the improvement comprising: a plurality of
`data in accordance with application program instructions, said (A) computer system having at least one (F) memory bankwith a (D)
`In a (A) computer system having at least one (B) data processor for executing an (P) application program by operating on user
`Claim 1
`Case 1:17-cv-01172-LO-JFA Document 1-8 Filed 10/18/17 Page 2 of 28 PageID# 197
`
`Exhibit H -US 6,247,110 SRC Labs (cid:177)Microsoft Catapult V2
`
`(B)
`
`(A)
`
`
`
`Petitioner Microsoft Corporation - Ex. 1013, p. 35
`
`2
`
`Source:Doug Burger @ Microsoft Research NExT: (Re)Configurable Clouds and the Dawn of a New Era, FPL Keynote, August 30, 2016
`
`memory algorithm processorswithin individually addressableportions of said (F) memory bank,
`and an address bus connected to said at least one (B) data processor, the improvement comprising: a plurality of reconfigurable (G)
`accordance with application program instructions, said computer systemhaving at least one (F) memory bankwith a (D) data bus
`In a computer systemhaving at least one (B) data processor for executing an application programby operating on user data in
`Claim 1
`Exhibit H -US 6,247,110 SRC Labs (cid:177)Microsoft Catapult V2
`
`Case 1:17-cv-01172-LO-JFA Document 1-8 Filed 10/18/17 Page 3 of 28 PageID# 198
`
`(G)
`
`(F)
`
`(D)
`
`(B)
`
`
`
`Petitioner Microsoft Corporation - Ex. 1013, p. 36
`
`3
`
`Source:Adrian M. Caulfield et al.: A Cloud-Scale Acceleration Architecture, Microsoft Corporation, IEEE Computer Society, October 15, 2016
`
`(G)
`
`(MC)
`
`(B)
`
`(D)
`said one (B) data processor executes said application program; and
`said plurality of (G) memory algorithm processorsare individually memory addressableby said at least one (B) data processor at
`(MC) means connecting said plurality of (G) memory algorithm processorsto said (D) data bus and said address bussuch that
`Claim 1
`
`Case 1:17-cv-01172-LO-JFA Document 1-8 Filed 10/18/17 Page 4 of 28 PageID# 199
`
`Exhibit H -US 6,247,110 SRC Labs (cid:177)Microsoft Catapult V2
`
`
`
`Petitioner Microsoft Corporation - Ex. 1013, p. 37
`
`4
`
`Source:Adrian M. Caulfield et al.: A Cloud-Scale Acceleration Architecture, Microsoft Corporation, IEEE Computer Society, October 15, 2016
`
`(B) data processor executes said application program; and
`(G) memory algorithm processorsare(H) individually memory addressable by said at least one (B) data processor at said one
`means connectingsaid plurality of (G) memory algorithm processorsto said data bus and said address bus such that said plurality of
`Claim 1
`
`Case 1:17-cv-01172-LO-JFA Document 1-8 Filed 10/18/17 Page 5 of 28 PageID# 200
`
`Exhibit H -US 6,247,110 SRC Labs (cid:177)Microsoft Catapult V2
`
`(B)
`(H)
`(G)
`
`
`
`Petitioner Microsoft Corporation - Ex. 1013, p. 38
`
`5
`
`Source:Andrew Putnam (cid:177)Microsoft: Large Scale Reconfigurable Computing in a Microsoft datacenter, Hot Chips 26 (cid:177)Aug 12, 2014
`
`(Q)
`(X)
`(G)
`on at least one (X) operandthat is received directly from said at least one (B) data processor.
`processing related to said application program in accordance with an (Q) identified algorithm, said data processing being performed
`said plurality of (G) memory algorithm processorsbeing (I) configured as individual data processing elements to perform data
`Claim 1
`Exhibit H -US 6,247,110 SRC Labs (cid:177)Microsoft Catapult V2
`
`Case 1:17-cv-01172-LO-JFA Document 1-8 Filed 10/18/17 Page 6 of 28 PageID# 201
`
`(I)
`
`(B)
`
`
`
`Petitioner Microsoft Corporation - Ex. 1013, p. 39
`(X)
`
`6
`
`Source:Adrian M. Caulfield et al.: A Cloud-Scale Acceleration Architecture, Microsoft Corporation, IEEE Computer Society, October 15, 2016
`
`(G)
`
`programmable gate array.
`The improvement of claim 1 wherein each of said plurality of (G) memory algorithm processorscomprises a (X) field
`Claim 2
`Case 1:17-cv-01172-LO-JFA Document 1-8 Filed 10/18/17 Page 7 of 28 PageID# 202
`
`Exhibit H -US 6,247,110 SRC Labs (cid:177)Microsoft Catapult V2
`
`
`
`Petitioner Microsoft Corporation - Ex. 1013, p. 40
`
`7
`
`Source:Adrian M. Caulfield et al.: A Cloud-Scale Acceleration Architecture, Microsoft Corporation, IEEE Computer Society, October 15, 2016
`
`gate array.
`The improvement of claim 1 wherein each of said plurality of memory algorithm processors comprises a (X) field programmable
`Claim 2
`
`(X)
`Case 1:17-cv-01172-LO-JFA Document 1-8 Filed 10/18/17 Page 8 of 28 PageID# 203
`
`Exhibit H -US 6,247,110 SRC Labs (cid:177)Microsoft Catapult V2
`
`
`
`Petitioner Microsoft Corporation - Ex. 1013, p. 41
`
`8
`
`Source:Adrian M. Caulfield et al.: A Cloud-Scale Acceleration Architecture, Microsoft Corporation, IEEE Computer Society, October 15, 2016
`(HI)
`(B)
`(H)
`(G)
`
`addresssaid memory bank (HI) independentof said at least one (B) data processor.
`The improvement of claim1wherein each of said plurality of (G) memory algorithm processorsis operative to (H) memory
`Claim 3
`
`Case 1:17-cv-01172-LO-JFA Document 1-8 Filed 10/18/17 Page 9 of 28 PageID# 204
`
`Exhibit H -US 6,247,110 SRC Labs (cid:177)Microsoft Catapult V2
`
`
`
`Petitioner Microsoft Corporation - Ex. 1013, p. 42
`
`9
`
`Source:Adrian M. Caulfield et al.: A Cloud-Scale Acceleration Architecture, Microsoft Corporation, IEEE Computer Society, October 15, 2016
`
`(K)
`
`(G)
`
`algorithm processors.
`The improvement of claim1wherein an (K) identified algorithm is preprogrammed into each of said plurality of (G) memory
`Claim 4
`
`Case 1:17-cv-01172-LO-JFA Document 1-8 Filed 10/18/17 Page 10 of 28 PageID# 205
`
`Exhibit H -US 6,247,110 SRC Labs (cid:177)Microsoft Catapult V2
`
`
`
`Petitioner Microsoft Corporation - Ex. 1013, p. 43
`10
`
`Source:Adrian M. Caulfield et al.: A Cloud-Scale Acceleration Architecture, Microsoft Corporation, IEEE Computer Society, October 15, 2016
`
`(M)
`
`(K)
`
`(G)
`
`associated with said plurality of (G) memory algorithm processors.
`The improvement of claim4wherein a plurality of (K) identified algorithmsare preprogrammed into a (M) memory device that is
`Claim 5
`
`Case 1:17-cv-01172-LO-JFA Document 1-8 Filed 10/18/17 Page 11 of 28 PageID# 206
`
`Exhibit H -US 6,247,110 SRC Labs (cid:177)Microsoft Catapult V2
`
`
`
`Petitioner Microsoft Corporation - Ex. 1013, p. 44
`11
`
`Source:Adrian M. Caulfield et al.: A Cloud-Scale Acceleration Architecture, Microsoft Corporation, IEEE Computer Society, October 15, 2016
`
`(K)
`
`(G)
`
`associated with said plurality of (G) memory algorithm processors.
`The improvement of claim4wherein a plurality of (K) identified algorithmsare preprogrammed into a memory device that is
`Claim 5
`
`Case 1:17-cv-01172-LO-JFA Document 1-8 Filed 10/18/17 Page 12 of 28 PageID# 207
`
`Exhibit H -US 6,247,110 SRC Labs (cid:177)Microsoft Catapult V2
`
`
`
`Petitioner Microsoft Corporation - Ex. 1013, p. 45
`12
`
`Source:Adrian M. Caulfield et al.: A Cloud-Scale Acceleration Architecture, Microsoft Corporation, IEEE Computer Society, October 15, 2016
`
`(M)
`
`(R)
`
`The improvement of claim5wherein said (M) memory device comprises at least one (R) read only memory device.
`Claim 6
`Case 1:17-cv-01172-LO-JFA Document 1-8 Filed 10/18/17 Page 13 of 28 PageID# 208
`
`Exhibit H -US 6,247,110 SRC Labs (cid:177)Microsoft Catapult V2
`
`
`
`Petitioner Microsoft Corporation - Ex. 1013, p. 46
`13
`(W)
`
`Source:Andrew Putnam (cid:177)Microsoft: Large Scale Reconfigurable Computing in a Microsoft datacenter, Hot Chips 26 (cid:177)Aug 12, 2014
`
`(Q)
`(X)
`memory algorithm processors.
`a data processing resultof an (X) operandthat has been processed by an (Q) identified algorithm to another of said plurality of
`The improvement of claim1wherein any given one of said plurality of (G) memory algorithm processors is(W) operative to pass
`Claim 7
`
`(G)
`Exhibit H -US 6,247,110 SRC Labs (cid:177)Microsoft Catapult V2
`
`Case 1:17-cv-01172-LO-JFA Document 1-8 Filed 10/18/17 Page 14 of 28 PageID# 209
`
`
`
`Petitioner Microsoft Corporation - Ex. 1013, p. 47
`14
`
`Source:Adrian M. Caulfield et al.: A Cloud-Scale Acceleration Architecture, Microsoft Corporation, IEEE Computer Society, October 15, 2016
`
`(W)
`
`(G)
`
`algorithm processors.
`a data processing resultof an operand that has been processed by an identified algorithm to another of said plurality of memory
`The improvement of claim1wherein any given one of said plurality of (G) memory algorithm processors is(W) operative to pass
`Claim 7
`
`Case 1:17-cv-01172-LO-JFA Document 1-8 Filed 10/18/17 Page 15 of 28 PageID# 210
`
`Exhibit H -US 6,247,110 SRC Labs (cid:177)Microsoft Catapult V2
`
`
`
`Petitioner Microsoft Corporation - Ex. 1013, p. 48
`15
`(F)
`
`(G)
`
`Source:Adrian M. Caulfield et al.: A Cloud-Scale Acceleration Architecture, Microsoft Corporation, IEEE Computer Society, October 15, 2016
`
`(P)
`
`(D)
`
`(H)
`
`(B)
`within said (F) memory bank at plurality of individual (H) memory addressable memory locations;
`address busconnected to said plurality of (B) data processors; a plurality of reconfigurable (G) memory algorithm processors
`program by operating on user data in accordance with program instructions; a (F) memory bankhaving a (D) data bus and an
`A(A) multiprocessor computer systemcomprising: a plurality of (B) data processorsfor executing at least one (P) application
`Claim 11
`Exhibit H -US 6,247,110 SRC Labs (cid:177)Microsoft Catapult V2
`
`Case 1:17-cv-01172-LO-JFA Document 1-8 Filed 10/18/17 Page 16 of 28 PageID# 211
`
`(A)
`
`
`
`Petitioner Microsoft Corporation - Ex. 1013, p. 49
`16
`
`Source:Doug Burger @ Microsoft Research NExT: (Re)Configurable Clouds and the Dawn of a New Era, FPL Keynote, August 30, 2016
`
`(G)
`
`(D)
`memory bank at plurality of individual memory addressablememory locations;
`connecte
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