Exhibit C-12: “Splash 2: FPGAs in a Custom Computing Machine,” D.A. Buell et al., 1996 (“Buell”)
`
`
`
`A book chapter entitled, “Splash 2: FPGAs in a custom Computing Machine,” by D.A. Buell, J. M. Arnold, and W. J. Kleinfelder,
`(“Buell”) was published in 1996, and is therefore prior art to U.S. Patent No. 7,225,324 (“’324 Patent”) at least under 35 U.S.C. §§
`102(a) and (b).
`
`The citations presented herein are exemplary and not exclusive; each prior art reference as a whole discloses each and every limitation
`of the claims. A citation to a figure or figure reference numeral incorporates by reference the discussion and/or explication of such
`figure or feature/component referenced by the reference numeral. Further, the mapping in this chart is based on Amazon’s present
`understanding of Plaintiffs’ interpretation of the asserted claims of the patent-in-suit as reflected in Plaintiffs’ infringement
`contentions. Nothing in the chart should be regarded as necessarily reflecting how the prior art references would apply to claim
`elements of the asserted patent under a proper interpretation of the claims. Disclosures cited for dependent claims incorporate by
`reference the disclosure included herein for the corresponding independent claim.
`
`
`Asserted Claim of ’324
`Patent
`[1A] A method for data
`processing
`
`Exemplary Disclosure of Buell
`
`Buell at 97: “With the onset of the Human Genome Initiative [3] and constant advances in genetic
`sequencing technology, genetic sequence data are being generated at an ever increasing rate. As a result,
`biologists are faced with an influx of new sequences that they would like to classify and study by
`comparing them to existing databases. The analysis of a newly generated sequence typically involves
`searching the databases for similar sequences. With the enormous size of the databases, fast methods are
`needed for comparing sequences [11].
`
`In this chapter, we describe two systolic array architectures for sequence comparison...”
`
`Buell at 100: “The locality of reference shown in Figure 8.3 can be exploited to produce systolic
`algorithms in which communication is limited to adjacent processors….
`
`The systolic architecture and data flow shown in Figure 8.5 were used in the design of P-NAC of Lipton
`and Lopresti [12], a custom VLSI chip for DNA sequence comparison. Each processing element (PE)
`computes the distances along a particular diagonal of the distance matrix.”
`
`
`
`
`
`
`
`
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2051, p. 1
`
`

`

`Exhibit C-12: “Splash 2: FPGAs in a Custom Computing Machine,” D.A. Buell et al., 1996 (“Buell”)
`
`
`
`Asserted Claim of ’324
`Patent
`
`Exemplary Disclosure of Buell
`
`
`
`
`Buell at Figure 8.1:
`
`2
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2051, p. 2
`
`

`

`Exhibit C-12: “Splash 2: FPGAs in a Custom Computing Machine,” D.A. Buell et al., 1996 (“Buell”)
`
`
`
`Asserted Claim of ’324
`Patent
`
`Exemplary Disclosure of Buell
`
`
`Buell at Figure 8.9 [emphasis added]:
`
`
`
`3
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2051, p. 3
`
`

`

`Exhibit C-12: “Splash 2: FPGAs in a Custom Computing Machine,” D.A. Buell et al., 1996 (“Buell”)
`
`
`
`Asserted Claim of ’324
`Patent
`
`Exemplary Disclosure of Buell
`
`
`
`
`
`
`
`Buell showing a method for processing data at Figure 8.12:
`
`4
`
`
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2051, p. 4
`
`

`

`Exhibit C-12: “Splash 2: FPGAs in a Custom Computing Machine,” D.A. Buell et al., 1996 (“Buell”)
`
`
`
`Asserted Claim of ’324
`Patent
`
`Exemplary Disclosure of Buell
`
`
`
`Buell showing a method for processing data at Figure 8.7:
`
`5
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2051, p. 5
`
`

`

`Exhibit C-12: “Splash 2: FPGAs in a Custom Computing Machine,” D.A. Buell et al., 1996 (“Buell”)
`
`
`
`Asserted Claim of ’324
`Patent
`
`Exemplary Disclosure of Buell
`
`
`
`[1B] in a
`reconfigurable
`computing system,
`
`
`Buell at 97: “ln this chapter, we describe two systolic array architectures for sequence comparison and
`their implementations on the Splash 2 programmable logic array.”
`
`Buell at 108: “…the programmability and reprogrammability of Splash 2 allowed for experimentation
`and incremental refinement that could not have been afforded on a less flexible system.”
`
`
`
`
`
`
`
`
`6
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2051, p. 6
`
`

`

`Exhibit C-12: “Splash 2: FPGAs in a Custom Computing Machine,” D.A. Buell et al., 1996 (“Buell”)
`
`
`
`Asserted Claim of ’324
`Patent
`
`Exemplary Disclosure of Buell
`
`
`
`Buell at Figure 8.5 [emphasis added]:
`
`
`
`
`
`
`
`
`
`7
`
`
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2051, p. 7
`
`

`

`Exhibit C-12: “Splash 2: FPGAs in a Custom Computing Machine,” D.A. Buell et al., 1996 (“Buell”)
`
`
`
`Asserted Claim of ’324
`Patent
`
`Exemplary Disclosure of Buell
`
`Buell at Figure 8.9 [emphasis added]:
`
`
`
`
`
`
`
`
`8
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2051, p. 8
`
`

`

`Exhibit C-12: “Splash 2: FPGAs in a Custom Computing Machine,” D.A. Buell et al., 1996 (“Buell”)
`
`
`
`Asserted Claim of ’324
`Patent
`[1C] the reconfigurable
`computing system
`comprising at least one
`reconfigurable
`processor,
`
`Exemplary Disclosure of Buell
`
`Buell at 108: “On uniprocessor machines, a straightforward implementation of the dynamic programming
`algorithm in the C language is used in the benchmark. On multiprocessor machines, a parallel
`implementation of the dynamic programming algorithm is used.”
`
`Buell at Figure 8.5 [emphasis added]:
`
`
`
`
`
`
`9
`
`
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2051, p. 9
`
`

`

`Exhibit C-12: “Splash 2: FPGAs in a Custom Computing Machine,” D.A. Buell et al., 1996 (“Buell”)
`
`
`
`Asserted Claim of ’324
`Patent
`
`Exemplary Disclosure of Buell
`
`Buell at Figure 8.9 [emphasis added]:
`
`
`
`
`
`10
`
`
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2051, p. 10
`
`

`

`Exhibit C-12: “Splash 2: FPGAs in a Custom Computing Machine,” D.A. Buell et al., 1996 (“Buell”)
`
`
`
`Asserted Claim of ’324
`Patent
`[1D] the reconfigurable
`processor comprising a
`plurality of functional
`units, said method
`comprising:
`
`Exemplary Disclosure of Buell
`
`Buell at 107: “For the DNA version of the bidirectional array, each of the 16 array FPGAs (X1 to X16)
`contains 24 PEs, making a total of 384 PEs in a one-board Splash 2 system. The protein version packs 64
`PEs into a one-board Splash 2 system…
`
`ln the DNA version of the unidirectional array, each of the 16 array FPGAs (X1 to Xl6) holds 14 PEs. In
`addition, the two interface FPGAs contain 12 PEs each, making a total of 248 PEs in a one-array-board
`Splash 2 system.”
`
`Buell at Figure 8.5 [emphasis added]:
`
`
`
`
`
`11
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2051, p. 11
`
`

`

`Exhibit C-12: “Splash 2: FPGAs in a Custom Computing Machine,” D.A. Buell et al., 1996 (“Buell”)
`
`
`
`Asserted Claim of ’324
`Patent
`
`Exemplary Disclosure of Buell
`
`
`Buell at Figure 8.6 [emphasis added]:
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`12
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2051, p. 12
`
`

`

`Exhibit C-12: “Splash 2: FPGAs in a Custom Computing Machine,” D.A. Buell et al., 1996 (“Buell”)
`
`
`
`Asserted Claim of ’324
`Patent
`
`Exemplary Disclosure of Buell
`
`Buell at Figure 8.9 [emphasis added]:
`
`
`
`
`
`
`
`13
`
`
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2051, p. 13
`
`

`

`Exhibit C-12: “Splash 2: FPGAs in a Custom Computing Machine,” D.A. Buell et al., 1996 (“Buell”)
`
`
`
`Asserted Claim of ’324
`Patent
`
`Exemplary Disclosure of Buell
`
`Buell at Figure 8.10 [emphasis added]:
`
`
`[1E] transforming an
`algorithm
`
`
`
`
`Buell at 104: “The unidirectional PE is diagrammed in Figure 8.10. In this configuration, each PE
`computes the distances in one row of the distance matrix. At each time step, the PEs compute the
`distances along a single antidiagonal in the distance matrix, as depicted in Figure 8.4. Each PE stores two
`distances, DST and PDST.”
`Buell at 98: “8.1.2 Dynamic Programming Algorithm
`
`The edit distance can be computed with a well-known dynamic programming algorithm, which has an
`interesting history of independent discovery as devised by Sankoff and Kruskal [17]. We use the following
`formulation…”
`
`“A straightforward sequential implementation of the dynamic programming algorithm requires O (mn)
`time and O (min (m, n)) space to compute the edit distance.”
`
`Buell at 100: “Masek and Patterson (16) give an algorithm with time performance of O (n2/log n) for
`sequences of length n, provided that the sequence alphabet is finite and all costs are integers. However, for
`a particular implementation, they observe that their algorithm performs faster than the basic dynamic
`programming algorithm only for sequences of length 262,419 or longer. Better time performance can be
`achieved by exploiting the inherent parallelism in Equation (8.2). One notable property of the dynamic
`
`14
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2051, p. 14
`
`

`

`Exhibit C-12: “Splash 2: FPGAs in a Custom Computing Machine,” D.A. Buell et al., 1996 (“Buell”)
`
`
`
`Asserted Claim of ’324
`Patent
`
`Exemplary Disclosure of Buell
`
`programming recurrence is that each entry in the distance matrix depends on adjacent entries, as
`diagrammed in Figure 8.3. This property has been the basis for many parallel algorithms for computing
`the edit distance…”
`
`“A block diagram of the [bidirectional] PE and a listing of the algorithm it executes are shown in Figures
`8.6 and 8.7, respectively.”
`
`Buell at Figure 8.7:
`
`
`
`
`Buell at 104: “The algorithm executed by each PE in the unidirectional array is listed in Fig. 8.12. As
`shown, the algorithm compares one source sequence to a single target sequence.”
`
`
`
`
`
`15
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2051, p. 15
`
`

`

`Exhibit C-12: “Splash 2: FPGAs in a Custom Computing Machine,” D.A. Buell et al., 1996 (“Buell”)
`
`
`
`Asserted Claim of ’324
`Patent
`
`Exemplary Disclosure of Buell
`
`Buell at Figure 8.12:
`
`
`
`
`
`16
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2051, p. 16
`
`

`

`Exhibit C-12: “Splash 2: FPGAs in a Custom Computing Machine,” D.A. Buell et al., 1996 (“Buell”)
`
`
`
`Asserted Claim of ’324
`Patent
`
`[1F] into a calculation
`
`Exemplary Disclosure of Buell
`
`Buell at 107: “In order to make a uniform comparison between Splash 2 and implementations of the
`dynamic programming algorithm on other architectures, we measure the performance of a solution in
`terms of the number of cells (entries in the DP distance table) updated per second (CUPS).”
`
`Buell at 100: “There are several ways to map the edit distance computation onto a linear systolic array.
`We describe two such mappings. Both exploit the locality of reference by computing the entries along
`each antidiagonal in parallel, as shown in Figure 8.4.”
`
`“Each processing clement (PE) [of the bi-directional array] computes the distances along a particular
`diagonal of the distance matrix.”
`
`Buell at Figure 8.4 [emphasis added]:
`
`
`
`
`
`
`
`17
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2051, p. 17
`
`

`

`Exhibit C-12: “Splash 2: FPGAs in a Custom Computing Machine,” D.A. Buell et al., 1996 (“Buell”)
`
`
`
`Asserted Claim of ’324
`Patent
`
`Exemplary Disclosure of Buell
`
` Buell at 104: “In this [unidirectional] configuration, each PE computes the distances in one row of the
`distance matrix. At each time step, the PEs compute the distances along a single antidiagonal in the
`distance matrix as depicted in Figure 8.4. Each PE stores two distances, DST and PDST. Denoting the
`previously computed value of DST and PDST as DST' and PDST', respectively, the computation graph
`for the ith PE is shown in Figure 8.11.”
`
`Buell at Figure 8.11 [emphasis added]:
`
`
`
`
`Buell at 107: “In order to make a uniform comparison between Splash 2 and implementations of the
`dynamic programming algorithm on other architectures, we measure the performance of a solution in
`terms of the number of cells (entries in the DP distance table) updated per second (CUPS). When
`comparing two sequences of lengths n and m, a total of nm cells needs to be calculated.”
`
`Buell at 100: “8.2 SYSTOLIC SEQUENCE COMPARISON
`
`The locality of reference shown in Figure 8.3 can be exploited to produce systolic algorithms in which
`communication is limited to adjacent processors.
`
`There are several ways to map the edit distance computation onto a linear systolic array. We describe two
`such mappings [bidirectional and unidirectional]…
`
`
`[1G] that is systolically
`implemented by said
`reconfigurable
`computing system at the
`at least one
`reconfigurable
`processor,
`
`18
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2051, p. 18
`
`

`

`Exhibit C-12: “Splash 2: FPGAs in a Custom Computing Machine,” D.A. Buell et al., 1996 (“Buell”)
`
`
`
`Asserted Claim of ’324
`Patent
`
`Exemplary Disclosure of Buell
`
`The systolic architecture and data flow shown in Figure 8.5 were used in the design of P-NAC of Lipton
`and Lopresti [12], a custom VLSI chip for DNA sequence comparison.”
`
`Buell at 104: “Both the bidirectional and unidirectional systolic arrays have been implemented on
`the Splash 2 programmable logic array, with versions for DNA and protein sequences”
`
`Buell at 108: “Two systolic arrays for computing the edit distance between two genetic sequences have
`been presented and their implementations on Splash 2 described. The bidirectional and unidirectional
`arrays have maximum throughputs or 5.5 and 12 million characters per second, respectively, for DNA
`database search. Compared to implementations of the dynamic programming algorithm on several
`contemporary workstations and minicomputers, the Splash 2 implementations promise to deliver several
`orders of magnitude better performance”
`
`Buell at Figure 8.5 [emphasis added]:
`
`
`19
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2051, p. 19
`
`

`

`Exhibit C-12: “Splash 2: FPGAs in a Custom Computing Machine,” D.A. Buell et al., 1996 (“Buell”)
`
`
`
`Asserted Claim of ’324
`Patent
`
`Exemplary Disclosure of Buell
`
`
`Buell at Figure 8.9 [emphasis added]:
`
`
`
`
`20
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2051, p. 20
`
`

`

`Exhibit C-12: “Splash 2: FPGAs in a Custom Computing Machine,” D.A. Buell et al., 1996 (“Buell”)
`
`
`
`Asserted Claim of ’324
`Patent
`
`Exemplary Disclosure of Buell
`
`
`
`
`
`
`
`
`21
`
`
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2051, p. 21
`
`

`

`Exhibit C-12: “Splash 2: FPGAs in a Custom Computing Machine,” D.A. Buell et al., 1996 (“Buell”)
`
`Exemplary Disclosure of Buell
`
`Buell at Figure 8.8 [emphasis added]:
`
`
`
`
`Asserted Claim of ’324
`Patent
`[1H] instantiating at
`least two of said
`functional units at the
`at least one
`reconfigurable processor
`to perform said
`calculation
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`22
`
`
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2051, p. 22
`
`

`

`Exhibit C-12: “Splash 2: FPGAs in a Custom Computing Machine,” D.A. Buell et al., 1996 (“Buell”)
`
`
`
`Asserted Claim of ’324
`Patent
`
`Exemplary Disclosure of Buell
`
`Buell at 104: “Each PE stores two distances, DST and PDST. Denoting the previously computed value of
`DST and PDST as DST' and PDST', respectively, the computation graph for the ith PE is shown in Figure
`8.11.”
`
`Buell at Figure 8.11:
`
`
`
`[1J] wherein only
`functional units needed
`to solve the calculation
`are instantiated and
`
`[1K] wherein each
`instantiated functional
`unit at the at least one
`reconfigurable processor
`interconnects with
`each other instantiated
`functional unit at the at
`least one reconfigurable
`processor
`
`
`
`
`
`
`Buell at 101: “The source and target sequences are streamed through the [bidirectional] array in opposite
`directions. A comparison is performed [only] when a source character and a target character meet in a
`PE.”
`
`Buell at 103: “At each computational step, at most half of the PEs are active.”
`Buell at 102: “The source and target sequences enter the [bidirectional] array on opposite ends and flow in
`opposite directions at the same speed.”
`
`
`
`
`
`
`
`
`
`
`23
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2051, p. 23
`
`

`

`Exhibit C-12: “Splash 2: FPGAs in a Custom Computing Machine,” D.A. Buell et al., 1996 (“Buell”)
`
`
`
`Asserted Claim of ’324
`Patent
`
`Exemplary Disclosure of Buell
`
`
`Buell at Figure 8.5 [emphasis added]:
`
`
`
`24
`
`
`
`
`
`
`
`
`
`
`
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2051, p. 24
`
`

`

`Exhibit C-12: “Splash 2: FPGAs in a Custom Computing Machine,” D.A. Buell et al., 1996 (“Buell”)
`
`
`
`Asserted Claim of ’324
`Patent
`
`Exemplary Disclosure of Buell
`
`
`Buell at 103: “The architecture and data flow of the unidirectional array are shown in Figure 8.9. As the
`name suggests, data flows through the unidirectional array in one direction. The source sequence is
`loaded once and stored in the array starting from the leftmost PE. The target sequences arc streamed
`through the array…”
`
`Buell at Figure 8.9 [emphasis added]:
`
`
`
`
`
`
`
`25
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2051, p. 25
`
`

`

`Exhibit C-12: “Splash 2: FPGAs in a Custom Computing Machine,” D.A. Buell et al., 1996 (“Buell”)
`
`
`
`Asserted Claim of ’324
`Patent
`[1L] based on
`reconfigurable routing
`resources within the at
`least one reconfigurable
`processor as established
`at instantiation, and
`
`Exemplary Disclosure of Buell
`
`Buell at 102: “The source and target sequences enter the [bidirectional] array on opposite ends and flow in
`opposite directions at the same speed”
`
`Buell at 103: “As the name suggests, data flows through the unidirectional array in one direction. The
`source sequence is loaded once and stored in the array starting from the leftmost PE. The target sequences
`are streamed through the array one at a time, separated by control characters.”
`
`Buell at 104: “In this [unidirectional] configuration, each PE computes the distances in one row of the
`distance matrix. At each time step, the PEs compute the distances along a single antidiagonal in the
`distance matrix…
`
`Both the bidirectional and unidirectional systolic arrays have been implemented on the Splash 2
`programmable logic array, with versions for DNA and protein sequences.”
`
`Buell at Figure 8.5:
`
`
`
`
`
`
`26
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2051, p. 26
`
`

`

`Exhibit C-12: “Splash 2: FPGAs in a Custom Computing Machine,” D.A. Buell et al., 1996 (“Buell”)
`
`
`
`Asserted Claim of ’324
`Patent
`
`Exemplary Disclosure of Buell
`
`Buell at Figure 8.9:
`
`
`
`
`
`
`
`27
`
`
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2051, p. 27
`
`

`

`Exhibit C-12: “Splash 2: FPGAs in a Custom Computing Machine,” D.A. Buell et al., 1996 (“Buell”)
`
`
`
`Asserted Claim of ’324
`Patent
`
`[1M] wherein
`systolically linked lines
`of code of said
`calculation are
`instantiated as clusters
`of functional units
`within the at least one
`reconfigurable
`processor;
`
`Exemplary Disclosure of Buell
`
`Buell at 106: “8.3.2 Configurable Parameters
`
`The designs of both systolic arrays are not specific to a particular alphabet or cost function. The sequence
`alphabet and cost function are defined in an VHDL configuration file and can be customized for a
`particular sequence comparison application. A change in the parameters, however, would require a
`recompilation of the VHDL code. Versions for comparing DNA and protein sequences have been
`implemented.”
`Buell at 100: “8.2 SYSTOLIC SEQUENCE COMPARISON
`
`The locality of reference shown in Figure 8.3 can be exploited to produce systolic algorithms in which
`communication is limited to adjacent processors.
`
`There are several ways to map the edit distance computation onto a linear systolic array. We describe two
`such mappings [bidirectional and unidirectional]…
`
`The systolic architecture and data flow shown in Figure 8.5 were used in the design of P-NAC of Lipton
`and Lopresti [12], a custom VLSI chip for DNA sequence comparison.”
`
`Buell at 104: “Both the bidirectional and unidirectional systolic arrays have been implemented on
`the Splash 2 programmable logic array, with versions for DNA and protein sequences”
`
`Buell at 108: “Two systolic arrays for computing the edit distance between two genetic sequences have
`been presented and their implementations on Splash 2 described. The bidirectional and unidirectional
`arrays have maximum throughputs or 5.5 and 12 million characters per second, respectively, for DNA
`database search. Compared to implementations of the dynamic programming algorithm on several
`contemporary workstations and minicomputers, the Splash 2 implementations promise to deliver several
`orders of magnitude better performance”
`
`Buell at Figure 8.5 [emphasis added]:
`
`
`28
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2051, p. 28
`
`

`

`Exhibit C-12: “Splash 2: FPGAs in a Custom Computing Machine,” D.A. Buell et al., 1996 (“Buell”)
`
`
`
`Asserted Claim of ’324
`Patent
`
`Exemplary Disclosure of Buell
`
`
`Buell at Figure 8.9 [emphasis added]:
`
`
`
`
`29
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2051, p. 29
`
`

`

`Exhibit C-12: “Splash 2: FPGAs in a Custom Computing Machine,” D.A. Buell et al., 1996 (“Buell”)
`
`
`
`Asserted Claim of ’324
`Patent
`
`Exemplary Disclosure of Buell
`
`
`
`
`
`Buell, at Figure 8.8:
`
`[1N] utilizing a first of
`said instantiated
`functional units to
`
`30
`
`
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2051, p. 30
`
`

`

`Exhibit C-12: “Splash 2: FPGAs in a Custom Computing Machine,” D.A. Buell et al., 1996 (“Buell”)
`
`Exemplary Disclosure of Buell
`
`
`
`Asserted Claim of ’324
`Patent
`operate upon a
`subsequent data
`dimension of said
`calculation
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`31
`
`
`
`
`
`
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2051, p. 31
`
`

`

`Exhibit C-12: “Splash 2: FPGAs in a Custom Computing Machine,” D.A. Buell et al., 1996 (“Buell”)
`
`
`
`Asserted Claim of ’324
`Patent
`
`Exemplary Disclosure of Buell
`
`
`
`
`
`
`
`
`
`Buell at Figure 8.7:
`
`[1P] forming a first
`computational loop;
`and
`
`
`
`[1Q] substantially
`concurrently utilizing a
`second of said
`
`
`Buell at 101: “A comparison is performed when a source character and a target character meet in a PE.”
`
`Buell at time step 3 of Figure 8.8 [emphasis added]:
`
`32
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`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2051, p. 32
`
`

`

`Exhibit C-12: “Splash 2: FPGAs in a Custom Computing Machine,” D.A. Buell et al., 1996 (“Buell”)
`
`Exemplary Disclosure of Buell
`
`
`
`Asserted Claim of ’324
`Patent
`instantiated functional
`units to operate upon a
`previous data dimension
`of said calculation
`
`
`
`
`
`Buell at time step 4 of Figure 8.8 [emphasis added]:
`
`
`
`
`
`
`[1R] forming a second
`computational loop
`
`Buell at Figure 8.7:
`
`33
`
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`
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`
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2051, p. 33
`
`

`

`Exhibit C-12: “Splash 2: FPGAs in a Custom Computing Machine,” D.A. Buell et al., 1996 (“Buell”)
`
`
`
`Asserted Claim of ’324
`Patent
`
`Exemplary Disclosure of Buell
`
`[1S] wherein said
`systolic implementation
`of said calculation
`enables said first
`computational loop
`and said second
`computational loop to
`execute concurrently
`
`
`Buell, at time step 3 of Figure 8.8, [emphasis added]:
`
`
`
`
`
`34
`
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`
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`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2051, p. 34
`
`

`

`Exhibit C-12: “Splash 2: FPGAs in a Custom Computing Machine,” D.A. Buell et al., 1996 (“Buell”)
`
`Asserted Claim of ’324
`Patent
`
`Exemplary Disclosure of Buell
`
`[1T] and pass
`computed data
`seamlessly between
`said computational
`loops.
`
`
`Buell at 102: “At the end of the computation the resulting edit distance [PEDist] is transported out of the
`array on the distance streams. A partial trace of the bidirectional array when comparing the sequences
`TCT AGACC and GCAT AAGC is shown in Figure 8.8.”
`
`Buell at time step 4 of Figure 8.8 [emphasis added]:
`
`
`
`
`
`
`[17] The method of
`claim 1 wherein said
`calculation comprises a
`search algorithm for
`an image search
`
`
`
`In addition, or alternatively, this limitation is disclosed in at least the following references (see
`corresponding chart for disclosure in each reference): Splash, Indeck, Greenberger, Parvin, and Amira. At
`least for the reasons articulated in the accompanying pleading, one skilled in the art would have been
`motivated to combine each of these references with the present reference at the time the asserted patent
`was filed.
`
`
`
`
`
`
`
`35
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`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2051, p. 35
`
`