in order to deliver high computational throughputs
`through parallelism detection, the data-flow approach has
`been demonstrated. While conventional explicit parallel-
`ism approaches can sometimes show high performance,
`they req uire afocused effort on the part ofthe programmer
`in order to understand and describe the parallelism of the
`programmed problem. On the other hand, the functional
`programming approach allows the implicit detection of
`parallelism at runtlme. At the same time, only a fraction of
`the programming effort needs to be expended. This shows
`that one of the main advantages brought by a data-flow
`architecture is its programmability which, intu rn,translates
`. into higher performance for a given amount of program-
`ming effort. In addition, the approach is completely scal-
`able and the configuration of the multiprocessor systems
`can be adapted to the size of the application. On the other
`hand, the runtime scheduling of instructions imposesover-
`head on regular operations and lowers the expectable per-
`formance. This expected loss of performance has been
`traced to the high level of resolution [small granularity}
`which has been adopted by many data-flow projects. in a
`signal processing application, the regularity ofthe low level
`of processing makes it more appropriate to design a system
`with multiple levels of resolution. indeed, we have dem-
`onstrated here an architecture with two hierarchy con-
`structs. The lowest consists in a layer of vector processors
`whilethe highest provides atrue data-flow approach. Future
`research will study how multiple layers could even include
`systolic arrays as leaf processorsfor dedicated applications.
`These would then be included into multiple hierarchy sys-
`terns.
`
`In summary, it can be said that the data-driven principles
`ofexecution are a necessity inthe design 61‘ multiprocessor
`systems, be they incorporated at design, compile, or run-
`time. The granularity of the scheduling model often pre-
`sents a tradeoff between delivering maximum amounts of
`parallelism and reducing communication costs.
`
`ACKNOWLEDGMENT
`
`The author would like to gratefully acknowledge the many
`helpful suggestions for improvement made by the anon-
`ymous referees.
`
`REFERENCES
`
`{3]
`
`[1] W. B. Ackerman, "Data-flow languages," in Proc. 1979 Nat.
`ComputerConf.lNewYork,NY,June-l~7),vol.48. Arlington,
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`1066, Nov. 1932.
`
`GAUDIOT: DATA-DRIVEN MULTICOMPUTERS IN USP
`
`1233
`
`Petitioner Microsoft Corporation - Ex. 1066, p. 200
`Petitioner Microsoft Corporation - EX. 1066, p. 200
`-———————-—._...______________________
`
`

`

`[34]
`
`[35]
`
`[36]
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`{37]
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`cessing ll. New York, NY: [EEE PRESS, 1986.
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`chronous data flow programs for digital signal processing,"
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`NAL—A data flow-oriented language for signal processing,"
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`graphic formulation of spotlight-mode synthetic aperture
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`eration tor horizontal architectu res: compiler techniques and
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`Architecture, June 1982.
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`tecture: Architectural concepts," iEEE Trans. Comput, vol.
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`in ("ontrofSystemg C. T. Leondes, Ed., vol. 3, pp. 219—264, 1966.
`
`
`
`lean-Luc Gaodiot (Member, IEEE) was born
`in Nancy, France, in 1954. He received the
`Dipldme d’l ngénieur from the Ecole Super-
`ieure d'lngénleurs en Eiectrotechnlque et
`Electronique, Paris, France, in 1976, and the
`M.Sc. and Phi]. degrees in computer sci-
`ence from the University of California, Los
`Angeles, in 1977 and 1982, respectively.
`His experience includes microprocessor
`systems design at Teledyne Controls, Santa
`Monica, CA (19794980) and research in
`innovative architectu res for the TRW Tech nology Research Center,
`El Segundo, CA (1980—1982). Since graduating in 1962, he has been
`on the flaw lty ofthe Department of Electrical Engi neeri ng-Systems,
`University of Southern California, where he is currently an Assis-
`tant Professor. His research interests include data-flow architeo
`tu res, fault-tolerant multiprocessors, and parallel logic program-
`ming systems. In addition to his academic duties. he has consulted
`for several aerospace companies in the Southern California area.
`Dr. Gaudiot is a member of ACM.
`
`1:34
`
`PROCEEDINGS OF THE IEEE, VOL. 75, N0. 9, SEPTEMBER 1987
`Petitioner Microsoft Corporation - Ex. 1066, p. 201
`Petitioner Microsoft Corporation - EX. 1066, p. 201
`—--—-———-————————_.._________________________
`
`

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`
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`Petitioner Microsoft Corporation - EROflOEfidpfibQiit/I
`Petitioner Microsoft Corporation - Ex. 1066, p. 209
`———————-——_._._______________
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`Petitioner Microsoft Corporation - reseaméipsfi W
`Petitioner Microsoft Corporation - Ex. 1066, p. 210
`———————-—__..__________________________
`
`

`

`(cid:3) (cid:3) (cid:3) (cid:3) (cid:3) (cid:3) (cid:3)
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`Petitioner Microsoft Corporation - Ex. 1066, p. 211
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`journal of Parallel and Distributed Computing
`Volume 10, Issue 4. December 1990. Pages 33384-8
`Architectures for statically scheduled dataflow (Article)
`Ashford LeeI E., Bier,J.C.
`,2,
`University ofCalifornia Berkeley, Berkeley, CA 94720, United States
`
`v VIEW references (52)
`Abstract
`When dataflow program graphs can be statically scheduled, little run-time overhead (software or hardware) is
`necessary. This paper describes a class ofparallel architectures consisting ofvon Neumann processors and one or
`more shared memories, where the order ofshared-mernory accesses is determined at compile time and enforced at
`run time. The architecture is extremely lean in hardware. vet fer a set of important applications it can perform as well
`as any shared~memory architecture. Dataflow graphs can be mapped onto it statically. Furthermore, itsupports shared
`data structures without the run—time overhead oft-structures. A software environment has been constructed that
`automatically maps signal processing applications onto a simulation ofsuch an architecture, where the architecture is
`.
`.
`.
`.
`.
`.
`.
`.
`Implemented using Motorola DSP96U02 microcomputers. Static(compilemme) scheduling Is possible for a subclass
`ofdatafiow program graphs where the firing pattern ofactors is data independent This model is suitable for digital
`signal processing and some other scientific computation. It supports recurrences. manifest iteration. and conditional
`assignment. However, it does not support true recursion, data-dependent iteration, or conditional evaluation. An
`effort is under way to weaken the constraints ofthe model to determine the implications for hardware design. ©
`1990,
`
`iSSN: 07437315
`CODEN:JPDCE
`Source Type: Journal
`Original language: English
`
`DOI: 1G.1015f0743-7315(90}90034-M
`DocumentType: Article
`_
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`References (52)
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`1
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`2
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`Arvincl. Gostelow, K.P.
`The U-lnterpreter
`(1982) Computer, 15 (2), pp. 42-49. Cited 95 times.
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`View at Publisher
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`Arvind. Nikhil, Pingali
`i-structures: Data structures for parallel computing
`(1987) Computation Structures Group Memo 269
`MIT, (revised Mar. 1989) ACM Trans. Programming Languages Systems, to appear
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`Metrics G) View all metrics)
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`16
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`gag-a; Media and (item-,5
`beyond Scopus.
`
`v
`
`Cited by 16 documents
`,
`y
`A representation for genetic-
`algorithm—based multiprocessor
`task scheduling
`
`Jelodar. M5. , Fakhraie. S.N. ,
`Montazeri, F.
`
`{2006) 2006 EH? Congress on
`Evolutionary Computation, CEC
`200.6
`
`5°“tenti°"'c°"sf'°”?
`multiprocessor DSP systems
`ransactlon ordering In
`Khandelia, M. , Bambha, N.K. ,
`Bhattacharyya, 5.5.
`(2006} iEEE Fansactions on
`Signal Processing
`Ciptirnal scheduling Dfdlg'tal
`signal processmg data-flow
`graphs using shortest-path
`algorithms
`Shatnawi, A.
`, Ahmad. MD. ,
`Swamy, M.N.5.
`{2002) Computerjournal
`
`View all 16 citing documents
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`is cited in Scopus:
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`I - ‘
`'
`Petitioner Microsoft Corporation - Ex. 1066, p. 212
`Petitioner M1crosoft (53" gr; Tfificgfl,Ӥ 0W6, p. 212
`———————————______________________
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`3
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`Arvind. Private communication. 1989.
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`4
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`Bier.JefFrey C, Lee, Edward A.
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`Processors, pp. 280-283. Cited 4 times.
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`Bienjefirrey C., Lee. Edward A.
`A class ofmultiprocessor archltectures for real—time DSP
`{1990) Proceedings - {EEE internationai Symposium on Circuits and Systems. 4. pp. 2622—2625. Cited 4
`times.
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`Burton. Sleep
`Executing functional programs on a virtual tree ofprocessors
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`Task Allocation and Scheduling
`Digital Signal Processing
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`Konstantinides. K. , Kaneshiro,
`RJ'- ’ Tani, J-R‘
`{1990)iEEE Transactions on
`Acoustic, Speech. and Signai
`Processing
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`r parallel programs
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`fictive—pass scheduling algorithm
`Kim. D_ ’ Yi, 3.43.
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`4
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`7
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`Chase
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`A pipelined data flow architecture for signal processing: The NEC uPD7231
`(1984) VLSI Signai Processing. Cited 4 times.
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`Chu, W.W., Holloway. L.J., La n, M.-T., Efe. K.
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`(1987) IEEE fiansactions on Computers, C—36 (6), pp. 667-679. Cited 94 times.
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`10 Cohen. 6., Dubois, D., Quadrat.J.P., Viot. M.
`A Linear-System-Theoretic View of Discrete-Event Processes and its Use For
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`igggu'g-mfigg View at Publisher
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`Petitioner Microsoft Corporation - Ex. 1066, p. 213
`Petitioner Microsoft Corporation - EX. 1066, p. 213
`-—————————_._.___________________
`
`

`

`11 Cornish,Hogan,Jensen
`The Texas Instruments distributed data processor
`(1979} Free Louisiana Computer Exposition, pp. 189-193. Cited 7 times.
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`Petitioner Microsoft Corporation - Ex. 1066, p. 214
`Petitioner Microsoft Corporation - EX. 1066, p. 214
`_________________________________
`
`

`

`20 Geo. Tio, Hum
`Design ofan efficient dataflow architecture without datafiow
`(1988) Pros. international Coni‘ierence on Fifth Generation Computer Systems. Cited 10 times.
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`25 Ha, Lee
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`A semantic model of reference counting and its abstraction
`(1986) Proc. 1986/4014 Conference on Lisp and Fundionai Programming. pp. 351363. Cited 70 times.
`MIT. Cambridge. MA
`
`Petitioner Microsoft Corporation - Ex. 1066, p. 215
`Petitioner Microsoft Corporation - EX. 1066, p. 215
`———————-——___.__________________________
`
`

`

`29
`
`iannucci
`
`A dataflowivon Neumann hybrid architecture
`(1988) Tech. Rep. TR—418. Cited 17 times.
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`32 Kelier, Lin,Tana|ra
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`aii “Mani-{Mfg View at