Product Obsolete/Under Obsolescence
`
`APPLICATION NOTE
`
`2: XILINX®
`
`Xiiinx FPGAs: A Technical Overview
`
`for the First-Time User
`
`
`
`Application Note by Peter Alfke
`XAPP 097 December 12, 1998 (Version 1.3)
`
`Summary
`
`This Application Note introduces the reader to the various Xilinx product family‘s logic components and provides a general
`overview of what the logic components within the devices are used for.
`1'
`
`Xilinx_ Families
`Spartan TM. X03000. X04000. X05000. X09000
`
`Introduction
`
`In the Spartan“. X03000, X04000. and X05200 device
`families, Xilinx offers several evolutionary and compatible
`generations of Field Programmable Gate Arrays (FPGAs).
`Here is a short description of their common features.
`
`Every Xilinx FPGA performs the function of a custom LSI
`circuit. such as a gate array, but the FPGA is user-program-
`mable and even reprogrammable in the system. Xilinx sells
`standard off-the-shelf devices in multiple families. and
`many different
`sizes,
`speeds,
`operating—temperature
`ranges, and packages. The user selects the appropriate
`device and then enters the logic design into the Xilinx
`development system software running on a P0 or worksta-
`tion. and then loads the resulting configuration file into the
`Xilinx FPGA.
`
`This overview describes two aspects of Xilinx FPGAs; what
`logic resources are available to the user and how the
`devices are programmed.
`
`user Logic
`Different in structure frOm traditiOnal logic circuits, or PALs,
`EPLDs and even gate arrays, the Xilinx FPGAs implement
`combinatorial logic in small lookuup tables (16 x ‘i ROMs);
`each such table either feeds the D—input of a flip—flop or
`drives other logic or lfO. Each FPGA contains a matrix of
`identical
`logic blocks, usually square, from 8 x 8 in the
`X04002XL to 68 x 68 in the X040125XV. Metal lines of var-
`
`ious lengths run horizontally and vertically in-between
`these logic blocks, selectively interconnecting them or con-
`necting them to the inputioutput blocks.
`
`Logic Blocks
`
`This modular architecture is rich in registers and powerful
`function generators that can implement any function of up
`to five variables. For wider inputs. function generators are
`easily concatenated. Generous on—chip buffering makes
`logic block delays insensitive to loading by the interconnect
`
`structure. but interconnect delays are layout dependent and
`must be analyzed ifthey are performance critical.
`
`Clocks
`
`Clock lines are well-buffered and can drive all flip-flops with
`< 2 ns skew from chip cornerto corner, even throughout the
`biggest device. The user need not worry about clock load-
`ing or clock-delay balancing. or about hold time issues on
`the chip,
`if the designated global clock lines are used.
`There are eight such global low-skew clock lines in Spartan
`and X04000 devices, four in X05200 devices, and two in
`X03000 devices.
`
`Special Features
`
`internal bidirectional busses.
`All devices can implement
`The Spartan, X04000 and X05200 family devices have
`dedicated fast carry circuits that improve the efficiency and
`speed of adders. subtractors, comparators. accumulators
`and synchronous counters. These families also support
`boundary scan on every pin.
`
`Spartan and X04000 series devices can use any of their
`logic block look-up tables as distributed RAM, with synchro-
`nous write and dual-port options. This makes FlFOs, shift
`registers and DSP distributed multipliers very fast and effi-
`cient.
`
`|nputsf0utputs
`
`All device pins are available as bidirectional user IIO, with
`the exception of the supply connections and a few dedi-
`cated configuration pins. The outputs on X03000 and
`X05200 devices always swing rail-to-rail. Spartan and
`X04000Ei‘EX outputs have a global choice between “TTL =
`totem pole” or "CMOS = rail-to-rail” output swing.
`
`The original families operate from a 5 V supply. but have
`added 3.3 V variants. These 3.3 V devices, designated by
`an "I." in their product name, have rail-to-rail outputs.
`
`Inputs of all 5 V deviCes can be globally configured for
`either 'l'l'L input thresholds or CMOS thresholds (50% of
`
`
`
`XAPP 097 December 12, 1998 (Version 1.3)
`
`14-5
`
`Petitioner Microsoft Corporation - Ex. 1045, p. 5
`Petitioner Microsoft Corporation - EX. 1045, p. 5
`
`

`

`Product Obsolete/Under Obsolescence
`
`2: )(ILINXa
`Xilinx FPGAs: A Technical Overview for the First-Time User
`
`Vcc). All 3.3 V devices have CMOS input thresholds. All
`inputs have hysteresis (Schmitt-trigger action) of 100 to
`200 mV. SpartanXL and X04000XL inputs are uncondition-
`ally 5 Vtolerant, even while their supply voltage is as low as
`0 V. This eliminates all power-supply sequencing problems.
`
`Global Reset
`
`All Xilinx FPGAs have a global asynchronous reset input
`affecting all device flipwfiops. In the Spartan, X04000 and
`X05200 family devices, any pin can be configured as a
`reset input; in X03000—families, RESET is a dedicated pin.
`
`Power Consumption
`
`Since all Xilinx FPGAs use CMOS SRAM technology. their
`quiescent or stand-by power consumption is very low, micro-
`watts for X03000 devices. max 25 mW to 75 mW for the
`other 5 V families. The operational power consumption is
`totally dynamic, proportional to the transition frequency of
`inputs, outputs, and internal nodes. Typical power consump-
`tion is between 100 mW and 5 W, depending on device size,
`clock rate, and the internal logic structure.
`
`All devices monitor Vcc continuously and shut down when
`Vcc drops to 3 V (2 V for 3.3 V devices). The device then
`3-states all outputs and prepares for reconfiguration.
`
`Programming or Configuring
`
`Design Entry‘
`A design usually starts as a schematic, drawn with one of
`the popular CAE tools. or as a High—Level Language textual
`description. Most CAE tools have an interface to the Xilinx
`development system, running on PCs or workstations.
`
`Design Implementation
`
`After schematic or HDL design entry, the design is read by
`the Xilinx software. The software first partitions the design
`into logic blocks, then finds a near-optimal placement for
`each block, and finally selects the interconnect routing.
`This process of partitioning the logic, placing it, and routing
`the interconnects rUns automatically, but the user may also
`affect the outcome by imposing specific timing constraints.
`or selectively editing critical portions of the design. The
`user thus has a wide range of choices between a fully auto«
`matic implementation and detailed involvement in the lay—
`out process.Once the design is complete, a detailed timing
`report is generated and a serial bitstream is produced
`which can be downloaded into the FPGA, into a PROM pro-
`grammer, or made available as a computer file.
`
`formthe intended digital function. The number of configura-
`tion bits varies with device type, from 14,819 hits for the
`smallest device (X03020) to 2,797,040 bits for the largest
`device (X040125XV). Multiple FPGA devices can be
`daisy-chained and configured with a common concate—
`nated bitstream. Device utilization does not change the
`number of configuration bits. Inside the device, these con-
`figuration bits control or define the combinatorial circuitry,
`flip-flops, interconnect structure, and the liO buffers, as well
`as their pull—up or pull-down resistors, input threshold and
`output slew rate.
`
`Power—up Sequence
`
`the device waits for Vcc to reach an
`Upon power-up,
`acceptable level, then clears the configuration memory,
`holds all internal flip-flops reset, and 3-states the outputs
`but activates their weak pull-up resistors. The device then
`initiates configuration, either as a master, (clocking in a
`data stream from an external source). or as a slave
`(accepting clock and data stream from an external source).
`
`Bit-Saris.l Configuration
`
`The Xilinx serial PROM is the simplest way to configure the
`FPGA, using only three or four device pins. Typical configu—
`ration time is around one microsecond per bit, but this can
`be reduced. Configuration thus takes from a few millisec-
`onds to a several hundred milliseconds. Serial PROMs
`
`come in sizes from 36K to 4M bits and can be daisy
`chained to store a longer bitstream.
`
`Byte-Paraiiei Configuration
`
`Xilinx SpartanXL, X03000, X04000, and X05200 FPGA
`devices can also be configured with byte-wide data, either
`from a PROM or from a microprocessor. Parallel configura-
`tion modes are not faster than serial modes except in Spa—
`tanXL and X04000XLA.
`
`Reconfiguration
`
`The user can reconfigure the device at any time by pulling
`the PROGRAM pin Low, to initiate a new configuration
`sequence. During this process, outputs not used for config-
`uration are 3—stated. Partial reconfiguration is not possible.
`For high—volume high-density applications, Xilinx offers
`lower cost, fixed programmed HardWire versions.
`
`Readback of Configuration Data
`
`After the device has been programmed, the content of the
`configuration "shift register“ can be read back serially, with-
`out intertering with device operation.
`
`Configuring the FPGA
`
`Quality and Reliability
`
`The user then exercises one of several options to load this
`file into the Xilinx FPGA device, where it
`is stored in
`latches, arranged to resemble one long shift register. The
`data content of these latches customizes the FPGA to per—
`
`Since 1985. Xilinx has shipped over 100 million FPGA
`devices. Industry leading quality and reliability (ESD pro-
`tection, AOL and FIT) and aggressive price reductions have
`undoubtedly contributed to this success.
`
`
`
`1 4-6
`
`XAPP 09? December 12, 1998 (Version 1.3)
`
`Petitioner Microsoft Corporation - Ex. 1045, p. 6
`Petitioner Microsoft Corporation - EX. 1045, p. 6
`
`