UNITED STATES DISTRICT COURT
`WESTERN DISTRICT OF WASHINGTON
`AT SEATTLE
`
` SRC LABS LLC and SAINT REGIS
`MOHAWK TRIBE,
`Plaintiff,
`
`v.
`MICROSOFT CORPORATION,
`Defendants.
`
`Case No. 2:18-cv-00321-JLR
`DECLARATION OF DR. HENRY
`HOUH IN SUPPORT OF
`DEFENDANT’S CLAIM
`CONSTRUCTION POSITIONS
`
`I, Henry H. Houh, Ph.D., do hereby declare as follows under penalty of perjury under the
`
`laws of the State of Washington and the United States:
`
`I.
`
`INTRODUCTION
`
`I, Dr. Henry Houh, am over eighteen years of age, and I am competent to testify as
`to the matters set forth herein if I am called upon to do so.
`I have been engaged by Microsoft Corporation (“Microsoft”) to provide expert
`analysis testimony in the above-captioned matter. In particular, I have been asked to provide my
`opinions on the proper construction of certain claim terms recited in U.S. Patent Nos. 6,247,110
`(“110 Patent”); 6,076,152 (“152 Patent”); 7,225,324 (“324 Patent”); 7,620,800 (“800 Patent”),
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2058, p. 1
`
`

`

`6,434,687 (“687 Patent”); and 7,421,524 (“524 Patent”) (i.e., “the Patents-in-Suit”). I have also
`been asked to provide my opinions on the qualifications of a person of ordinary skill in the art at
`the time of the inventions claimed in the Patents-in-Suit.
`In reaching my opinions, I have reviewed the documents cited herein and relied on
`
`my many years of knowledge and experience in the field of information retrieval (outlined in
`Section II). I am being compensated at a rate of $620 per hour for my study and other work in this
`matter. I am also being reimbursed for reasonable and customary expenses associated with my
`work and testimony in this investigation. My compensation is not contingent on the outcome of
`this matter or the specifics of my testimony.
`BACKGROUND AND EXPERIENCE
`II.
`
`My professional career has spanned more than 25 years. As set forth in my
`
`curriculum vitae, a copy of which is submitted as Attachment 1, during these years I have gained
`extensive experience in computer system and networking architectures, including the design and
`use of reconfigurable logic in such systems.
`I received a Ph.D. in Electrical Engineering and Computer Science from the
`
`Massachusetts Institute of Technology (“MIT”) in 1998. I also received a Master of Science
`degree in Electrical Engineering and Computer Science in 1991, a Bachelor of Science Degree in
`Electrical Engineering and Computer Science in 1989, and a Bachelor of Science Degree in
`Physics in 1990, all from MIT.
`As an undergraduate student, I had a strong interest in digital design and computer
`
`architecture. The core EECS course on Computer Architecture, also known as 6.004 Computation
`Structures, involved building a microcoded computer from discreet components and programming
`the microcoded instructions through a series of lab projects. The final optional lab project was to
`optimize the hardware and/or software of the computer. My hardware and software optimizations
`produced a speed up of roughly thirty times faster for executing the benchmark programs. Based
`on the results of the final project, I was invited to become a laboratory teaching assistant (lab TA)
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2058, p. 2
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`

`

`for the class, and I also secured an Undergraduate Research Opportunities Program (UROP) with
`the course professor, Steve Ward, as part of the Computer Architecture Group (CAG) in the
`Laboratory for Computer Science. I later became the head lab TA for 6.004, and I revised and
`rewrote some of the lab assignments. During the second half of my senior year, I was admitted to
`the graduate school at MIT and I became a full course TA for 6.004, a role only graduate students
`were allowed to undertake. I was a TA for 6.004 three times, and was the head TA the final time.
`6.004 was a required class for all undergraduate electrical engineering and computer science
`students. The topics taught in 6.004 included computer architecture, interpreters, data path details,
`symbolic microcoding, vertical vs horizontal microcoding, microarchitecture, addressing modes,
`RISC vs CISC, machine language, assemblers, microinterpreter organization and data structures,
`memory organization, bus and communication protocols, multi-level memories, cache
`organization and coherence, virtual memory, memory mapping, memory protection, operating
`systems, pipelined machines, and multiprocessors.
`During my graduate studies, my thesis research focused on communications and
`
`data networking. To fulfill my course requirements for a Ph.D, I took graduate courses in
`communications networks, optical communications, digital signal processing, and data
`networking, among others.
`As part of my doctoral research at MIT from 1991-1998, I worked as a research
`
`assistant in the Telemedia Network Systems (“TNS”) group at the Laboratory for Computer
`Science. The TNS group built a high-speed gigabit ATM interconnect network and applications
`which ran over the network, such as remote video capture (including audio), processing and
`display on computer terminals. I helped design the core network components (such as the ATM
`switch), and I designed and built the high speed ATM links, and designed and wrote the device
`drivers for the host interface cards.
`I designed several versions of the host interface card to connect our workstations to
`
`our high speed network. Each host interface card connected to the computer’s peripheral bus,
`specifically the DEC TURBOchannel bus, used in the DEC 3000 and 5000 Alpha workstations.
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2058, p. 3
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`

`

`Each board used Programmable Array Logic for the control logic. The initial version of the host
`interface operated in programmed I/O mode, where the CPU polled the board and initiated all the
`data reads and writes from/to the host interface card. The next version of the host interface was a
`DMA bus master, and could transfer data directly into system memory without intervention of the
`CPU.
`
`Interconnection of various endpoints in our networking system required the setup
`
`of end-to-end virtual circuits which required, for each switch in the connection path, the switch’s
`header remapping tables to be configured for each virtual circuit required. I developed and
`implemented our system’s protocol of controlling the content of these tables and the overall circuit
`setup.
`
`I also set up the group’s web server, which at the time was one of the first several
`
`hundred web servers in existence. The TNS group was the first group to initiate a remote video
`display over the World Wide Web. Vice President Al Gore visited our group in 1996 and received
`a demonstration of – and remotely drove – a radio controlled toy car with a wireless video camera
`mounted on it; the video was encoded by TNS-designed hardware, streamed over the TNS-
`designed network and displayed using TNS-designed software.
`I authored or co-authored twelve papers and conference presentations on our
`
`group’s research. I also co-edited the final report of the gigabit networking research effort with
`Professor David Tennenhouse and Senior Research Scientist David Clark. David Clark is
`generally considered to be one of the fathers of the Internet Protocol and served as Chief Protocol
`Architect for the Internet. With its focus on networking, the group, including myself, set up and
`maintained the network and computer systems. These systems included the networking on the
`workstations and desktops, the distributed file system, desktops and workstations, setting up and
`maintaining the distributed file system (Network File System) and the authentication system
`(Network Information Service, formerly known as Yellow Pages). Our system allowed users to
`log into any of the group’s workstations using their username/password, which allowed that all of
`the user’s files would be virtually mounted on that workstation as a networked home directory.
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2058, p. 4
`
`

`

`I defended and submitted my Ph.D. thesis, titled “Designing Networks for
`
`Tomorrow’s Traffic,” in January 1998. As part of my thesis research, I analyzed local-area and
`wide-area flows to show a more efficient method for routing packets in a network, based on traffic
`patterns at the time. My thesis also addressed real-time streamed audio and video. The network
`traffic that I analyzed was IP protocol traffic, including UDP and TCP.
`From 1997 to 1999, I worked at NBX Corporation, which was acquired by 3Com
`
`Corporation in 1999. During this time, I was a Senior Scientist and Engineer working in IP
`Telephony. NBX delivered the world’s first fully featured business telephone system to run over
`a data network, the NBX100. NBX was one of the first business phone systems to be configurable
`via a web interface. Users and administrators had access to varying levels of configuration for the
`phone system.
`As part of my work at NBX, I designed the core audio reconstruction algorithms
`
`for the telephones which depacketized the voice data and reconstructed the audio. In addition, I
`designed the voice data packet transmission algorithms. I created a system to capture and analyze
`network packets sent by devices in the NBX system for aid in testing and debugging. I also
`designed and validated the core packet transport protocol used by the phone system, used for every
`command instruction sent throughout the NBX system. In addition, I designed and oversaw the
`development of the underlying transport protocol used by the NBX100 phone system for reliable
`packet transport. That transport protocol was used by the NBX100 system and its successor. I
`wrote NBX’s first demonstration IP software stack, which added the capability for utilizing the
`NBX100 phone system on an IP network. NBX first demonstrated a phone in the NBX100 system
`working over the Internet in 1998 at a trade show in Las Vegas. I was later the lead architect in
`designing NBX’s next-generation highly scalable system, and, after NBX was acquired by 3Com,
`I did some work with 3Com’s cable equipment division, including demonstrating a working NBX
`IP phone system over 3Com’s cable equipment infrastructure using an early version of DOCSIS
`at a trade show in 1999. The NBX100 was the market’s leading business phone system to run on
`a data network for several years following its introduction. During that time, I became more
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2058, p. 5
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`

`

`familiar with the various standards relevant to Internet telephony as well as the problems which
`designers of commercial telephony operations were faced with in implementing VoIP.
`I, along with two of NBX’s founders, was awarded U.S. Patent No. 6,697,963
`
`titled “Telecommunication method for ensuring on-time delivery of packets containing time-
`sensitive data,” for some of the work we did while at NBX.
`After NBX, I worked at Teradyne, a test tool company primarily focused on
`
`semiconductors. Teradyne had recently acquired Hammer, a company that specialized in load and
`functional testing for telecommunications systems. The Hammer product is well known as a
`telecom test tool. Teradyne spun out Hammer and several other internal divisions into an
`independent company called Empirix. I became Chief Technologist of the Hammer division of
`Empirix. Empirix was a leader in VoIP network testing and monitoring.
`At Empirix, I laid out a new multi-year product vision for data network testing,
`
`secured internal funding for the effort, and led a team to deliver a new technology platform to the
`market in February 2001. This new product, PacketSphere, initially emulated network behavior
`so that wide-area VoIP connections could be tested in a lab. A later release allowed PacketSphere
`to generate high volumes of VoIP calls, including media streams, and to monitor the quality of
`VoIP voice streams. Later, the core technology was added to other Empirix products such as
`Empirix’s Hammer XMS to monitor thousands of VoIP media streams in real time to determine
`their quality. PacketSphere was Empirix’s most successful new platform introduction. Companies
`purchased the PacketSphere product to emulate an Internet Protocol network to see the effects of
`deploying their product on the Internet prior to launch. PacketSphere received several industry
`awards.
`
`The PacketSphere was based on a new class of processors known as network
`
`processors. I architected the system to include a core standard processor CPU and multiple
`processor cards which could plug into peripheral bus slots. Multiple network processor cards could
`be added to a system, and each card had the capability to access a central memory bank external
`to the network processor cards. We used the C-5 network processor, which itself consisted of
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2058, p. 6
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`

`

`sixteen channel processors and five co-processors. The channel processors could be programmed
`to work in parallel processing mode or in pipelined processing mode. Internally, all the processors
`had associated memory and access to all other processor memory through a flat memory space
`across all processor memories. Our group, which I managed, wrote all the specialized code for
`PacketSphere applications which ran on each multi-core chip, and different programs could run on
`portions of each network processor, or on each different network processor card.
`During my time at Empirix, I presented lectures on VoIP and data network testing
`
`to companies including Lucent Labs (formerly AT&T Bell Labs). I was also invited to present
`several guest lectures in a software engineering course at MIT. Since then, I have also participated
`twice as a unit lecturer (two weeks) in an experimental course that was taught by an Institute
`Professor (the highest award that a MIT Professor can achieve) and sponsored by the Chairman of
`the MIT Corporation (MIT’s board of trustees).
`From 2004 to 2008, I was employed by BBN Technologies Corp., a technology
`
`research and development company located in Cambridge, Massachusetts. BBN Technologies is
`a world-renowned company with expertise in acoustics, speech recognition, and communications
`technology. BBN Technologies staff have pioneered many internetworking technologies and
`Internet applications, and built some of the world’s largest government and commercial data
`networks.
`
` My duties and responsibilities at BBN Technologies generally included
`commercialization of the technologies developed by BBN Technologies, which included spinning
`off companies and growing commercial businesses in-house. More particularly, I was involved in
`utilizing the award-winning AVOKE STX speech recognition technology to create the public
`audio/video search engine EveryZing (formerly known as PodZinger) which was spun out into a
`stand-alone company now known as RAMP, Inc. PodZinger won the 2006 MITX Technology
`Award for best Web 2.0 Application and was also named the 2006 Forbes Favorite Video & Audio
`Search Engine, beating out Google, Yahoo, and other companies. After managing the creation of
`the initial prototype system, PodZinger built out a full streaming audio and video search solution
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2058, p. 7
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`

`

`when I was the Vice President of Operations and Technology there. I was also involved in the
`Boomerang Mobile Shooter Detection project as the Vice President of Engineering for the
`program. The Boomerang system was deployed to Iraq and Afghanistan, and was credited with
`saving many lives.
`From 1989 to 1990, I worked at AT&T Bell Laboratories on optical computers.
`
`This work generated six peer-reviewed papers, and multiple U.S. and European patent applications
`in which I was named as a co-author or inventor. I also interned at AT&T Bell Laboratories in
`1987 and 1988. Additional relevant experience in the field of optical computers is listed in my
`curriculum vitae, a copy of which is attached as Exhibit A.
`I am a named inventor on several patents and published patent applications,
`
`including: U.S. Patent No. 6,967,963, entitled “Telecommunication Method for Ensuring On-time
`Delivery of Packets Containing Time- Sensitive Data”; U.S. Patent Application Publication No.
`2002/0015387, entitled “Voice Traffic Packet Capture and Analysis Tool for a Data Network”;
`U.S. Patent Application Publication No. 2002/0016708, entitled “Method and Apparatus for
`Utilizing a Network Processor as Part of a Test System”; U.S. Patent Application Publication No.
`2002/0016937, entitled “Method and Apparatus for Utilizing a Network Processor as Part of a Test
`System”; and U.S. Patent No. 7,590,542, entitled “Method of Generating Test Scripts Using a
`Voice-Capable Markup Language.”
`Based at least on my education and experience, I consider myself an expert in
`
`computer system and networking architectures, and have extensive experience using
`reconfigurable logic in such systems. My qualifications and experience are set forth in more detail
`in my Curriculum Vitae, which is attached.
`MATERIALS REVIEWED
`III.
`
`In performing my analysis I have reviewed the Patents-in-Suit, corresponding
`
`prosecution histories, and the references cited herein.
`LEGAL STANDARDS USED IN MY ANALYSIS
`IV.
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2058, p. 8
`
`

`

`Although I am not an attorney and do not offer any opinions on the law, I have been
`
`informed of certain legal principles that I have relied on in reaching the opinions set forth in this
`Declaration. I describe those principles of which I have been informed in the relevant sections
`below.
`
`V.
`
`THE PERSON OF ORDINARY SKILL IN THE ART
`
`I have been informed that a person of ordinary skill in the art (or a “Skilled Artisan”)
`
`is a hypothetical person who is presumed to have known all of the relevant prior art as of the
`priority date. I have been informed that factors that may be considered in determining the level of
`ordinary skill in the art may include: (a) the educational level of the inventor; (b) the type of
`problems encountered in the art; (c) prior art solutions to those problems; (d) the rapidity with
`which innovations are made; (e) the sophistication of the technology; and (f) the educational level
`of active workers in the field.
`I have been asked to provide my opinion as to the qualifications of the person of
`
`ordinary skill in the art to which the Patents-in-Suit pertains, which I provide in detail below.
`
`A.
`
`The 152 and 110 Patents
`
`One of ordinary skill in the art in the field of the 152 and 110 Patents in the 1997
`
`time frame would have been a person with a Bachelor’s degree in electrical engineering, computer
`engineering, computer science, or in a related field, and four years of experience with the design
`or use of field programmable gate array based systems. Alternatively, such a person would have
`had an advanced degree in one of those fields and two years of related experience. Moreover, such
`a person would have been knowledgeable about computer architectures and how FPGAs could be
`included in them. Such a person also would have been knowledgeable about software algorithms
`that could be implemented on FPGAs and how to configure FPGAs to carry out such
`implementation
`
`B.
`
`The 524 Patent
`
`
`
`A person of ordinary skill in the art in the field of the 524 Patent in the 1997 time
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2058, p. 9
`
`

`

`frame would have been a person with a Bachelor’s degree in Electrical Engineering, Computer
`Engineering, Computer Science, or in a related field, and four years of experience with the design
`or use of field programmable gate array based systems or network adapters. Alternatively, such a
`person would have had an advanced degree in one of those fields and two years of related
`experience. Moreover, such a person would have been knowledgeable about computer
`architectures and how FPGAs could be included in them and also knowledgeable about computer
`networks and how FPGAs could interact with them. Such a person also would have been
`knowledgeable about algorithms that could be implemented on FPGAs and how to configure
`FPGAs to carry out such implementation.
`
`C.
`
`The 687 Patent
`
`A person of ordinary skill in the art in the field of the 687 Patent in the 2001 time
`
`frame would have been someone with an advanced degree in electrical or computer engineering,
`or computer science with substantial study in computer architecture, hardware design, and
`computer algorithms. In addition to the educational background, that person would also have had
`at least two years’ experience working in the field. Alternatively, that person would have had a
`bachelor’s degree covering those disciplines and at least three years working the field. Such a
`person would also have been knowledgeable about the programming, design and operation of
`computer systems based on reconfigurable components such as FPGAs (field programmable gate
`arrays).
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2058, p. 10
`
`

`

`D.
`
`The 324 and 800 Patents
`
`A person of ordinary skill in the art in the field of the 324 and 800 Patents in the
`
`2002 time frame would have had an advanced degree in electrical or computer engineering, or
`computer science with substantial study in computer architecture, hardware design, and computer
`algorithms, and at least three years’ experience working in the field. Alternatively, that person
`would have had a bachelor’s degree covering those disciplines and at least four years working the
`field. Such a person would have been knowledgeable about the programming, design and
`operation of computer systems based on reconfigurable components such as FPGAs (field
`programmable gate arrays), including computer systems for performing systolic and data driven
`calculations.
`
`VI.
`
`COMPUTER ARCHITECTURE TUTORIAL
`Overview
`A.
`
`Three of the patents addressed by this report – the 152, 110, and 524 patents – are
`
`generally directed to computer architectures employing a reconfigurable computing element, such
`as a field programmable gate arrays, or “FPGA.” The other three patents addressed here – the 687,
`324 and 800 patents – are directed to specific types of programming that can be implemented on
`reconfigurable computers, e.g., computer systems employing FPGAs.
`Computer systems, both today and in the prior art, generally include three different
`
`types of components – processing elements, memory and input/output devices (often referred to
`as “I/O” or “peripherals”). Processing elements – and there may be more than one in a computer
`system – can be thought of as the “brains” of the system. They are the component(s) that perform
`that actual processing, or manipulation, of data for the user. A central processing unit, or CPU, is
`a typical example.
` Memory is a term generally denoting a class of devices that store digital information
`for later retrieval. One of the most common types of memory used both today and in the prior art
`is called dynamic random access memory, or “DRAM.”
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2058, p. 11
`
`

`

`I/O generally denotes anything else in the computer system that receives
`
`information from the outside world (input), transfers information to the outside world (output), or
`does both. A keyboard, for example, is an input device because it is used to input data (keystrokes)
`from the user to the system. A printer is an output device because it is sent data to be printed. A
`network interface card is both an input and an output device because a computer system can use it
`to both send and receive network messages.
`The various components of a computer system are usually connected together by
`
`one or more “busses.” A “bus” in this context is one or more wires associated with a protocol for
`communicating information to components connected to the bus by varying voltages on the wires.
`There are many different kinds of busses, most of which have been specifically designed for a
`particular kind of communication or to optimize communications with a particular type of device.
`For example, many types of computer memory are designed to receive or output data in a parallel
`fashion, so a memory bus may include as many as 64 separate wires for transferring 64 bits of data
`simultaneously, additional wires to carry address information and yet more wires to carry “control”
`information (e.g., commands). A bus designed to communicate with I/O devices, on the other
`hand, may have many fewer wires and transfer information in a serial manner.
`Below I have included a very simplified diagram of a computer system. It includes
`
`circuits such as a “Memory Controller” and an “I/O Controller”, which are designed to
`communicate with memory and I/O devices. In early computer systems, these circuits would have
`more often been implemented on one or more separate chips, and connected to the CPU via a bus
`called a “system bus”:
`
`
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2058, p. 12
`
`

`

`
`
`I have also included a very simplified diagram of a modern computer system below.
`
`Note that I have included a “Memory Controller” and an “I/O Controller” as part of the CPU. In
`modern devices these controller circuits are typically implemented on the same chip as the rest of
`the CPU:
`
`
`
`
`
`
`Note that in the figures above I have also included an “execution unit” in the CPU.
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2058, p. 13
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`

`

`As explained in more detail below, the execution unit is the portion of the CPU that responds to a
`sequence of software instructions by carrying out a sequence of logical or mathematical operations
`indicated by the instructions. The sequence of instructions is often called a “program” or “routine.”
`A reconfigurable computing system is a computer system, such as the one depicted
`
`above, but which additionally includes one or more reconfigurable computing elements, such as
`an FPGA. As explained in more detail below, an FPGA is a device that can also perform logical
`or mathematical operations on data. However, unlike a conventional CPU which performs a
`particular logical or mathematical operation in response to a particular software instruction, an
`FPGA is configured to perform one or more operations by loading configuration information into
`the device, and then performs the same operation(s), and only those operations, until reconfigured.
`Each of these conventional, prior art techniques are disclosed in the patents at issue
`
`here. Before addressing the patents specifically, I address each technique in more detail below.
`
`B.
`
`Data Processors
`
`As used in the patents at issue here, the phrase “data processor” refers to a
`
`processing element of a computer system that carries out operations on data in response to software
`instructions. E.g., Exhibit A (152 Patent), 2:30-32 (“Broadly, what is disclosed herein is a
`computer including at least one data processor for operating on user data in accordance with
`program instructions.”) The phrase is therefore synonymous with the term “central processing
`unit” or “CPU” as conventionally used.
`The software instructions are “executed” by the data processor, causing the data
`
`processor to manipulate data, often referred to as “operands,” by carrying out various types of
`logical or mathematical operations on that data. Large sequences of software instructions may
`cause the computer to perform many different tasks for the computer user, from sorting data in a
`database to performing calculations in a spreadsheet.
`A computer system that includes such a data processor has historically been
`
`referred to as a “stored program computer” because the software instructions and operands are
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2058, p. 14
`
`

`

`stored in a computer memory. The storage of instructions and operands in memory permits a user
`to easily alter the instructions that control the computing system or the data it processes, providing
`a great amount of flexibility.
`For example, a user of a “stored program computer” can easily switch between one
`
`program and another simply by causing the computer to cease executing the instructions associated
`with a first program (and perhaps writing operands back to memory for later retrieval) and begin
`executing the instructions associated with a second program (by reading instructions and operands
`out of memory and into the data processor). A real world example would be when a user of a
`conventional personal computer switches from using a web browser and opens a word processing
`program. Operands associated with the browser would be written back to memory so that they
`will be saved for later use, and the software instructions associated with the browser would be
`flushed from the data processor. New instructions and operands associated with the word
`processor would be read from memory and transferred to the data processor. The data processor
`would then be controlled by the newly loaded instructions.
` Moreover, in this type of system, programs can be easily modified by altering the
`instructions and/or operands associated with the program while they are stored in memory. Thus,
`for example, a new sequence of instructions and/or new operands may be written to the memory
`locations associated with the program, adding to the instructions and operands already there and/or
`replacing some. In this manner, new or altered functionality can be provided very easily. A real
`world example would be an update providing new security features or new bug fixes to a program.
` While a stored program computer provides flexibility to the user as to the operations
`the computer can be caused to carry out, the instructions are executed in a generally sequential
`manner. That is, software instructions are read from memory and shifted into the “execution unit”
`in a consecutive manner (e.g., Instruction No. 1 followed by Instruction No. 2, followed by
`Instructions No. 3 etc.) The program flow will often jump or branch to non-sequential instructions,
`but the system will generally begin sequential execution again at the new instruction, at least until
`another branch is reached. Such sequential operations mean that the data processor can only carry
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2058, p. 15
`
`

`

`out one task at a time, limiting the speed with which computationally intensive programs can be
`executed.
`
`Designers of modern CPUs and software programs have designed alternatives that
`
`are more complex execution units and software programs that can execute more than one stream
`of instructions at a time, and also by placing multiple “cores” (i.e., the circuitry making up a single
`data processor) on the same integrated circuit chip, but the extent of the parallelism that can be
`provided by these techniques is limited due to the complexity of designing execution units and
`software programs that can carry out a very large number of related operations at the same time.
`
`C. Memory
`
`In the context of computer systems, and specifically of the patents at issue here,
`
`memory refers to a variety of devices that are intended to store information, usually in the form of
`a sequence of digital bits, for later retrieval by another device, such as a CPU.
`Electronic memory devices come in many different forms, but perhaps the most
`
`common form is an integrated circuit chip implementing a technology called dynamic random
`access memory, or “DRAM.” The specifics of DRAM technology are not particularly important
`to the issues raised here, but their typical use in a computer system is. Several of the patents at
`issue here use conventional terms that refer to such typical uses.
`For example, the 152 and 110 Patents disclose a computer system having multiple
`
`“memory banks” in the memory subsystem, as shown in Figure 1 of those patents below:
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`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2058, p. 16
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`Exhibit A (152 Patent), Fig. 1; see also id., 3:14-16 (“The memory interconnect
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`fabric 14 is then also coupled to M memory banks comprising memory bank subsystems 16 (Bank
`0) through 16 (Bank M).”)
` Memory banks were known in the prior art to the 152 and 110 Patents. For
`example, U.S. No. 6,052,773 to DeHon (Exhibit P) describes a “memory device having a plurality
`of memory banks,” Exhibit P, Abstract, “each comprising an array of memory cells