IPR2018-01605, -01606, -01607
`(U.S. Patent No. 7,620,800)
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
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`––––––––––––––––––
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`––––––––––––––––––
`
`MICROSOFT CORPORATION,
`Petitioner,
`
`v.
`
`DIRECTSTREAM, LLC,
`Patent Owner.
`
`––––––––––––––––––
`
`Case No. IPR2018-01605, -01606, -01607
`U.S. Patent No. 7,620,800 B2
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`––––––––––––––––––
`
`REPLY DECLARATION OF DR. HAROLD STONE
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`Microsoft Corp. v. Directstream, LLC, IPR2018-01605, -01606, -01607
`Petitioner Microsoft Corp. – Ex. 1076 Cover
`
`

`

`IPR2018-01605, -01606, -01607
`(U.S. Patent No. 7,620,800)
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`1.
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`I have reviewed Patent Owner’s Response and Dr. Houman
`
`Homayoun’s supporting declaration. I have been asked to reply to certain
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`statements by Patent Owner and its expert. This is my declaration on those topics.
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`I. COMPUTATIONAL LOOPS
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`2.
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`Patent Owner and Dr. Homayoun have proposed that the definition of
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`“computational loop” should be “a set of computations that is executed repeatedly
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`per datum, either a fixed number of times or until some condition is true or false.”
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`Patent Owner Response (“Response”), 65; EX2112¶¶207, 225-226, 229-230, 233,
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`241. I disagree.
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`3.
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`In my prior declaration, I did not offer a construction for the phrase
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`“computational loop” because I believed the term should have its plain and
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`ordinary meaning and that meaning was generally well known. I have reviewed
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`the Board’s Institution Decision (Paper 21) and agree that the Board’s construction
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`of this term as “a set of computations that is executed repeatedly, either a fixed
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`number of times or until some condition is true or false” reflects that plain and
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`ordinary meaning. Institution Decision, 23. Based on my experience, this is how a
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`person of ordinary skill in the art (“a Skilled Artisan”) reading the 800 Patent
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`would understand the term in the 2002 time frame. I disagree with Patent Owner’s
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`1
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`Microsoft Corp. v. Directstream, LLC, IPR2018-01605, -01606, -01607
`Petitioner Microsoft Corp. – Ex. 1076, p. 1
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`

`

`IPR2018-01605, -01606, -01607
`(U.S. Patent No. 7,620,800)
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`and Dr. Homayoun’s proposed modification because it does not reflect that
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`understanding.
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`4.
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`For example, nothing in the words “computational loop” requires
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`repeatedly executing computations “per datum,” as the dictionary definition relied
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`on by the Board confirms. While the patent discloses loops, EX1005, FIGS. 4A-
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`4B, 6A-6G, 5:65-6:28, and 6:42-7:37, these loops do not disclose loop calculations
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`that are repeated multiple times “per datum.” Rather, what is disclosed is merely
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`the repeated execution of certain computations, i.e., a computational loop. A
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`Skilled Artisan would understand that these examples are embodiments of
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`“computational loop” as recited in the claims, and these exemplify the broadest
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`reasonable interpretation of “computational loop.”
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`5.
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`Indeed, the Patent Owner’s proposed interpretation of “computational
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`loop” is inconsistent with the disclosure of the 800 Patent. For instance, one
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`example of a “computational loop” included in the disclosure of the 800 Patent can
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`be found in the prior art paper published in 2001 by Caliga and Barker and
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`incorporated-by-reference into the 800 Patent at EX1005, 4:58-62. Patent Owner
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`cites this paper in support of its construction of “computational loop.” See
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`Response, 67. That loop is reproduced below:
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`2
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`Microsoft Corp. v. Directstream, LLC, IPR2018-01605, -01606, -01607
`Petitioner Microsoft Corp. – Ex. 1076, p. 2
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`

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`IPR2018-01605, -01606, -01607
`(U.S. Patent No. 7,620,800)
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`EX2037, 5 (annotated).
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`6.
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`Note that this figure specifically identifies the structure as a “loop
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`over filter coefficients” and implements the following calculation for index j:
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`Sum = datain(j)*R(j) + datain(j +1)*R(j+1)+Sum, j = 0,2,4,…,ncoef-1
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`3
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`Microsoft Corp. v. Directstream, LLC, IPR2018-01605, -01606, -01607
`Petitioner Microsoft Corp. – Ex. 1076, p. 3
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`

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`IPR2018-01605, -01606, -01607
`(U.S. Patent No. 7,620,800)
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`7.
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`Note that to carry out this equation, multiple iterations of the same
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`calculations must occur, albeit with different data values for “datain,” “R,” and
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`“Sum.” The values for “datain” and “R” are different for each iteration, as the
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`indices for each will be different for each iteration. The value of “Sum” will also
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`be different for each iteration, as that value is captured in a register each cycle and
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`fed back over the path that I annotated as “computational loop” to be used in the
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`next cycle for the next iteration of the calculation.
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`8.
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`The loop above – which is incorporated into the disclosure of the 800
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`Patent – therefore does not meet the Patent Owner’s claim construction for
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`“computational loop” because it is not a set of computations executed repeatedly
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`per datum a fixed number of times. Patent Owner’s interpretation therefore
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`excludes perhaps the most detailed example of a “computational loop” included in
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`its patent. I believe a Skilled Artisan would accordingly not read the claim phrase
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`“computational loop” as narrowly as Patent Owner does.
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`9.
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`Patent Owner also asserts that Splash2 (EX1007) does not satisfy the
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`claimed “computational loops” under its proposed interpretation. Response, 78-81.
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`I disagree with that conclusion as well. As I discussed in my original declaration,
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`the Unidirectional Systolic Array described in Chapter 8 of Splash2 includes
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`multiple processing elements executing computational loops simultaneously to
`4
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`Microsoft Corp. v. Directstream, LLC, IPR2018-01605, -01606, -01607
`Petitioner Microsoft Corp. – Ex. 1076, p. 4
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`

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`IPR2018-01605, -01606, -01607
`(U.S. Patent No. 7,620,800)
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`solve the edit distance calculation. See, e.g., EX1003¶¶105-06. That calculation
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`requires the comparison of two genetic sequences: a source sequence and a target
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`sequence. To perform the comparison, each processing element is initially loaded
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`with a source sequence character. EX1007, 103; EX1003¶217. The characters of
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`the target sequence are then streamed through the processing elements and
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`compared against the stored source sequence characters. EX1003¶¶220-23. In
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`each processing element during one time step, one target sequence character is
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`compared against the source sequence character stored in that processing element.
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`Id. In that same processing element during the next time step, a new target
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`sequence character is compared against that same source sequence character. Id.,
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`¶¶221-22. Thus, in each time step each processing element compares a different
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`target sequence character against its stored source sequence character.
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`10. As I also explained in my original declaration, each processing
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`element of the Unidirectional Systolic Array performs these comparisons by
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`executing the computations depicted in FIG. 8.12:
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`5
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`Microsoft Corp. v. Directstream, LLC, IPR2018-01605, -01606, -01607
`Petitioner Microsoft Corp. – Ex. 1076, p. 5
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`

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`IPR2018-01605, -01606, -01607
`(U.S. Patent No. 7,620,800)
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`EX1007, 105; EX1003¶¶146, 211. These instructions calculate the edit distance
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`between one target sequence character and the stored source sequence character in
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`the particular processing element. EX1003¶146.
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`11. Accordingly, because each processing element in the Unidirectional
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`Array executes its loop instructions multiple times for the same source character,
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`it executes the loop repeatedly per datum, as Patent Owner argues is required by
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`the claims.
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`6
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`Microsoft Corp. v. Directstream, LLC, IPR2018-01605, -01606, -01607
`Petitioner Microsoft Corp. – Ex. 1076, p. 6
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`

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`IPR2018-01605, -01606, -01607
`(U.S. Patent No. 7,620,800)
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`12. Moreover, in both the Unidirectional and Bidirectional Systolic
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`Arrays disclosed in Splash2, each processing element executes its disclosed
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`computational loop instructions “a fixed number of times or until some condition is
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`true or false.” For example, Splash2 states that both systolic arrays described in
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`Chapter 8 “exploit the locality of reference by computing the entries along each
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`antidiagonal in parallel, as shown in Figure 8.4. … Each processing element (PE)
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`computes the distances along a particular diagonal matrix. A block diagram of the
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`PE and a listing of the algorithm it executes are shown in Figures 8.6 and 8.7,
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`respectively.” EX1007, 100. A Skilled Artisan would have understood from this
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`disclosure that each processing element executes its loop instructions until it
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`“computes the distances along a particular diagonal of the distance matrix.” See
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`EX1003¶¶225-26, 237-38.
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`13.
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`Splash2 also discloses that the sequences being compared in each
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`array are of length “m” and “n,” respectively. EX1007, 103-04. A Skilled Artisan
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`would therefore understand that each processing element carries out execution of
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`its loop instructions until those indices (“m” and “n”) are reached, as I explained
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`during my deposition. EX2063, 225:19-226:5 (“So that one of skill in the art
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`would stop this when those indices are reached.”) Indeed, Patent Owner makes
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`this same point in its response. See Response, 79 (“This is confirmed by Petitioner
`7
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`Microsoft Corp. v. Directstream, LLC, IPR2018-01605, -01606, -01607
`Petitioner Microsoft Corp. – Ex. 1076, p. 7
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`

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`IPR2018-01605, -01606, -01607
`(U.S. Patent No. 7,620,800)
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`and its expert that the ‘loop-endloop’ repeats until the amount of data
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`concludes.”)(Emphasis in original.)
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`14.
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`In other words, the Unidirectional Systolic Array of Splash2 performs
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`“a set of computations [as set forth in FIG. 8.12] that is executed repeatedly [once
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`for each target sequence character streamed through the array] per datum [per
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`source sequence character], either a fixed number of times or until some
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`condition is true or false [until the last target sequence character is compared
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`against the last source sequence character].”
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`II. LOOPING ON SPLASH2
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`15.
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`Patent Owner and its expert also assert that the Splash 2 system
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`implemented loops on an attached CPU rather than in the FPGAs of the system,
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`relying solely on a paper by Gokhale and Minnich, entitled “FPGA Computing In
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`A Data Parallel C.” Response 83; EX2112¶209. I disagree.
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`16.
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`The paper by Gokhale and Minnich does not relate to the edit distance
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`calculations described in Chapter 8 of Splash2, which formed the basis of the
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`opinions in my original declaration. Rather, the Gokhale and Minnich paper
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`describes a technique for automatically synthesizing digital logic on the Splash 2
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`system for programs written in a language called Data-parallel Bit-serial C, or
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`“dbC,” for an SIMD (single-instruction multiple data) implementation. See
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`8
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`Microsoft Corp. v. Directstream, LLC, IPR2018-01605, -01606, -01607
`Petitioner Microsoft Corp. – Ex. 1076, p. 8
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`

`

`IPR2018-01605, -01606, -01607
`(U.S. Patent No. 7,620,800)
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`Gokhale, Maya, and Ron Minnich. "FPGA computing in a data parallel C." [1993]
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`Proceedings IEEE Workshop on FPGAs for Custom Computing Machines. IEEE,
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`1993 (EX1074), 94.
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`17.
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`I note that Splash2 discloses that the systolic arrays described in
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`Chapter 8 and used to calculate edit distance were programmed in VHDL, not dbC.
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`EX1007, 106. And a Skilled Artisan would understand that the systolic array
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`structure of the edit distance implementations is not an SIMD structure. So
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`whether or not the system described by Gokhale and Minnich implemented loops
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`on the Splash 2 CPU, that paper has nothing to do with the systolic arrays
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`described in Chapter 8 of Splash2.
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`18.
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`Indeed, as I explained in my original declaration, the computational
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`loops of the systolic arrays of Splash2 are implemented in the FPGAs of the Splash
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`2 system. EX1003¶¶208, 217-38. Splash2 expressly states that “[b]oth the
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`bidirectional and unidirectional systolic arrays have been implemented on the
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`Splash 2 programmable logic array, with versions for DNA and protein
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`sequences.” EX1007, 104 (emphasis added).
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`19.
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`Splash2 also states that for the bidirectional systolic array, “[e]ach
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`processing element (PE) computes the distances along a particular diagonal of the
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`distance matrix. A block diagram of the PE and a listing of the algorithm it
`9
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`Microsoft Corp. v. Directstream, LLC, IPR2018-01605, -01606, -01607
`Petitioner Microsoft Corp. – Ex. 1076, p. 9
`
`

`

`IPR2018-01605, -01606, -01607
`(U.S. Patent No. 7,620,800)
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`executes are shown in Figures 8.6 and 8.7, respectively.” EX1007, 100. Figure
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`8.7 depicts the loop instructions for that array. See id., 101. Similarly, for the
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`unidirectional array, Splash2 states “[t]he algorithm executed by each PE in the
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`unidirectional array is listed in Figure 8.12.” Id., 104. Figure 8.12 depicts the loop
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`instructions for the unidirectional array. See id., 105. Thus, Splash2 discloses that
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`it is the processing elements, or “PEs,” of the arrays that execute the looping
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`instructions. The book further states, however, that “[f]or the DNA version of the
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`bidirectional array, each of the 16 array FPGAs (Xl to X16) contains 24 PEs,”
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`and “[i]n the DNA version of the unidirectional array, each of the 16 array FPGAs
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`(Xl to Xl6) holds 14 PEs.” Id., 107 (emphasis added). Thus, Splash2 expressly
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`states that the processing elements that implement the loop instructions for both
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`systolic arrays are implemented in the FPGAs of the Splash2 system.
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`III. RAPID
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`20.
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`Patent Owner and its expert also assert RaPiD (EX1009) does not
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`disclose a computational loop, but instead discloses “a bypass or forwarding path.”
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`Response, 89-90; EX2112¶¶235-40. I disagree.
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`21. As I explained in my original declaration, RaPiD discloses an
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`implementation of the Discrete Cosine Transform (DCT) on a systolic array of a
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`reconfigurable computing system. EX1003¶303; EX1009, 5-7. It implements a 2-
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`10
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`Microsoft Corp. v. Directstream, LLC, IPR2018-01605, -01606, -01607
`Petitioner Microsoft Corp. – Ex. 1076, p. 10
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`

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`IPR2018-01605, -01606, -01607
`(U.S. Patent No. 7,620,800)
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`D DCT operation as “two sequential 1-D DCTs,” EX1009, 5, which it explains can
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`be implemented using the following two “dot product” equations:
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`EX1003¶307. As I have explained, each of these equations calculates the
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`dot product of a row of the first matrix (a in Eq. 5 and z in Eq. 6) and a column of
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`the second matrix w (in both, though with difference indices). EX1003¶321.
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`22. As I have also explained in my original declaration at ¶¶321-29, such
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`calculations require multiple iterations, each iteration including
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`(i) a multiplication of one element from a row of the first matrix (a or
`z) with a corresponding element from a column of the second matrix
`(w), and
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`(ii) the addition of the product of that multiplication to the running
`sum of such products calculated during the previous iterations.
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`11
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`Microsoft Corp. v. Directstream, LLC, IPR2018-01605, -01606, -01607
`Petitioner Microsoft Corp. – Ex. 1076, p. 11
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`

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`IPR2018-01605, -01606, -01607
`(U.S. Patent No. 7,620,800)
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`Thus, the equations set forth above calculate a running sum, with the intermediate
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`sum output by each iteration fed back as an input to the next iteration of
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`calculations.
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`23.
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`To implement the 2-D DCT, RaPiD discloses the following hardware
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`of Figure 10 corresponding to a cell:
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`EX1009, 111.1
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`1 I note that a Skilled Artisan would have understood that the term “netlist” as used
`in Figure 10 to refer to the fact that the figure shows the electrical connectivity of
`the circuit realized in the RaPiD cell.
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`12
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`Microsoft Corp. v. Directstream, LLC, IPR2018-01605, -01606, -01607
`Petitioner Microsoft Corp. – Ex. 1076, p. 12
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`

`

`IPR2018-01605, -01606, -01607
`(U.S. Patent No. 7,620,800)
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`24.
`
`To illustrate how the calculations set forth above are carried out
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`repeatedly, I highlighted in an annotated version of Figure 10 in ¶327 of my
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`original declaration the location in the hardware where the output of the ALU (i.e.,
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`the running sum) is looped back to the ALU input for use in the next iteration of
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`the loop:
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`25.
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`Patent Owner and its expert assert that the data path I highlighted in
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`Figure 10 above does not illustrate a computational loop, but rather is “a structure
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`called a bypass or forwarding path.” Response, 89. I disagree. As explained
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`above, the data path highlighted in Figure 10 loops the intermediate, or running,
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`sum from the output of the ALU to its input so that it may be used in the next
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`iteration of the DCT calculation. The path therefore represents the location in the
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`13
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`Microsoft Corp. v. Directstream, LLC, IPR2018-01605, -01606, -01607
`Petitioner Microsoft Corp. – Ex. 1076, p. 13
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`

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`IPR2018-01605, -01606, -01607
`(U.S. Patent No. 7,620,800)
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`hardware of RaPiD where the running sum is fed back to an ALU input, so that it
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`may be used in the next iteration of the computational loop.2
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`26.
`
`That the disclosure of RaPiD constitutes a “computational loop” for
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`purposes of the 800 Patent is beyond argument. Compare, for example, the loop of
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`RaPiD to the computational loop incorporated-by-reference into the 800 Patent via
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`EX2037 and discussed above. Both the RaPiD loop and the loop disclosed in
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`EX2037 accumulate a running, or intermediate, sum by feeding back a value of the
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`2 I also note that the Patent Owner and its expert assert that a “bypass” is not a
`“computational loop,” Response, 89-90, EX2112¶¶235-40, but do not provide
`support for that contention. The expert does cite to an earlier declaration that
`includes a Figure 4.56 the expert characterizes as including a “forwarding
`path.” Specifically, he identifies the “blue” portion of that figure as representing
`the forwarding path. See EX2029, ¶45, citing a figure from EX2043 at page 311
`(p. 334, using the exhibit page numbers). The blue portion of that figure, however,
`does not include the same loop structure that I have identified in RaPiD as a
`“computational loop.” In particular, the structure of RaPiD Figure 10 that I have
`highlighted feeds back the intermediate sum output by the ALU to the input of the
`ALU so that it can be used in the next iteration of the calculations. The blue
`portion of Figure 4.56 communicates control information through various stages to
`a “Forwarding Unit,” and then to the control inputs of two MUXes. EX2043 at
`311. Thus, the blue path of Figure 4.56 does not loop back the output of any
`structure to the input of that structure so that it can be used in the next iteration of
`calculations. RaPiD thus discloses something different from the forwarding path
`cited by Patent Owner’s expert. It discloses a “computational loop.”
`
`14
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`Microsoft Corp. v. Directstream, LLC, IPR2018-01605, -01606, -01607
`Petitioner Microsoft Corp. – Ex. 1076, p. 14
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`

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`IPR2018-01605, -01606, -01607
`(U.S. Patent No. 7,620,800)
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`sum obtained in the previous step to be used in the next step. A Skilled Artisan
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`would therefore understand that the loop structure disclosed in RaPiD is analogous
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`to the structure identified as a “loop” in the 800 Patent through the incorporated-
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`by-reference paper EX2037.
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`27.
`
`Finally, I note that during my deposition I agreed that Figure 10
`
`depicts a bypass, but I was not asked and did not specify where in the Figure that
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`bypass is located. EX2063, 201:21-202:1. In particular, my testimony indicating
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`that there is a bypass in Figure 10 referred to the bottom wire of Figure 10 labeled
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`“Column 1-D DCT results flows out,” which either bypasses the cell or is
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`terminated at the multiplexor while the cell’s DCT results are passed instead to the
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`next cell. That bottom wire – and not the feedback path of Figure 10 I highlighted
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`in my original declaration at ¶327 -- is the bypass I was referring to in my
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`testimony, which I would have stated had I been asked.
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`Dated: November 26, 2019
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`Respectfully Submitted,
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`(cid:3)(cid:5)(cid:4)(cid:2)(cid:7) (cid:1)(cid:6)(cid:7)
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`15
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`Microsoft Corp. v. Directstream, LLC, IPR2018-01605, -01606, -01607
`Petitioner Microsoft Corp. – Ex. 1076, p. 15
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`