Petition for Inter Partes Review of U.S. Patent No. 7,620,800
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`Paper No. 1
`
`MICROSOFT CORPORATION.
`
`Petitioner,
`
`v.
`
`SAINT REGIS MOHAWK TRIBE,
`
`Patent Owner
`
`Patent No. 7,620,800
`
`Issued: November 17, 2009
`
`Filed: April 9, 2007
`
`Inventors: Jon M. Huppenthal, David E. Caliga
`
`Title:
`
`MULTI-ADAPTIVE PROCESSING SYSTEMS AND
`TECHNIQUES FOR ENHANCING PARALLELISM AND
`PERFORMANCE OF COMPUTATIONAL FUNCTIONS
`
`____________________
`
`Inter Partes Review No. IPR2018-01605
`
`PETITION FOR INTER PARTES REVIEW OF U.S. PATENT NO. 7,620,800
`UNDER 35 U.S.C. §§ 311-319 AND 37 C.F.R. § 42.1-.80 & 42.100-.123
`________________________
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`

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`Petition for Inter Partes Review of U.S. Patent No. 7,620,800
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`TABLE OF CONTENTS
`
`I.
`
`II.
`
`INTRODUCTION ........................................................................................... 1
`
`COMPLIANCE WITH REQUIREMENTS FOR INTER PARTES
`REVIEW .......................................................................................................... 2
`
`A.
`
`B.
`
`Certification the 800 Patent May Be Contested by Petitioner .............. 2
`
`Fee for Inter Partes Review (§ 42.15(a)) ............................................... 3
`
`C. Mandatory Notices (37 CFR § 42.8(b)) ................................................ 3
`
`D.
`
`Proof of Service (§§ 42.6(e) and 42.105(a)) ......................................... 5
`
`III.
`
`IDENTIFICATION OF CHALLENGED CLAIMS ....................................... 5
`
`IV. RELEVANT INFORMATION CONCERNING THE CONTESTED
`PATENT .......................................................................................................... 6
`
`A.
`
`B.
`
`C.
`
`D.
`
`E.
`
`Effective Filing Date ............................................................................. 6
`
`Level of Ordinary Skill ......................................................................... 6
`
`Overview of 800 Patent ......................................................................... 7
`
`Prosecution History of 800 Patent ......................................................... 9
`
`Claim Construction.............................................................................. 10
`
`1.
`
`2.
`
`3.
`
`4.
`
`5.
`
`6.
`
`“functional unit” ........................................................................ 10
`
`“data driven” ............................................................................. 11
`
`“transforming an algorithm into a data driven calculation” ..... 11
`
`“form” ....................................................................................... 12
`
`“clusters of functional units” .................................................... 14
`
`“data dimension” ....................................................................... 15
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`Petition for Inter Partes Review of U.S. Patent No. 7,620,800
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`7.
`
`8.
`
`9.
`
`“seamlessly” .............................................................................. 15
`
`“data mining” ............................................................................ 16
`
`“stream communication” .......................................................... 17
`
`V.
`
`OVERVIEW OF SPLASH 2 ......................................................................... 19
`
`A.
`
`General Architecture of Splash 2 .............................................. 19
`
`A.
`
`Systolic Algorithms For Searching Genetic Databases ...................... 21
`
`VI.
`
`PRECISE REASONS FOR REQUESTED RELIEF .................................... 28
`
`A.
`
`Claim 1 is Anticipated by Splash2 ...................................................... 28
`
`1.
`
`Claim 1 is Anticipated .............................................................. 28
`
`B.
`
`Claim 1 is Obvious over Splash2 ........................................................ 46
`
`1.
`
`2.
`
`3.
`
`4.
`
`5.
`
`Considering the Chapters of Splash2 Together ........................ 46
`
`Transforming an Algorithm into a Calculation ........................ 48
`
`Forming ..................................................................................... 50
`
`First Wherein Clause ................................................................. 50
`
`Second Wherein Clause ............................................................ 52
`
`C.
`
`D.
`
`E.
`
`Claim 1 is Obvious over Splash2 in view of Gaudiot ......................... 53
`
`Claims 8 and 9 Are Obvious under Splash2 in view of RaPiD, With or
`Without Gaudiot .................................................................................. 56
`
`Claim 20 is Obvious over Splash2 in view of Jeong, With or Without
`Gaudiot ................................................................................................ 70
`
`VII. CONCLUSION .............................................................................................. 81
`
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`Petition for Inter Partes Review of U.S. Patent No. 7,620,800
`
`I.
`
`INTRODUCTION
`
`U.S. Patent No. 7,620,800 (“the 800 Patent”) describes a multiprocessor
`
`computer system for performing systolic, data driven processing on reconfigurable
`
`computing elements, such as FPGAs. The application from which it issued was
`
`filed in 2007.
`
`Systolic data driven processing on multiprocessor systems employing
`
`FPGAs was well known by that time. The principal reference relied on here is a
`
`1996 book describing what is likely the most successful example of such a system,
`
`the Splash 2 computer. See EX1007. Splash 2 was used by numerous scientists
`
`and engineers to carry out various types of processing, including numerous systolic
`
`applications. As demonstrated below, the Splash 2 book discloses details of the
`
`Splash 2 system and of certain processing carried out on that system for the
`
`comparison of genetic sequences that together satisfy each and every element of
`
`numerous claims of the 800 Patent.
`
`One would think that such a seminal prior art reference would have been
`
`provided to the examiner of the 800 Patent, if the applicants had been aware of it.
`
`In fact, they were aware of the book, but provided only a small excerpt to the
`
`examiner. The face of the 800 Patent and its prosecution history demonstrate that
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`Petition for Inter Partes Review of U.S. Patent No. 7,620,800
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`the applicants disclosed only pages 1-11 of the Splash 2 book and a four-page
`
`summary article about Splash 2 and some of its programming, neither of which the
`
`examiner relied on. EX1005, Face; EX1006, 49. Those pages of the book
`
`describe only the background context of custom computing machines and a brief
`
`introduction to Splash 2, EX1007, 1-11, and the article has only a terse few
`
`paragraphs about the programming done on the system, EX1060. A fuller
`
`description of the system architecture and programming of Splash 2 begins on
`
`page 12 of the book, and continues for the next 188 pages, including an entire
`
`chapter – Chapter 8, relied on here – on systolic processing on the Splash 2
`
`computer. EX1007, 12-200.
`
`As demonstrated below, the materials the applicants withheld from the
`
`examiner disclose each and every limitation of numerous claims of the 800 Patent,
`
`and, either alone or in combination with other materials, render all claims
`
`challenged by this Petition unpatentable. Petitioner therefore respectfully requests
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`the challenged claims be cancelled, for the reasons set forth herein.
`
`II.
`
`COMPLIANCE WITH REQUIREMENTS FOR INTER PARTES
`
`REVIEW
`
`A.
`
`Certification the 800 Patent May Be Contested by Petitioner
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`Petition for Inter Partes Review of U.S. Patent No. 7,620,800
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`Petitioner certifies it is not barred or estopped from requesting inter partes
`
`review of U.S. Patent No. 7,620,800 (“the 800 Patent”) (EX1005). Neither
`
`Petitioner, nor any party in privity with Petitioner, has filed a civil action
`
`challenging the validity of any claim of the 800 Patent. The 800 Patent has not
`
`been the subject of a prior inter partes review by Petitioner or a privy of Petitioner.
`
`Petitioner also certifies this petition for inter partes review is filed within one year
`
`of the date of service of a complaint alleging infringement of a patent. Petitioner
`
`therefore certifies this patent is available for inter partes review.
`
`B.
`
`Fee for Inter Partes Review (§ 42.15(a))
`
`The Director is authorized to charge the fee specified by 37 CFR § 42.15(a)
`
`to Deposit Account No. 50-1597.
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`C. Mandatory Notices (37 CFR § 42.8(b))
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`The real party of interest of this petition is Microsoft Corporation.
`
`(“Microsoft”) located at One Microsoft Way, Redmond, WA 98052. Lead counsel
`
`and backup lead counsel are as follows:
`
`Lead Counsel
`Joseph A. Micallef
`jmicallef@sidley.com
`Reg. No. 39,772
`(202) 736-8492
`
`Backup Lead Counsel
`
`Scott M. Border
`sborder@sidley.com
`(pro hac vice to be requested)
`(202) 736-8188
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`Petition for Inter Partes Review of U.S. Patent No. 7,620,800
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`Jason Greenhut
`jgreenhut@sidley.com
`Reg. No. 71,657
`(312) 853-2144
`
`Service on Petitioner may be made by e-mail (sidleysrclabsipr@sidley.com),
`
`mail or hand delivery to: Sidley Austin LLP, 1501 K Street, N.W., Washington,
`
`D.C. 20005. The fax number for lead and backup counsel is (202) 736-8711.
`
`The 800 Patent is or has been the subject to, or relates to, the following
`
`proceedings:
`
` SRC Labs, LLC et al v. Microsoft Corporation, WAWD-2-18-cv-
`
`00321
`
` SRC Labs, LLC et al v. Amazon Web Services, Inc et al, WAWD-2-
`
`18-cv-00317
`
` SRC Labs, LLC et al v. Microsoft Corporation, VAED-1-17-cv-01172
`
` SRC Labs, LLC et al v. Amazon Web Services, Inc. et al, VAED-1-17-
`
`cv-01227
`
` SRC Labs, LLC et al v. Amazon Web Services, Inc. et al, VAED-2-17-
`cv-00547
`
` Microsoft Corporation v. Saint Regis Mohawk Tribe, IPR2018-01601
`
` Microsoft Corporation v. Saint Regis Mohawk Tribe, IPR2018-01602
`
` Microsoft Corporation v. Saint Regis Mohawk Tribe, IPR2018-01603
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`4
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`Petition for Inter Partes Review of U.S. Patent No. 7,620,800
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` Microsoft Corporation v. Saint Regis Mohawk Tribe, IPR2018-01606
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` Microsoft Corporation v. Saint Regis Mohawk Tribe, IPR2018-01607
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`D.
`
`Proof of Service (§§ 42.6(e) and 42.105(a))
`
`Proof of service of this petition is provided in Attachment A.
`
`III.
`
`IDENTIFICATION OF CHALLENGED CLAIMS
`
`Claims 1, 8, 9, and 20 of the 800 Patent are unpatentable over the prior art as
`
`follows:
`
`(i)
`
`(ii)
`
`Claim 1 is anticipated by Splash2 (EX1007).
`
`Claim 1 is obvious over Splash2.
`
`(iii) Claim 1 is obvious over Splash2 in view of Gaudiot (EX1010).
`
`(iv) Claims 8 and 9 are obvious over Splash2 in view of RaPiD (EX1009),
`
`with or without Gaudiot.
`
`(v)
`
`Claim 20 is obvious over Splash2 in view of Jeong (EX1061), with or
`
`without Gaudiot.
`
`Petitioner’s proposed construction of the contested claims, the evidence
`
`relied upon, and the precise reasons why the claims are unpatentable are provided
`
`in §§IV-VI, below. The evidence relied upon in this petition is listed in
`
`Attachment B.
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`Petition for Inter Partes Review of U.S. Patent No. 7,620,800
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`IV. RELEVANT INFORMATION CONCERNING THE CONTESTED
`
`PATENT
`
`A.
`
`Effective Filing Date
`
`Patent Owner has claimed a priority date of October 31, 2002 for the 800
`
`Patent. EX1013, 3. We assume that date in the analysis below.
`
`B.
`
`Level of Ordinary Skill
`
`A person of ordinary skill in the art in the field of the 800 Patent in the 2002
`
`time frame (“a Skilled Artisan”) would have had an advanced degree in electrical
`
`or computer engineering, or computer science with substantial study in computer
`
`architecture, hardware design, and computer algorithms, and at least three years’
`
`experience working in the field. Alternatively, that person would have had a
`
`bachelor’s degree covering those disciplines and at least four years working the
`
`field. Such a person would have been knowledgeable about the programming,
`
`design and operation of computer systems based on reconfigurable components
`
`such as FPGAs (field programmable gate arrays) and CPLDs (complex
`
`programmable logic devices), including computer systems for performing systolic
`
`and data driven calculations. That person would also have been familiar with
`
`hardware description languages such as VHDL that could be used to configure
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`Petition for Inter Partes Review of U.S. Patent No. 7,620,800
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`FPGAs and CPLDs that serve as components of reconfigurable computer systems.
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`Finally, such a person would also have been familiar with various other areas of
`
`technology that by 2002 had relied on high performance and parallel computing
`
`systems. EX1003¶45.
`
`C. Overview of 800 Patent
`
`The 800 Patent claims a method of using a reconfigurable computing system
`
`to process a “data driven” calculation during which different data dimensions of a
`
`calculation are simultaneously processed by “lines of code” formed as clusters of
`
`functional units. Id., 12:45-13:8; EX1003¶46.
`
`The 800 Patent states that multiprocessor systems using parallel processing
`
`were known, EX1005, 1:44-52, but that “as more and more performance is
`
`required, so is more parallelism, resulting in ever larger systems. Clusters exist
`
`today that have tens of thousands of processors and can occupy football fields of
`
`space. Systems of such a large physical size present many obvious downsides,
`
`including, among other factors, facility requirements, power, heat generation and
`
`reliability.” Id., 1:55-61; EX1003¶47. The patent states that the solution to this
`
`supposed problem is that “a processor technology could be employed that offers
`
`orders of magnitude more parallelism per processor,” EX1005, 1:65-67, and such a
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`technology exists in the form of “a reconfigurable processor.” Id., 2: 2;
`
`EX1003¶48.
`
`The patent depicts such a technology in Figure 2 (below), showing an
`
`adaptive processor 200 that includes “an adaptive processor chip 202 [that]
`
`incorporates a large number of functional units (‘FU’) 204 interconnected by
`
`reconfigurable routing resources.” EX1005, 5:34-38; EX1003¶49.
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`Petition for Inter Partes Review of U.S. Patent No. 7,620,800
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`The 800 Patent states that the conventional approach to implementing nested
`
`loops in “a conventional sequential processing operation” is problematic because
`
`“all of the logic that has been instantiated is not being completely utilized.”
`
`EX1005, 5:65-6:10. It states that the solution to this problem “is to have an
`
`application evaluate a problem in a data flow sense. That is, it will ‘pass’ a
`
`subsequent dimension of a given problem through the first loop 412 of logic
`
`concurrently with the previous dimension of data being processed through the
`
`second loop 414.” Id., 6:21-26. The patent further states that “a ‘dimension’ of
`
`data can be: multiple vectors of a problem, multiple planes of a problem, multiple
`
`time steps in a problem and so forth.” Id., 6:25-28; EX1003¶50.
`
`D.
`
`Prosecution History of 800 Patent
`
`The original claims of the 800 Patent application were directed to “a method
`
`for data processing in a reconfigurable computing system” that operates on
`
`different “data dimensions” of a “calculation” using “at least two functional units.”
`
`EX1006, 30. The claims were rejected as obvious over the 324 Patent in view of
`
`Gaudiot. EX1006, 140. The applicant filed a terminal disclaimer in response that
`
`disclaimed any patent term beyond that of the 324 Patent. Id., 150. The claims as
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`Petition for Inter Partes Review of U.S. Patent No. 7,620,800
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`originally filed (with a minor change to claim 30 to correct a rejection for lack of
`
`antecedent basis) were subsequently allowed on June 30, 2009. Id., 165-67.
`
`E.
`
`Claim Construction
`
`Petitioner proposes the constructions of several claim terms set forth below
`
`based on the ordinary meaning to a Skilled Artisan in the context of the patent.
`
`These constructions are within the broadest reasonable interpretation, and are
`
`applied in the analysis below. If Patent Owner contends claim terms should be
`
`read to have a special meaning, those contentions should be disregarded unless
`
`Patent Owner also amends the claims compliant with 35 U.S.C. §112 to make them
`
`expressly correspond to those contentions.
`
`1.
`
`“functional unit”
`
`The phrase “functional unit” should be construed to mean a computational
`
`unit configured to perform a specific task.
`
`The 800 Patent indicates that “functional units” are entities found in both
`
`conventional CPUs and in reconfigurable processors, EX1005, 5:16-28, and
`
`indicates that functional units are dedicated to certain processing tasks, id., 2:2-7;
`
`5:38-50; EX1003¶56. US 6,434,687, incorporated by reference into the 800
`
`Patent, id., 1:14-22, also discloses a processing element (MAP element 112)
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`Petition for Inter Partes Review of U.S. Patent No. 7,620,800
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`characterized as comprising an FPGA used as a “reconfigurable functional unit.”
`
`EX1014, 687 Patent, 5:14-16; EX1003¶57. The phrase “a computational unit
`
`configured to perform a specific task” captures the essence of these disclosures.
`
`EX1003¶58; see also EX1059, 540; EX1003¶59.
`
`2.
`
`“data driven”
`
`In the context of the 800 Patent, the ordinary meaning to a Skilled Artisan of
`
`“data driven” is the scheduling of operations upon the availability of their
`
`operands. See EX1010 at 1220. The specification of the 800 Patent offers no
`
`further explanation of “data driven,” although the term appears in one title among
`
`the citation titles in the front matter of the patent. See EX1034. EX1034 defines
`
`“data driven” to be “that the operation is evaluated when the required operands are
`
`available.” EX1034, 141; EX1003¶60. A Skilled Artisan would understand that
`
`definition to reflect the ordinary meaning of the phrase. Id.
`
`3.
`
`“transforming an algorithm into a data driven calculation”
`
`The phrase “transforming an algorithm into a data driven calculation”
`
`should be construed to mean compiling an algorithm into configuration code
`
`representing computations that process data in a data driven fashion.
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`Petition for Inter Partes Review of U.S. Patent No. 7,620,800
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`The 800 Patent does not use any form of the word “transform” outside the
`
`claims. However, application US 09/755,744, EX1022, incorporated by reference
`
`into the 800 Patent (see EX1005, 1:9-22), relates the process of “transforming an
`
`algorithm” for a reconfigurable computer to a parallelizer that automatically
`
`generates the code to be run on a reconfigurable element. EX1022, 0025. A person
`
`of ordinary skill in the art would have understood that to be a process of compiling
`
`an algorithm into configuration code for a reconfigurable processor. EX1003¶62.
`
`The Skilled Artisan would also have understood the ordinary English
`
`meaning of “a data driven calculation” to be that the transformation produces code
`
`representing computations that process data in a data driven fashion. EX1003¶63.
`
`The Skilled Artisan would therefore have understood “transforming an algorithm
`
`into a data driven calculation” to be “compiling an algorithm into configuration
`
`code representing computations that process data in a data driven fashion.”
`
`EX1017, 84; EX1003¶63-64.
`
`4.
`
`“form”
`
`In the context of the 800 Patent, the ordinary meaning to a Skilled Artisan of
`
`“form” is create, such as by configuring, a particular structure. EX1003, ¶65.
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`Petition for Inter Partes Review of U.S. Patent No. 7,620,800
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`The term “form” is not used in the Specification of the 800 Patent, other than
`
`in the claims. In view of the Specification as a whole, a Skilled Artisan would
`
`have understood the term “form” as used in the claims to be directed to the same
`
`functionality as the term “instantiate” as used in the claims of the 324 Patent, the
`
`parent of the 800 Patent. EX1001, Claims. For example, the 800 Patent discloses
`
`instantiating only those functional units needed to solve a particular problem,
`
`EX1005, 2:2-4, and instantiating at least two functional units, id., 2:52-55.
`
`Similarly, claim 1 of the 800 Patent claims “forming” only those functional units
`
`needed to solve a particular problem, EX1005, 12:55-56, and “forming” at least
`
`two functional units, id., 12:53-54. A Skilled Artisan would reasonably conclude
`
`those disclosures are corresponding to those claimed behaviors. Because both of
`
`these patents are based on the same specification and directed to the same
`
`invention, and that common specification makes no distinction between
`
`“instantiate” and “form,” a Skilled Artisan would reasonably conclude that the two
`
`claim words are intended to be directed to the same functionality. EX1003, ¶66.
`
`Further, the Patent Owner seems to have replaced the word “instantiate” in,
`
`for example, claim 1 of the 324 Patent with the word “form” in claim 1 of the 800
`
`Patent. Compare EX1001, 12:55-13:19; EX1005, 12:45-13:8. Indeed, claim 15 of
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`Petition for Inter Partes Review of U.S. Patent No. 7,620,800
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`the 800 Patent, which depends from claim 1, still includes the word “instantiating,”
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`even though that verb does not appear in claim 1, which suggests that the Patent
`
`Owner was simply swapping the word “forming” in for the word “instantiating”
`
`and missed claim 15. The prosecution history thus also indicates that “forming” is
`
`directed to the same functionality as the word “instantiating.” EX1003, ¶67.
`
`In response to an Examiner’s request for a definition of “instantiate” during
`
`the processing of the 324 Patent, the patentee responded: “A reconfigurable
`
`processor is essentially a blank processor that must be configured (instantiated) to
`
`conduct a particular task. To instantiate means to create such an instance or
`
`configuration by, for example, defining one particular variation of the processor's
`
`structure.” EX1002, 216; EX1003, ¶68. A Skilled Artisan would therefore have
`
`understood the applicant’s reply to have defined the term “instantiate” to mean
`
`“create, such as by configuring, a particular structure” because it parenthetically
`
`equates “instantiation” with configuration. EX1003¶69.
`
`The construction applied here is consistent with the Patent Owner’s
`
`interpretation of the same term in District Court. EX1069, 31. The Board should
`
`therefore apply this interpretation.
`
`5.
`
`“clusters of functional units”
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`Petition for Inter Partes Review of U.S. Patent No. 7,620,800
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`The term “clusters of functional units” should be construed to mean groups
`
`of functional units.
`
`The 800 Patent specification uses the word “cluster” to refer generically to a
`
`group. EX1005, 1:53-58. One of ordinary skill in the art would also have
`
`understood the ordinary English meaning of “cluster” to be “group.” EX1023;
`
`EX1003¶¶71-72.
`
`6.
`
` “data dimension”
`
`The term “data dimension” should be construed to mean multiple vectors of
`
`a problem, multiple planes of a problem, multiple time steps in a problem and so
`
`forth. The 800 Patent defines this claim term in this manner. EX1005, 6:25-26 (“In
`
`practice, a ‘dimension’ of data can be: multiple vectors of a problem, multiple
`
`planes of a problem, multiple time steps in a problem and so forth.”); EX1003¶74.
`
`7.
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`“seamlessly”
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`The term “pass computed data seamlessly between said computational
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`loops” should be construed to mean to communicate computed data directly
`
`between functional units that are calculating computational loops.
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`The term “seamlessly” is not used in the Specification of the 800 Patent,
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`other than in the claims. During prosecution of the parent 324 Patent, the patentees
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`Petition for Inter Partes Review of U.S. Patent No. 7,620,800
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`identified “seamlessly” with the passing of data directly (“passed as input data”)
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`from one compute loop of a systolic array to a neighboring loop of the array. See
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`EX1002, 226; EX1003¶76. A Skilled Artisan would have understood the term
`
`“flow seamlessly” as used in the quote from the file history of the 324 Patent to
`
`mean that data is communicated directly between functional units. In view of the
`
`Specification as a whole, a Skilled Artisan would have also understood the term
`
`“flow seamlessly” to mean that data is communicated directly between functional
`
`units in the Claims of the 800 Patent. EX1003¶77.
`
`8.
`
`“data mining”
`
`The term “data mining” should be construed to mean the process of
`
`discovering useful and previously unknown information in large databases.
`
`EX1003¶78.
`
`The specification of the 800 Patent discusses “data mining” in only a single
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`passage, and does not define it. EX1005, 11:6-18; EX1003¶79. In that passage,
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`the 800 Patent discloses the use of statistics (correlation) to search through a
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`database as a characteristic of the data mining applications to which the patent is
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`directed. EX1003¶80. Obviously, the information sought is unknown, or the
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`search would not be useful.
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`This description is consistent with other definitions of the term “data
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`mining,” including “the process of collecting, searching through, and analyzing a
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`large amount of data in a database, as to discover patterns or relationships,”
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`EX1026, and “the practice of searching through large amounts of computerized
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`data to find useful patterns or trends,” EX1027. See EX1024, 1; EX1025, 132;
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`EX1026; EX1003¶¶81-83. Each is directed to essentially the same concept. A
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`Skilled Artisan would therefore have understood “data mining” to mean the
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`process of discovering useful and previously unknown information in large
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`databases. EX1003¶84.
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`9.
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` “stream communication”
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`The term “stream communication” is not used in the 800 Patent except in its
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`claims, nor is it used in the incorporated references. However, the notion of
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`“stream of operands” is used in the incorporated reference US 6,434,687 to
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`Huppenthal at 9:12-14 (EX1014). A Skilled Artisan would understand this use of
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`“stream” to mean “sequence,” and therefore would understand “stream
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`communication” to mean “communication of a data sequence.” This is consistent
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`with the use of “stream of operands” in EX1014. It is also consistent with the
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`discussion of communication of data sequentially in a systolic wall of data with
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`respect to Fig. 7C, reproduced below.
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`With reference additionally now to FIG. 7C, the creation of a
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`systolic wall 712 of computation at Time Set 1 is shown. The
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`systolic wall 712 has been started for a vertical wall of cells and
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`communication of values between adjacent rows 718 through 724
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`in the vertical wall can occur without storing values to memory.
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`EX1005, 8:1-6; EX1003¶95.
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`V. OVERVIEW OF SPLASH 2
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`A. General Architecture of Splash 2
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`The book Buell et al., Splash 2, FPGAs in a Custom Computing Machine
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`(1996) (“Splash2”) (EX1007) was published in 1996 by the IEEE and describes the
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`Splash 2 reconfigurable computing system developed at the Supercomputing
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`Research Center in the early 1990s. EX1007, Preface, 4. It was publicly available
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`to interested members of the public at least as early as 1996, when it was shelved at
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`the MIT library, EX1065, ¶¶8-12; EX1066, ¶¶75, 80-82, and at the Library of
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`Congress, EX1007, 4. Specifically, it was received by MIT on August 8, 1996,
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`and catalogued by October 3, 1996. EX1065,¶¶8-9; EX1066, ¶¶75, 81. It was also
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`received by the Library of Congress by late September 1996 and catalogued
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`thereafter, and registered for copyright at the Copyright Office on May 8, 1997.
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`EX1007, 6; EX1070. EX1007, the Library of Congress version, is a copy of the
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`same Splash2 book on the shelves at MIT. EX1066, ¶77. It is thus prior art to the
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`324 Patent under 35 U.S.C. § 102(a) and (b). See also Power Integrations, Inc., v.
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`Semiconductor Components Industries, LLC, IPR2018-00377, Paper No. 10, *10
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`(July 17, 2018) (IPR petitioners permitted to rely on IEEE publication date)
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`The book depicts the overall system architecture as including a Sparc host
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`computer and a number of “array boards.” EX1007, 12-13; EX1003¶96.
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`Each array board contained 17 Xilinx XC4010 FPGA chips, with X0-X16
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`
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`designating the FPGAs.
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`Each Xilinx FPGA, moreover, contained a 20x20 array of Configurable Logic
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`Blocks (“CLBs”). EX1007, 4, 11, 11-13, 16; EX1003¶¶97-101.
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`Splash 2 array boards were configured for a specific set of operations using
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`VHDL and modern CAD design tools to create a “behavioral description[] of
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`algorithms” that eventually would be compiled into “a loadable FPGA object
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`module,” which object module was then loaded into the FPGAs to form the
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`necessary registers, logic units etc. EX1007, xiii, 46-78; EX1035, 6-6, 6-8, 6-48,
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`6-60, 6-62; EX1003¶¶102-103.
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`A.
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`Systolic Algorithms For Searching Genetic Databases
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`Splash2 describes various algorithms that were executed on the Splash 2
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`system, including algorithms for searching genetic databases, fingerprint matching
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`and image processing. See EX1007, 77-165; EX1003¶104. Chapter 8 of Splash2
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`describes “two systolic array architectures for [genetic] sequence comparison and
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`their implementations on the Splash 2 programmable logic array.” EX1007, 97.
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`The book explains that in comparing genetic sequences in the context of a
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`search, “it is useful to quantify their similarity in terms of a distance measure.” Id.,
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`98. It states that an “edit distance” – defined as “the minimum cost of
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`transforming one sequence to the other” – can be calculated based on assigning
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`values to different types of changes (edits) to one sequence in order to make it look
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`like another sequence. Id. EX1003¶105. Splash2 states that “[t]he edit distance
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`can be computed with a well-known dynamic programming algorithm” described
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`in a prior publication by Sankoff and Kruskal (“the Edit Distance Algorithm”).
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`EX1007, 98, and describes that algorithm in detail, id., 98-100; EX1003¶¶106-108.
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`Splash2 describes two different systolic architectures, one bidirectional and one
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`unidirectional, to implement the Edit Distance Algorithm. EX1007, 100-07;
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`EX1003¶109.
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`a.
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`Bidirectional Systolic Array
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`The first is based on a bidirectional systolic array of multiple processing
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`elements (rectangular boxes, sometimes referred to as “PEs”), as shown in Figure
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`8.5:
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`EX1007, 101; EX1008, 363-76; EX1003¶110.
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`For this implementation of the Edit Distance Algorithm, two genetic
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`sequences (source and target) are shifted in opposite directions through multiple
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`processing elements of the Splash 2 system. Each processing element calculates an
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`edit distance for the characters within it at a particular shift and provides the result
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`as an output to the next processing element on a “distance stream.” EX1007,
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`100-02, 104; EX1003¶¶111-112.
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`Splash2 depicts a processing element used in this implementation for the
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`Edit Distance Algorithm in Figure 8.6, showing characters from the source
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`sequence being input (“SCin”) and output (“SCout”), the source distance stream
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`being input (“SDin”) and output (“SDout”), characters from the target sequence
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`being input (“TCin”) and output (“TCout”) and the target distance stream being
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`input (“TDin”) and output (“TDout”).
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`EX1007, 101; EX1003¶112.
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`Splash2 also discloses in Figure 8.7 the code executed by each processing
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`element in this implementation, which includes a loop for computing the edit
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`distance (i.e., the minimum cost of transforming one sequence to the other)
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`between characters:
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`EX1007, 101; EX1003¶113.
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`b.
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`Unidirectional Systolic Array
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`Splash2 also describes a unidirectional systolic array for calculating edit
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`distance. EX1007, 103-04; EX1003¶114. The data flow through the array, and the
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`operation of a “tag stream” is set forth in Figure 8.9.
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