the mask being scanned across the image, in this case the
`opposite is occurring—the template is hard-wired into
`the FPGA while the image pixels are clocked past it.
`Anorher important opportunity for increased effi-
`ciency lies in the potential to combine multiple templates
`on a single FPGA. The simplest way to do this is to spa-
`tially partition the FPGA into several smaller blocks, each
`ofwhich handles the logic for a single template. Alterna~
`lively, one can seek to identify templates having some
`topological commonality, and winch can therefore share
`parts of adder trees. This is illustrated in Big. 11, which
`
`shows two templates that share several pixels in common,
`and which can be mapped using a set of adder trees-that
`leverage this overlap- The advantage of using FPGAs is
`that FPGAs can be dynamically optimized at the gate
`level
`to exploit template characteristics. A gen-
`eral—purpose correlatot would have to provide large gen-
`eral—purpose adder trees to handle the sunnrfing of all
`possible template bits. The FPGA, however, exploits the
`sparse nature of the templates, and only constructs the
`small adder trees required. FPGAs can Exploit other fac-
`tors such as collapsing adder trees With common ele-
`
`
`
`
`
`
`
`
`
`
`
`
`
`‘P‘B
`
`IEEE SIGNAL PROCESSING MAGAZINE
`
`SEPTEMBER 1993
`
`Petitioner Microsoft Corporation - Ex. 1066, p. 158
`Petitioner Microsoft Corporation - EX. 1066, p. 158
`——-—-——————______________________
`
`

`

`
`
`Template 1
`
`
`
` l____ _l t_
`
`
`A I0. Example binary template with five ”on”pixels (rap) and
`A l l. Template commonalities are exploited to reduce hardware
`corresponding adder flee (bottom).
`toqulrements for computing multiple correlations.
`
`meats, and storing pixels that are not needed by the adder
`trees using RAM~basod shift registers.
`Table 2 illustrates the FPGA resource trade-offs in-
`volved in template mapping. The table gives the FPGA
`utilization for the Xilinx 4062 when four through seven
`template pairs are simultaneously mapped into the FPGA
`using the approach described above. Each template pair
`consists ot'hivo 32 x 32 binary images and is represented
`in the hardware using two template-specific adder trees.
`The number oftemplates per second thatcan becvaluated
`using this approach is a function of many factors includ-
`ing the clock rate, the FPGA configuration time,
`the
`number oftemplates per configuration, the candidate im-
`age and target sizes, the number ofclock cycles needed to
`evaluate the templates at each relative imageltcmplatc oil'-
`set, and on I/O considerations. The performance can be
`upper bounded by assuming that the 1/0 is fully efficient;
`i.e., that the FPGA is always either computing correla-
`tions or being reconfigured. Assuming efficient MO is
`fairly reasonable in the prototype systems we have con—
`stmcted, we have been able to avoid letting the FPGA be
`idle by using scaled down versions of the templates.
`When all ofthese factors are considered together, we find
`that configuration can consume more time than compu-
`tation; i.e. there is a significant perfiirmance penalty due
`to reconfiguration. This overhead will diminish to 10%
`or less when partially reconfigurable FPGAs become
`more widely available. However, for parts that are not
`partially reconfigurable,
`the benefits of increased
`computation power offered by larger FPGAs are to some
`extent mitigated by the larger configuration bitstreants
`and longer reconfiguration times that these parm require.
`
`SEPTEMBER 1 998
`
`Figure 12 shows a configurable computing board
`that was construcred at UCLA as a prototype for the
`template-matching problem. The board contains a “dy—
`namic” FPGA that is used for template correlations and
`is run—time reconfigured, a “static” FPGA for control,
`SRAM for storage of pixels and results, EPROM for
`configuration bitstream storage, and an interface to an
`i960 embedded processor for more advanced configura-
`tion control.
`
`Ongoing Research
`
`Configurable computing has growu from a field with a
`handful of researchers in 1989 [45] Lo one that now re-
`ceives the attention of hundreds of researchers and engi-
`neers in academia,
`industry, defense, and a rapidly
`increasing number of start—up companies. In this section
`we identify some of the open issues in this field and de-
`scribe selected recent and ongoing projects that aim to ad-
`dress them.
`
`One ofthe most interesting questions in configurable
`computing concerns the exrent to which current FPGA
`device and machine architectures should be altered to
`better support computing as opPOsed to the prototyping
`that drove much of the early evolution of FPGAs. Aca-
`demic researchers pursuing this question face the obvious
`challenge of being unable to fully exploit the existing in-
`fiastmcrure of commercial FPGAs and design tools. and
`typically design custom FPGAs to validate their architec-
`ture proposals. Various projects are underway, each at—
`tacking one or more of the well-known weaknesses of
`commercial FPGAs. For example, some researchers are
`
`IEEE SlGNAI. PROCESSING ”WINE
`
`T9
`
`Petitioner Microsoft Corporation - Ex. 1066, p. 159
`Petitioner Microsoft Corporation - EX. 1066, p. 159
`———————————_______________________
`
`

`

`
`
`
`
`investigating architecnnes that are based on relatively
`wide 16-bit datapaths (as opposed to the 1-bit datapaths
`found in today’s FPGAs). While less flexiblethan FPGAs,
`these computing devices are much more efficient in sili-
`con terms and achieve higher arithmetic performance on
`16—bit mmger data. Other Inscarchcrs are hivestiganng
`novel configuration approaches that either reduce config-
`uration time through context-switching or that distribute
`configuration data with data to be processed. Still other
`researchers are merging general~purpose processors and
`FPGA resources on the same die in an attempt to com-
`bine the besr features of both technologies.
`Peter Athanas’ group at Virginia Tech is exploring
`16-bit computing devices based on the “wormhole” tech—
`nique: a computing approach that dish-ibutes configura»
`tion data with the data to be processed [33]. Consisting
`ofa single multiplier and a 4 x 4 array ofI 6—bit arithmetic
`logic units (Allis) interconnecncd by a crossbar, their
`COLT device combines configuration data and data into
`a single packet. Resemhljng dataflow computing in many
`aspects, configuration data in one packet are used to route
`data through the array and to configure ALUs for subse-
`quent processing. COLT has been fabricated and is cur-
`rently being tested.
`Carl Ebeling‘s group at the University ofWashington
`is working on RAPID, another device based on 16-bit
`datapaths [14]. A RAPID arrayeonsisrs ofa mosrlylinear
`array of RAPID cells, each cell consisting of an integer
`multiplier, three integer ALUs, six registers, and finer
`small memories. RAPID is primarilysntically configured
`but uses limited dynamic control to provide run—time
`flexibility.
`Matrix, developed by Andre DeHon and others at
`MIT, is based on a cell that can serve as an instruction
`store, a memory element, or a computational clement. All
`datapaths are 8-bit and these cells are interconnected
`with multilevel interconnect that can be used both for
`data and instruction distribution. Matrix is currently on-
`dergoing commercial development by a new startup
`company, Silicon Spice. Del-Ion has also conducted an
`in—depth study that sets FPGA—based computing in a
`
`general-purpose computing context and has suggested
`several machine architectures [12.].
`:
`FPGA vendors are also pursuing their own research
`and development projects as well as more aggressive fab-
`rication processes. For example, over the next taro years,
`devices using supply voltages of2.5 Volts and below will
`become common. In addition, the technology lag of
`FPGAs with respect to ASICS in terms offeature sine and
`number of metal layers is rapidly shrinking, with
`3—5~layer FPGAs fabricated using sub .3 micron technol~
`ogy expecred to become common. The vendors are also
`likely to both introduce and adopt arcifiteCtural irniova-
`tions that have shown promise in academic research.
`Since future FPGAs will track ASIC technology more
`closely and will benefit from a richer set of architectural
`features, they are likely to compare more favorabiygwith
`ASICs for many applications than that of today.
`:
`The BRASS projecr at U.C. Berkeley under John
`Wawrzynelc [22] is developing a single chip (Garp) that
`incorporates a MIPS~II processor and an FPGA: core
`Whose elements roughlycorrcspond to those found in the
`Xilinx 4000 series. The BRASS researchers have modified
`the bill’s-II protessor, replacing the floating-point unit
`with an FPGA core of their own design, and have ang~
`mcnted the instruction set to include operations that
`manage the FPGA resources. Their goal is to execute
`data-intensive operations on the FPGA core andileave
`general-pnrpoae operations on the processor. A related
`effort at National Semiconductor Corporation is build—
`ing an FPGA thatwill combine a programmable proces-
`sor and a fine—grained FPGA on the same chip [13].
`Other researchers are investigating solutions to hinting
`eonfigtnable computing. elements with more traditional
`processors. For example, Ian Rabaey of U.C. Berkeley
`has examined die allocation of tasks in typical digital sig-
`nal processing and has proposed amultigtanulan‘tyarehi—
`tecture that alans computations to he directed to the
`hardWare that best supports them [34]. Rabaey is also in-
`vestigating strategies for low-power FPGAS. Though
`some power reduction will occur automatically due to
`technology changes, there is substantial opportunity to
`
`30
`
`IEEE SIC-NM. PROCESSING MAGAZINE
`
`SEPTEMBER 1993
`
`Petitioner Microsoft Corporation - Ex. 1066, p. 160
`Petitioner Microsoft Corporation - EX. 1066, p. 160
`—-——-————________________________
`
`

`

`redesign the logical units in FPGAs with powcras a prin-
`demonstrated applications in the following areas: neural
`cipal constraint.
`networks [15], morphology [48], ATR [35] and genetic
`Several groups are looking at FPGAs that have multi—
`algorithms [19]. BYU has also developed a variety ofde—
`ple configurations, or contexts, stored on-chip simulta-
`sign and implementation strategies [25] and provides tu—
`neously. At any given time one context is active and the
`torials for many different FPGA platforms via their web
`others are stored in Iowa planes. Contexts can be
`site: http:f;’splish.ee.byu.edu. A large bibliography ofre~
`swapped extremely quickly—“requiring from one to sev—
`lated papers is also available at this site.
`eral hundred clock cycles to complete—pocentially elimi—
`BYU‘S early research agenda was twofold: one, deter-
`nating much of the overhead involved in loading
`mine what characreristics make an application a good
`configuration bitstreams from off~chip. Of course, con-
`candidate for implementation on an FPGA—based com—
`text switching involves other overheads such as the rc~
`pucing platform, and two, research and understand the
`sources needed tohold multiple contexts on-chip, and the
`strengths and weaknesses ofcurrent devices, system orga—
`hardware and tools to manage context~switching The
`nizations, and tools. Following up on this basic research,
`earliest Work on contest-snatched FPGAs was done at
`BYU is now in the process of developing new system. or-
`Xilinx beginning in 1991, though it remained proprietary
`ganizations and application-development strategies that
`until very recently [42]. In the academic community con-
`are based upon high-performance circuit libraries, do-
`text switching was studied by Tom Knight, DeHon, and
`main-specific compilation, and RTR. BYU also contin—
`their colleagues at MIT [11, All].
`ues to experiment with applications in an effort to find
`Work to develop new configurable computing devices
`additional applications that can exploit this technology.
`also benefits from an understanding of how algorithms
`Iohn Villascnor and his colleagues at UCLA have
`map intoche range ot'architecnires represented by today’s
`demonstrated a video conununications system in which a
`FPGAs and FPGA systems. Some of the most extensive
`single SOOO-gate FPGA was reconfigured four times per
`algorithm mapping work has been performed by the
`image frame to allow compression and transmission ofan
`BYU group led by Brad Hutchings, which has experi-
`image [26]. The Mojave project at UCLA, led by John
`mented with most commercially available (and noncom—
`Villasenor and Bill Mangione-Smjth, has resulted in sev-
`mercially available} FPGAs as well as prototype systems
`eral generations of boards and domain-specific design li-
`such as the HP Terarnac [2] and Splash—2 [4]. BYU has
`braries for the ATE. application described previously.
`These boards included an interface to
`an embedded processor that. per-
`formcd on-the-fly analysis of results
`and modified the PPGA configura-
`tion sequence accordingly [43, 4-4].
`Researchers including Mohammad
`Shajaan and John Sorenscn of die
`Technical University of Denmark
`[38] have examined architectures for
`performing digital filtering using
`FPGAs. Because today’s FPGAs per-
`form multiplications poorly, much of
`the attention in filtering using FPGAs
`has focused on middply—fiee imple-
`mentations. In the funire, it is also
`likely that adaptive filtering algo-
`rithms will find application in FPGAS
`disc are partially reconfigured as the
`filter coefficients evolve.
`Anorhet area of research focus is in
`compilers and tools for configurable
`computing platforms. Ian Page ofOx-
`ford University has developed Han—
`del, a programming language that
`allows programmers to simulta-
`neously develop the FPGA eiucuit cle~
`scriptions and processor software
`with a single description language
`based on OCCAM. [31}. Reine:-
`Hartenstein of the University of
`
`
`
`
`
`A :2. a configurable computing board forflfR Duittat UCLA. the board Includes a “the
`nomic" FPGA that implements template correlations and is rapidly reconfigured during
`and an mom for
`execution, a ”static” FPGA for control, SRAM for image data storage,
`configuration bftstream storage. The board resides in a host PC and
`receives images
`across a PC: bus.
`
`SEWEMBER 1998
`
`IEEE SIGNAL PROCESSING MAGAZINE
`
`8]
`
`Petitioner Microsoft Corporation - Ex. 1066, p. 161
`Petitioner Microsoft Corporation - EX. 1066, p. 161
`——————————.____________________
`
`

`

`Kaisetslautern has developed a machine-level abstrac-
`tion called the Xputer [21] that also derives the target
`machine description and its program From the same de-
`scription. Wayne Luk. at Imperial College is investigat-
`ing formal approaches to FPGA design based on the
`language RUBY [29]. Transmogrifier-C [l7], devel—
`oped by researchers. at the University ofToronto, is a
`programming approach targeted at Toronto’s TM-Z
`custom platform, which is currently under develop-
`ment [27]. Anant Agarwal and his col—
`leagues at MIT are working on a utomated
`programming approaches for very large
`configurable—computing platforms [6].
`In addition, HP developed a very
`easy-to-usc compiler for their Terarnac
`system that automatically partitioned,
`placed, and routed 'a netlist of l—million
`gates into the nearly 1000 custom FPGAs
`that formed Teramac [2].
`Configurable computing is represented
`by a growing presence in the commercial
`world. In addition to FPGA vendors in-
`cluding Xilins and Alters there is a rapidly growing list of
`start-up companies with producrs that are based on
`configurable computing. These including Annapolis
`Microsystems of Annapolis Maryland, which common
`cialized the SPLASH-U architecture; Virtual Computing
`Corporation of Reseda, California; Morphologic of
`Nashua, New Hampshire; and Giga Operations of
`Berkeley.
`
`The lack of a sufficiently general high-level software
`programming model is of course a well-known problem
`among researchers performing work in configurable
`computing, and there are many ongoing efforts in which
`creation of a design tool infrastructure is a goal. EVen if
`such languages can be developed, tested, and adopted1
`there remains die problem ofthe “compiler,” whiCh in the
`domain of FPGAS means the tool chain That translates a
`filnttional or structural description ofthe task into aton—
`
`M C
`
`onfigurable computing is likely to benefit
`from architectural innovations both
`'
`in FPGAs and in the hardware to
`interface to them.
`
`figuration bitstteam that fiilly describes the circuit in the
`FPGA. PPGA place and route tools have always benefited
`from place and route teclmiques used in ASIC design,
`which involves many ofthe same challenges and tradeofih
`interms ofcloclt speed, design complexity, etc. Herrera,
`the several hours needed by current-generation conirner—
`cial FPGA tools to synthesize, place, and route a design
`on an PPGA, while fasr when viewed in the context of
`ASIC design, are unacceptably slow when compared to
`software compilers. To make configurable compllting
`practical will require that FPGA place and route tools he
`made faS‘ECl' by several orders ofmagnitude, most liliiely at
`the cost of highly suboptimal mappings of tasks into
`hardware. One exciting, but as yet unproven, appioach
`Illat has been advocated by William Mangione~Smith of
`UCLA is dynamic compilation, in which small units of
`precompiled FPGA configuration bitstreams can bcicom-
`bined extremely quicldy at run time to constitutee fiJll
`FPGA configuration bitstteam. There are many: chal-
`lenges in dynanuc compilation, not the least of “filth is
`the proprietary nature of configuration bitstteanas for
`most commercial FPGfls.
`'
`.As configurable computing advances it is also impor—
`tant to distinguish techniques that are truly new, such as
`large—scale run—time hardware reconfigurationLfi-om
`techniques that have existed in computing For imany
`years. Many of the “new” approaches in configurable
`computing are in fact existing computing concepts that
`are being implemented in a new domain. For example,
`the ATR algorithm described previously gains its effi—
`ciency from RTR, which can legitimately be claimed as an
`innovation due to configurable computing, and; from
`mapping target templates into template—specific adder
`trees, which is an example of the years~old technique of
`partial evaluation.
`
`Conclusions and Future Directions
`
`It is now clear that for applications requiring deeply
`pipeline-d, highly parallel, bit—level operations including
`cryptography, target recognition, and some types of im-
`age prOcessing, configurable computing machines ofi‘er
`compelling Speed and cost advantages over alternative
`implementations. For these types of applications,
`configurable computing machines are likely to become
`solutions of choice. What is less clear is the extent to
`which configurable computing techniques will become
`useful in more general computing environments, in par
`ticular for applications that inmlve high arithmetic com~
`plexity. Given the dominance and ever—increasing
`(zip-abilities ofmicroprocessors for general-purpose com-
`puting, it seems highly unlikely that any other Computing
`model, including that offered by configurable compue
`log, will make significant inroads against microploccs—
`sors in the foreseeable futul‘t. Widespread adoption of
`configurable computing is also hampered by the lack of
`exactly what microprocessors possess in abundance: 21 set
`ofrelatively easy to use, widely known software program—
`ming languages and associated compilers or interpreters
`that allow a user with little or no knowledge ofthe under-
`lying hardware to instruct a computing platform to per-
`form a desired task.
`
`32
`
`IEEE SIGNAL PROCESSING MAGAZINE
`
`SEPTEMBER 1 933
`
`
`
`
`
`Petitioner Microsoft Corporation - Ex. 1066, p. 162
`Petitioner Microsoft Corporation - EX. 1066, p. 162
`-———————_________________________
`
`

`

`In addition to due obvious trend toward larger devices,
`configurable computing is likely to benefit from architec—
`rural innovations both in FPGAs and in the hardware to
`interface to them. Configurable computing is a young
`field with enormous potential to grow as FPGAs, their
`derivatives, and the tools to use them advance. The
`FPGAs that will be emerging in the next Few years will be
`in excess ofhalf a million equivalent gates, which is large
`enough to support a very diverse range ofapplications. In
`addition,
`the state of the art in architectures for
`configurable computing devices will be significantly en-
`riched by the many ongoing research efl‘orts studying ar-
`clutccturc issues. Existing and perhaps new vendors of
`configurable computing devices, who are now well aware
`of the potential of configurable computing, can be my
`peered produce devices and the associated tools that will
`make FPGAS oftoday look primitive.
`
`John Wiles-om is a Professor at UCLA‘s Electrical Engi-
`neering Department in Los Angeles, California. Brim!
`Hatching: is an Associate Professor at Brigham Young
`University’s Electrical and Computer Engineering De—
`partment in Provo, Utah.
`
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`Petitioner Microsoft Corporation - EX
`. 1066, p. 163
`———————————_________________________
`
`

`

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`84
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`IEEE SIGNAL PROCESSING mums
`
`SEPTEMB ER 1 993
`
`Petitioner Microsoft Corporation - Ex. 1066, p. 164
`Petitioner Microsoft Corporation - EX. 1066, p. 164
`—————-—————.—__________________________
`
`

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`
`Petitioner Microsoft Corporation - Ex. 1066, p. 165
`
`

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`

`proceedings iillEEE Q
`
`
`
`published monthly by the lostltut‘e of Electrical and Electronics Engineers, inc.
`september 1987
`
`SPECIAL ISSUE 0N
`
`HARDWARE AND SOFTWARE FOR DIGITAL SIGNAL PROCESSING
`
`What by Snoilt K. Mlira and Kalyan Mondal
`
`1139
`
`SCANNING THF :ssus
`
`PAPERS
`
`V15!
`
`The [MSMG Family of Digital Signal Processors, K—S. tin, G. A. aniz, and it. Simon Jr.
`1143
`VLSI Processor for Image Processing, M. Sugai, A. Kannma. K. Suzuki. .mri M. Noon
`1160
`1161? Digital Signal Processor for Test and h-‘Iflasttrement Environment, A. Kareem, C. l.. Ease.
`F. Elheri‘dge, and D. h-lclt’lnney.
`1112 The (Ir-aph Search Machine (GSA-ti: A VLSI Architecture for Connected Spec-ch Recognition anti
`Other Applications. .5. C. Clirtskl, T. M. Lalumia. D. R. Cnsslrlny, T. Koh, C. Cerveshi, G. A. Wilson,
`and l. Kumar
`
`1185 DSPfifilttilt: An Algorithm-Specific Digital Signal Processor Peripheral, C. D. Hillman
`1192
`Parallel Bit