roduct Obsolete or Under Obsolescence
`XC4000E and XC4000X Series Field
`Programmable Gate Arrays
`May 14, 1999 (Version 1.6)
`Product Specification
`XC4000E and XC4000X Series
`Low-Voltage Versions Available
`Features
`• Low-Voltage Devices Function at 3.0 - 3.6 Volts
`• XC4000XL:HighPerformanceLow-VoltageVersionsof
`Note:InformationinthisdatasheetcoverstheXC4000E,
`Additional XC4000X Series Features
`XC4000EX devices
`XC4000EX,andXC4000XLfamilies.Aseparatedatasheet
`coverstheXC4000XLAandXC4000XVfamilies.Electrical
`Specificationsandpackage/pininformationarecoveredin
`separatesectionsforeachfamilytomaketheinformation
`• High Performance — 3.3 V XC4000XL
`easiertoaccess,review,andprint.Foraccesstothesesec-
`• High Capacity — Over 180,000 Usable Gates
`tions, see the Xilinx web site at
`• 5 V tolerant I/Os on XC4000XL
`• 0.35 µm SRAM process for XC4000XL
`http://www.xilinx.com/xlnx/xweb/xil_publications_index.jsp
`• Additional Routing Over XC4000E
`• System featured Field-Programmable Gate Arrays
`- almost twice the routing capacity for high-density
`- SelectRAMTM memory: on-chip ultra-fast RAM with
`designs
`-
`synchronous write option
`• Buffered Interconnect for Maximum Speed Blocks
`- dual-port RAM option
`ImprovedVersaRingTMI/OInterconnectforBetterFixed
`•
`- Fully PCI compliant (speed grades -2 and faster)
`Pinout Flexibility
`- Abundant flip-flops
`• 12 mA Sink Current Per XC4000X Output
`- Flexible function generators
`• Flexible New High-Speed Clock Network
`- Dedicated high-speed carry logic
`- EightadditionalEarlyBuffersforshorterclockdelays
`- Wide edge decoders on each edge
`- Virtually unlimited number of clock signals
`- Hierarchy of interconnect lines
`• Optional Multiplexer or 2-input Function Generator on
`Internal 3-state bus capability
`-
`Device Outputs
`- Eight global low-skew clock or signal distribution
`• Four Additional Address Bits in Master Parallel
`networks
`Configuration Mode
`• System Performance beyond 80 MHz
`Introduction
`• Flexible Array Architecture
`• Low Power Segmented Routing Architecture
`• Systems-Oriented Features
`-
`IEEE 1149.1-compatible boundary scan logic
`XC4000Serieshigh-performance,high-capacityFieldPro-
`support
`grammableGateArrays(FPGAs)providethebenefitsof
`-
`Individually programmable output slew rate
`customCMOSVLSI,whileavoidingtheinitialcost,long
`- Programmable input pull-up or pull-down resistors
`developmentcycle,andinherentriskofaconventional
`- 12 mA sink current per XC4000E output
`masked gate array.
`• Configured by Loading Binary File
`- Unlimited re-programmability
`TheresultofthirteenyearsofFPGAdesignexperienceand
`• Read Back Capability
`feedbackfromthousandsofcustomers,theseFPGAscom-
`- Program verification
`binearchitecturalversatility,on-chipSelect-RAMmemory
`Internal node observability
`-
`with edge-triggered and dual-port modes,
`increased
`• Backward Compatible with XC4000 Devices
`speed,abundantroutingresources,andnew,sophisticated
`• Development System runs on most common computer
`softwaretoachievefullyautomatedimplementationof
`platforms
`complex, high-density, high-performance designs.
`-
`Interfaces to popular design environments
`TheXC4000EandXC4000XSeriescurrentlyhave20
`- Fully automatic mapping, placement and routing
`members, as shown inTable1.
`-
`Interactive design editor for design optimization
`May 14, 1999 (Version 1.6)
`6-5
`Petitioner Microsoft Corporation - Ex. 1035, p. 5
`
`RP
`
`0
`
`0
`
`0*
`
`6
`
`

`

`R
`
`6
`
`Product Obsolete or Under Obsolescence
`XC4000E and XC4000X Series Field Programmable Gate Arrays
`XC4000E and XC4000X Series
`Compared to the XC4000
`muchas50%fromXC4000values.See“FastCarryLogic”
`on page18 for more information.
`Select-RAM Memory: Edge-Triggered, Synchro-
`ForreadersalreadyfamiliarwiththeXC4000familyofXil-
`nous RAM Modes
`inxFieldProgrammableGateArrays,themajornewfea-
`turesintheXC4000Seriesdevicesarelistedinthis
`TheRAMinanyCLBcanbeconfiguredforsynchronous,
`section. The biggest advantages of XC4000E and
`edge-triggered,writeoperation.Thereadoperationisnot
`XC4000X devices are significantly increased system
`affected by this change to an edge-triggered write.
`speed,greatercapacity,andnewarchitecturalfeatures,
`Dual-Port RAM
`particularlySelect-RAMmemory. TheXC4000Xdevices
`alsooffermanynewroutingfeatures,includingspecial
`Aseparateoptionconvertsthe16x2RAMinanyCLBintoa
`high-speedclockbuffersthatcanbeusedtocaptureinput
`16x1 dual-port RAM with simultaneous Read/Write.
`data with minimal delay.
`ThefunctiongeneratorsineachCLBcanbeconfiguredas
`AnyXC4000Edeviceispinout-andbitstream-compatible
`either
`level-sensitive (asynchronous) single-port RAM,
`with the corresponding XC4000 device. An existing
`edge-triggered(synchronous)single-portRAM,edge-trig-
`XC4000bitstreamcanbeusedtoprogramanXC4000E
`gered(synchronous)dual-portRAM,orascombinatorial
`device.However,sincetheXC4000Eincludesmanynew
`logic.Configurable RAM Content
`features,anXC4000Ebitstreamcannotbeloadedintoan
`XC4000 device.
`XC4000XSeriesdevicesarenotbitstream-compatiblewith
`TheRAMcontentcannowbeloadedatconfigurationtime,
`equivalentarraysizedevicesintheXC4000orXC4000E
`so that the RAM starts up with user-defined data.
`families.However,equivalentarraysizedevices,suchas
`H Function Generator
`theXC4025,XC4025E,XC4028EX,andXC4028XL,are
`pinout-compatible.
`IncurrentXC4000Seriesdevices,theHfunctiongenerator
`Improvements in XC4000E and XC4000X
`ismoreversatilethanintheoriginalXC4000.Itsinputscan
`comenotonlyfromtheFandGfunctiongeneratorsbut
`Increased System Speed
`alsofromuptothreeofthefourcontrolinputlines.TheH
`functiongeneratorcanthusbetotallyorpartiallyindepen-
`XC4000EandXC4000Xdevicescanrunatsynchronous
`dentoftheothertwofunctiongenerators,increasingthe
`systemclockratesofupto80MHz,andinternalperfor-
`maximum capacity of the device.
`mancecanexceed150MHz.Thisincreaseinperformance
`IOB Clock Enable
`overthepreviousfamiliesstemsfromimprovementsinboth
`deviceprocessingandsystemarchitecture.
`XC4000
`Thetwoflip-flopsineachIOBhaveacommonclockenable
`Seriesdevicesuseasub-micronmulti-layermetalprocess.
`input,whichthroughconfigurationcanbeactivatedindivid-
`Inaddition,manyarchitectural
`improvementshavebeen
`uallyfortheinputoroutputflip-floporboth.Thisclock
`made, as described below.
`enableoperatesexactlyliketheECpinontheXC4000
`CLB.ThisnewfeaturemakestheIOBsmoreversatile,and
`TheXC4000XLfamilyisahighperformance3.3Vfamily
`avoids the need for clock gating.
`basedon0.35µSRAMtechnologyandsupportssystem
`Output Drivers
`speeds to 80 MHz.
`PCI Compliance
`The output pull-up structure defaults to a TTL-like
`totem-pole.Thisdriverisann-channelpull-uptransistor,
`XC4000Series-2andfasterspeedgradesarefullyPCI
`pullingtoavoltageonetransistorthresholdbelowVcc,just
`compliant.XC4000EandXC4000Xdevicescanbeusedto
`liketheXC4000familyoutputs.Alternatively,XC4000
`implement a one-chip PCI solution.
`SeriesdevicescanbegloballyconfiguredwithCMOSout-
`Carry Logic
`puts,withp-channelpull-uptransistorspullingtoVcc.Also,
`theconfigurablepull-upresistorintheXC4000Seriesisa
`Thespeedofthecarrylogicchainhasincreaseddramati-
`p-channeltransistorthatpullstoVcc,whereasintheorigi-
`cally.Someparameters,suchasthedelayonthecarry
`nalXC4000familyitisann-channeltransistorthatpullsto
`chainthroughasingleCLB(TBYP),haveimprovedbyas
`a voltage one transistor threshold below Vcc.
`6-7
`Petitioner Microsoft Corporation - Ex. 1035, p. 7
`
`May 14, 1999 (Version 1.6)
`
`

`

`R
`
`Product Obsolete or Under Obsolescence
`XC4000E and XC4000X Series Field Programmable Gate Arrays
`Table 1: XC4000E and XC4000X Series Field Programmable Gate Arrays
`Number
`
`Typical
`
`MaxLogic(No RAM) Max.RAM(No Logic)
`Max.
`of
`Total
`Gates
`Bits
`Gate Range
`LogicCells
`CLBMatrix
`User I/O
`Flip-Flops
`CLBs
`Device
`(Logic and RAM)*
`64
`256
`64
`XC4002XL
`152
`1,600
`2,048
`1,000 - 3,000
`8 x 8
`80
`360
`100
`XC4003E
`238
`3,000
`3,200
`2,000 - 5,000
`10 x 10
`112
`616
`196
`XC4005E/XL
`466
`5,000
`6,272
`3,000 - 9,000
`14 x 14
`128
`768
`256
`XC4006E
`608
`6,000
`8,192
`4,000 - 12,000
`16 x 16
`144
`936
`324
`XC4008E
`770
`8,000
`10,368
`6,000 - 15,000
`18 x 18
`160
`1,120
`400
`XC4010E/XL
`950
`10,000
`12,800
`7,000 - 20,000
`20 x 20
`192
`1,536
`576
`XC4013E/XL
`1368
`13,000
`18,432
`10,000 - 30,000
`24 x 24
`224
`2,016
`784
`XC4020E/XL
`1862
`20,000
`25,088
`13,000 - 40,000
`28 x 28
`256
`2,560
`1,024
`XC4025E
`2432
`25,000
`32,768
`15,000 - 45,000
`32 x 32
`256
`2,560
`1,024
`XC4028EX/XL
`2432
`28,000
`32,768
`18,000 - 50,000
`32 x 32
`XC4036EX/XL
`3078
`36,000
`41,472
`22,000 - 65,000
`36 x 36
`1,296
`3,168
`288
`XC4044XL
`3800
`44,000
`51,200
`27,000 - 80,000
`40 x 40
`1,600
`3,840
`320
`XC4052XL
`4598
`52,000
`61,952
`33,000 - 100,000
`44 x 44
`1,936
`4,576
`352
`XC4062XL
`5472
`62,000
`73,728
`40,000 - 130,000
`48 x 48
`2,304
`5,376
`384
`XC4085XL
`7448
`85,000
`100,352
`55,000 - 180,000
`56 x 56
`3,136
`7,168
`448
`* Max values of Typical Gate Range include 20-30% of CLBs used as RAM.
`wherehardwareischangeddynamically,orwherehard-
`Note:Allfunctionalityinlow-voltagefamiliesisthesameas
`ware must be adapted to different user applications.
`inthecorresponding5-Voltfamily,exceptwherenumerical
`FPGAsareidealforshorteningdesignanddevelopment
`references are made to timing or power.
`Description
`cycles,andalsoofferacost-effectivesolutionforproduc-
`tionrateswellbeyond5,000systemspermonth.
`XC4000Seriesdevicesareimplementedwitharegular,
`flexible,programmablearchitectureofConfigurableLogic
`Blocks(CLBs),interconnectedbyapowerfulhierarchyof
`Taking Advantage of Re-configuration
`versatileroutingresources,andsurroundedbyaperimeter
`ofprogrammableInput/OutputBlocks(IOBs).Theyhave
`generousroutingresourcestoaccommodatethemost
`FPGAdevicescanbere-configuredtochangelogicfunc-
`complex interconnect patterns.
`tionwhileresidentinthesystem.Thiscapabilitygivesthe
`systemdesigneranewdegreeoffreedomnotavailable
`Thedevicesarecustomizedbyloadingconfigurationdata
`with any other type of logic.
`intointernalmemorycells.TheFPGAcaneitheractively
`readitsconfigurationdatafromanexternalserialor
`Hardwarecanbechangedaseasilyassoftware.Design
`byte-parallelPROM(mastermodes),ortheconfiguration
`updatesormodificationsareeasy,andcanbemadeto
`datacanbewrittenintotheFPGAfromanexternaldevice
`productsalreadyinthefield.AnFPGAcanevenbere-con-
`(slave and peripheral modes).
`figureddynamicallytoperformdifferentfunctionsatdiffer-
`ent times.
`XC4000SeriesFPGAsaresupportedbypowerfuland
`sophisticatedsoftware,coveringeveryaspectofdesign
`Re-configurablelogiccanbeusedtoimplementsystem
`fromschematicorbehavioralentry,floorplanning,simula-
`self-diagnostics,createsystemscapableofbeingre-con-
`tion,automaticblockplacementandroutingofintercon-
`figuredfordifferentenvironmentsoroperations,orimple-
`nects,tothecreation,downloading,andreadbackofthe
`mentmulti-purposehardwareforagivenapplication.Asan
`configuration bit stream.
`addedbenefit,usingre-configurableFPGAdevicessimpli-
`fieshardwaredesignanddebuggingandshortensproduct
`BecauseXilinxFPGAscanbereprogrammedanunlimited
`time-to-market.
`numberoftimes,theycanbeusedininnovativedesigns
`6-6
`May 14, 1999 (Version 1.6)
`Petitioner Microsoft Corporation - Ex. 1035, p. 6
`
`

`

`R
`
`Product Obsolete or Under Obsolescence
`XC4000E and XC4000X Series Field Programmable Gate Arrays
`Additional Improvements in XC4000X Only
`Input Thresholds
`Increased Routing
`Theinputthresholdsof5Vdevicescanbegloballyconfig-
`uredforeitherTTL(1.2Vthreshold)orCMOS(2.5V
`Newinterconnect
`intheXC4000Xincludestwenty-two
`threshold),justlikeXC2000andXC3000inputs.Thetwo
`additionalverticallinesineachcolumnofCLBsandtwelve
`globaladjustmentsofinputthresholdandoutputlevelare
`newhorizontallinesineachrowofCLBs.Thetwelve“Quad
`independentofeachother.TheXC4000XLfamilyhasan
`Lines”ineachCLBrowandcolumnincludeoptionalrepow-
`inputthresholdof1.6V,compatiblewithboth3.3VCMOS
`eringbuffersformaximumspeed.Additionalhigh-perfor-
`and TTL levels.Global Signal Access to Logic
`mance routing near the IOBs enhances pin flexibility.
`Faster Input and Output
`ThereisadditionalaccessfromglobalclockstotheFand
`Afast,dedicatedearlyclocksourcedbyglobalclockbuffers
`G function generator inputs.
`isavailablefortheIOBs.Toensuresynchronizationwiththe
`Configuration Pin Pull-Up Resistors
`regularglobalclocks,aFastCapturelatchdrivenbythe
`earlyclockisavailable.Theinputdatacanbeinitially
`Duringconfiguration,thesepinshaveweakpull-upresis-
`loadedintotheFastCapturelatchwiththeearlyclock,then
`tors.Forthemostpopularconfigurationmode,Slave
`transferredtotheinputflip-floporlatchwiththelow-skew
`Serial,themodepinscanthusbeleftunconnected.The
`globalclock.Aprogrammabledelayontheinputcanbe
`threemodeinputscanbeindividuallyconfiguredwithor
`usedtoavoidhold-timerequirements.See“IOBInputSig-
`withoutweakpull-uporpull-downresistors.Apull-down
`nals” on page20 for more information.
`resistor value of 4.7 kΩ is recommended.
`Latch Capability in CLBs
`Thethreemodeinputscanbeindividuallyconfiguredwith
`orwithoutweakpull-uporpull-downresistorsafterconfigu-
`StorageelementsintheXC4000XCLBcanbeconfigured
`ration.
`aseitherflip-flopsorlatches.Thiscapabilitymakesthe
`ThePROGRAM input pin has a permanent weak pull-up.
`FPGA highly synthesis-compatible.
`Soft Start-up
`IOB Output MUX From Output Clock
`LiketheXC3000A,XC4000Seriesdeviceshave“Soft
`AmultiplexerintheIOBallowstheoutputclocktoselect
`Start-up.”Whentheconfigurationprocessisfinishedand
`eithertheoutputdataortheIOBclockenableastheoutput
`tothepad.Thus,twodifferentdatasignalscanshareasin-
`thedevicestartsup,thefirstactivationoftheoutputsis
`gleoutputpad,effectivelydoublingthenumberofdevice
`automaticallyslew-ratelimited.Thisfeatureavoidspoten-
`outputswithoutrequiringalarger,moreexpensivepack-
`tialgroundbouncewhenalloutputsareturnedonsimulta-
`age. This multiplexer can also be configured as an
`neously.Immediatelyafterstart-up,theslewrateofthe
`AND-gatetoimplementaveryfastpin-to-pinpath.See
`individualoutputsis,asintheXC4000family,determined
`“IOB Output Signals” on page23 for more information.
`by the individual configuration option.
`XC4000 and XC4000A Compatibility
`Additional Address Bits
`ExistingXC4000bitstreamscanbeusedtoconfigurean
`Largerdevicesrequiremorebitsofconfigurationdata.A
`daisychainofseverallargeXC4000Xdevicesmayrequire
`XC4000Edevice.XC4000Abitstreamsmustberecompiled
`aPROMthatcannotbeaddressedbytheeighteenaddress
`for use with the XC4000E due to improved routing
`bitssupportedintheXC4000E.TheXC4000XSeries
`resources,althoughthedevicesarepin-for-pincompatible.
`thereforeextendstheaddressinginMasterParallelconfig-
`uration mode to 22 bits.
`
`6-8
`
`May 14, 1999 (Version 1.6)
`Petitioner Microsoft Corporation - Ex. 1035, p. 8
`
`

`

`R
`
`Product Obsolete or Under Obsolescence
`XC4000E and XC4000X Series Field Programmable Gate Arrays
`Detailed Functional Description
`EachCLBcontainstwostorageelementsthatcanbeused
`tostorethefunctiongeneratoroutputs.However,thestor-
`XC4000 Series devices achieve high speed through
`ageelementsandfunctiongeneratorscanalsobeused
`advancedsemiconductortechnologyandimprovedarchi-
`independently.Thesestorageelementscanbeconfigured
`tecture.TheXC4000EandXC4000Xsupportsystemclock
`asflip-flopsinbothXC4000EandXC4000Xdevices;inthe
`ratesofupto80MHzandinternalperformanceinexcess
`XC4000Xtheycanoptionallybeconfiguredaslatches.DIN
`of150MHz.ComparedtoolderXilinxFPGAfamilies,
`canbeusedasadirectinputtoeitherofthetwostorage
`XC4000Seriesdevicesaremorepowerful.Theyoffer
`elements.H1candrivetheotherthroughtheHfunction
`on-chipedge-triggeredanddual-portRAM,clockenables
`generator.Functiongeneratoroutputscanalsodrivetwo
`onI/Oflip-flops,andwide-inputdecoders.Theyaremore
`outputsindependentofthestorageelementoutputs.This
`versatileinmanyapplications,especiallythoseinvolving
`versatility increases logic capacity and simplifies routing.
`RAM.Designcyclesarefasterduetoacombinationof
`ThirteenCLBinputsandfourCLBoutputsprovideaccess
`increasedroutingresourcesandmoresophisticatedsoft-
`tothefunctiongeneratorsandstorageelements.These
`ware.Basic Building Blocks
`inputsandoutputsconnecttotheprogrammableintercon-
`nect resources outside the block.
`Function Generators
`Xilinxuser-programmablegatearraysincludetwomajor
`configurableelements:configurablelogicblocks(CLBs)
`Fourindependentinputsareprovidedtoeachoftwofunc-
`and input/output blocks (IOBs).
`tiongenerators(F1-F4andG1-G4).Thesefunctiongen-
`• CLBs provide the functional elements for constructing
`erators,withoutputslabeledF’andG’,areeachcapableof
`the user’s logic.
`implementinganyarbitrarilydefinedBooleanfunctionof
`•
`IOBs provide the interface between the package pins
`fourinputs.Thefunctiongeneratorsareimplementedas
`and internal signal lines.
`memorylook-uptables.Thepropagationdelayistherefore
`independent of the function implemented.
`Three other types of circuits are also available:
`Athirdfunctiongenerator,labeledH’,canimplementany
`• 3-Statebuffers(TBUFs)drivinghorizontallonglinesare
`Booleanfunctionofitsthreeinputs.Twooftheseinputscan
`associated with each CLB.
`optionallybetheF’andG’functionalgeneratoroutputs.
`• Wideedgedecodersareavailablearoundtheperiphery
`Alternatively,oneorbothoftheseinputscancomefrom
`of each device.
`outsidetheCLB(H2,H0).Thethirdinputmustcomefrom
`• An on-chip oscillator is provided.
`outside the block (H1).
`Programmable interconnect
`resources provide routing
`SignalsfromthefunctiongeneratorscanexittheCLBon
`pathstoconnecttheinputsandoutputsoftheseconfig-
`twooutputs.F’orH’canbeconnectedtotheXoutput.G’or
`urable elements to the appropriate networks.
`H’ can be connected to the Y output.
`Thefunctionalityofeachcircuitblockiscustomizedduring
`ACLBcanbeusedtoimplementanyofthefollowingfunc-
`configurationbyprogramminginternalstaticmemorycells.
`tions:
`Thevaluesstoredinthesememorycellsdeterminethe
`logicfunctionsandinterconnectionsimplementedinthe
`• any function of up to four variables, plus any second
`FPGA.Eachoftheseavailablecircuitsisdescribedinthis
`functionofuptofourunrelatedvariables,plusanythird
`section.
`function of up to three unrelated variables1
`Configurable Logic Blocks (CLBs)
`• any single function of five variables
`• any function of four variables together with some
`ConfigurableLogicBlocksimplementmostofthelogicin
`functions of six variables
`anFPGA.TheprincipalCLBelementsareshownin
`• some functions of up to nine variables.
`Figure1.Two4-inputfunctiongenerators(FandG)offer
`Implementingwidefunctionsinasingleblockreducesboth
`unrestrictedversatility. Mostcombinatoriallogicfunctions
`thenumberofblocksrequiredandthedelayinthesignal
`needfourorfewerinputs.However,athirdfunctiongener-
`path, achieving both increased capacity and speed.
`ator(H)isprovided.TheHfunctiongeneratorhasthree
`TheversatilityoftheCLBfunctiongeneratorssignificantly
`inputs.Eitherzero,one,ortwooftheseinputscanbethe
`improvessystemspeed.Inaddition,thedesign-software
`outputsofFandG;theotherinput(s)arefromoutsidethe
`toolscandealwitheachfunctiongeneratorindependently.
`CLB.TheCLBcan,therefore,implementcertainfunctions
`This flexibility improves cell usage.
`ofuptoninevariables,
`likeparitycheckorexpand-
`able-identity comparison of two sets of four inputs.
`1. When three separate functions are generated, one of the function outputs must be captured in a flip-flop internal to the CLB. Only two
`unregistered function generator outputs are available from the CLB.
`May 14, 1999 (Version 1.6)
`6-9
`Petitioner Microsoft Corporation - Ex. 1035, p. 9
`
`6
`
`

`

`Product Obsolete or Under Obsolescence
`XC4000E and XC4000X Series Field Programmable Gate Arrays
`4
`C1 • • • C4
`
`R
`
`Q
`
`Bypass
`
`Bypass
`
`YQ
`
`Y
`XQ
`
`D E
`
`D E
`
`S/R
`CONTROL
`
`S/R
`CONTROL
`
`LOGIC
`FUNCTION
`OFF', G',
`H'
`ANDH1
`
`G4G3G2G1
`SD
`C RD
`F4F3F2F1
`SD Q
`C RD
`K(CLOCK)
`H'F'
`X
`Multiplexer Controlled
`Figure 1: Simplified Block Diagram of XC4000 Series CLB (RAM and Carry Logic functions not shown)
`by Configuration Program
`X6692
`Flip-FlopsTheCLBcanpassthecombinatorialoutput(s)totheinter-
`Clock Enable
`Theclockenablesignal(EC)isactiveHigh.TheECpinis
`sharedbybothstorageelements.Ifleftunconnectedfor
`connectnetwork,butcanalsostorethecombinatorial
`either,theclockenableforthatstorageelementdefaultsto
`resultsorotherincomingdatainoneortwoflip-flops,and
`the active state. EC is not invertible within the CLB.
`connect their outputs to the interconnect network as well.
`Thetwoedge-triggeredD-typeflip-flopshavecommon
`Table 2: CLB Storage Element Functionality
`clock(K)andclockenable(EC)inputs.Eitherorbothclock
`(active rising edge is shown)
`inputscanalsobepermanentlyenabled.Storageelement
`functionality is described inTable2.
` Mode
` K
` EC
` SR
` D
` Q
`Latches (XC4000X only)
`Power-Upor
`X
`X
`X
`X
`SR
`GSR
`TheCLBstorageelementscanalsobeconfiguredas
`X
`X
`1
`X
`SR
`latches. Thetwolatcheshavecommonclock(K)andclock
`1*
`0*
`D
`D
`Flip-Flop
`__/
`enable (EC)
`inputs. Storage element
`functionality is
`0
`X
`0*
`X
`Q
`described inTable2.
`Clock Input
`1
`1*
`0*
`X
`Q
`Latch
`0
`1*
`0*
`D
`D
`Eachflip-flopcanbetriggeredoneithertherisingorfalling
`Both
`X
`0
`0*
`X
`Q
`clockedge.Theclockpinissharedbybothstorageele-
`ments.However,theclockisindividuallyinvertibleforeach
`Legend:X__/SR0*1*
`Don’t care
`storageelement.Anyinverterplacedontheclockinputis
`Rising edge
`automatically absorbed into the CLB.
`Set or Reset value. Reset is default.
`Input is Low or unconnected (default value)
`Input is High or unconnected (default value)
`6-10
`May 14, 1999 (Version 1.6)
`Petitioner Microsoft Corporation - Ex. 1035, p. 10
`
`H1
`
`DIN/H2
`
`SR/H0
`
`EC
`
`11
`
`DINF'G'H'
`G'H'
`
`DINF'G'H'
`
`LOGIC
`FUNCTION
`OFG1-G4
`
`G'
`
`LOGIC
`FUNCTION
`OFF1-F4
`
`F'
`
`

`

`R
`
`Product Obsolete or Under Obsolescence
`XC4000E and XC4000X Series Field Programmable Gate Arrays
`Set/Reset
`Twofastfeed-throughpathsareavailable,asshownin
`Figure1.Atwo-to-onemultiplexeroneachoftheXQand
`Anasynchronousstorageelementinput(SR)canbecon-
`YQoutputsselectsbetweenastorageelementoutputand
`figuredaseithersetorreset.Thisconfigurationoption
`anyofthecontrolinputs.Thisbypassissometimesusedby
`determinesthestateinwhicheachflip-flopbecomesoper-
`the automated router to repower internal signals.
`ationalafterconfiguration.Italsodeterminestheeffectofa
`Control Signals
`GlobalSet/Resetpulseduringnormaloperation,andthe
`effectofapulseontheSRpinoftheCLB.Allthree
`MultiplexersintheCLBmapthefourcontrolinputs(C1-C4
`set/resetfunctionsforanysingleflip-floparecontrolledby
`inFigure1)intothefourinternalcontrolsignals(H1,
`the same configuration data bit.
`DIN/H2,SR/H0,andEC).Anyoftheseinputscandriveany
`Theset/resetstatecanbeindependentlyspecifiedforeach
`of the four internal control signals.
`flip-flop.Thisinputcanalsobeindependentlydisabledfor
`When the logic function is enabled, the four inputs are:
`either flip-flop.
`• EC — Enable Clock
`Theset/resetstateisspecifiedbyusingtheINITattribute,
`• SR/H0 — Asynchronous Set/Reset or H function
`orbyplacingtheappropriatesetorresetflip-floplibrary
`generator Input 0
`symbol.
`• DIN/H2 — Direct In or H function generator Input 2
`SR is active High. It is not invertible within the CLB.
`• H1 — H function generator Input 1.
`Global Set/Reset
`Whenthememoryfunctionisenabled,thefourinputsare:
`• EC — Enable Clock
`AseparateGlobalSet/Resetline(notshowninFigure1)
`• WE — Write Enable
`setsorclearseachstorageelementduringpower-up,
`• D0 — Data Input to F and/or G function generator
`re-configuration,orwhenadedicatedResetnetisdriven
`• D1 — Data input to G function generator (16x1 and
`active.Thisglobalnet(GSR)doesnotcompetewithother
`16x2 modes) or 5th Address bit (32x1 mode).
`routingresources;itusesadedicateddistributionnetwork.
`Using FPGA Flip-Flops and Latches
`Eachflip-flopisconfiguredaseithergloballysetorresetin
`thesamewaythatthelocalset/reset(SR)isspecified.
`Theabundanceofflip-flopsintheXC4000Seriesinvites
`Therefore,ifaflip-flopissetbySR,itisalsosetbyGSR.
`pipelineddesigns.Thisisapowerfulwayofincreasingper-
`Similarly, a reset flip-flop is reset by both SR and GSR.
`formancebybreakingthefunctionintosmallersubfunc-
`tionsandexecutingtheminparallel,passingontheresults
`STARTUP
`throughpipelineflip-flops.Thismethodshouldbeseriously
`consideredwhereverthroughputismoreimportantthan
`GSRGTSCLKDONEINQ1Q4Q2Q3
`PAD
`latency.
`IBUF
`ToincludeaCLBflip-flop,placetheappropriatelibrary
`symbol.Forexample,FDCEisaD-typeflip-flopwithclock
`enableandasynchronousclear.Thecorrespondinglatch
`symbol (for the XC4000X only) is called LDCE.
`Figure 2: Schematic Symbols for Global Set/Reset
`X5260
`InXC4000Seriesdevices,theflipflopscanbeusedasreg-
`istersorshiftregisterswithoutblockingthefunctiongener-
`GSRcanbedrivenfromanyuser-programmablepinasa
`atorsfromperformingadifferent,perhapsunrelatedtask.
`globalresetinput.Tousethisglobalnet,placeaninputpad
`Thisabilityincreasesthefunctionalcapacityofthedevices.
`andinputbufferintheschematicorHDLcode,drivingthe
`GSRpinoftheSTARTUPsymbol.(SeeFigure2.)Aspe-
`TheCLBsetuptimeisspecifiedbetweenthefunctiongen-
`cificpinlocationcanbeassignedtothisinputusingaLOC
`eratorinputsandtheclockinputK.Therefore,thespecified
`attributeorproperty,justaswithanyotheruser-program-
`CLBflip-flopsetuptimeincludesthedelaythroughthe
`mablepad.Aninvertercanoptionallybeinsertedafterthe
`function generator.
`inputbuffertoinvertthesenseoftheGlobalSet/Resetsig-
`Using Function Generators as RAM
`nal.Alternatively, GSR can be driven from any internal node.
`OptionalmodesforeachCLBmakethememorylook-up
`tablesintheF’andG’functiongeneratorsusableasan
`Data Inputs and Outputs
`arrayofRead/Writememorycells.Availablemodesare
`to the XC4000/A/H families),
`level-sensitive (similar
`Thesourceofastorageelementdatainputisprogramma-
`edge-triggered,anddual-portedge-triggered.Depending
`ble.ItisdrivenbyanyofthefunctionsF’,G’,andH’,orby
`ontheselectedmode,asingleCLBcanbeconfiguredas
`theDirectIn(DIN)blockinput.Theflip-flopsorlatchesdrive
`either a 16x2, 32x1, or 16x1 bit array.
`the XQ and YQ CLB outputs.
`May 14, 1999 (Version 1.6)
`6-11
`Petitioner Microsoft Corporation - Ex. 1035, p. 11
`
`6
`
`

`

`R
`
`√
`
`Product Obsolete or Under Obsolescence
`XC4000E and XC4000X Series Field Programmable Gate Arrays
`SupportedCLBmemoryconfigurationsandtimingmodes
`Theselectedtimingmodeappliestobothfunctiongenera-
`for single- and dual-port modes are shown inTable3.
`tors within a CLB when both are configured as RAM.
`XC4000Seriesdevicesarethefirstprogrammablelogic
`The number of read ports is also programmable:
`deviceswithedge-triggered(synchronous)anddual-port
`• Single Port: each function generator has a common
`RAMaccessibletotheuser. Edge-triggeredRAMsimpli-
`read and write port
`fiessystemtiming.Dual-portRAMdoublestheeffective
`• Dual Port: both function generators are configured
`throughputofFIFOapplications.Thesefeaturescanbe
`togetherasasingle16x1dual-portRAMwithonewrite
`individually programmed in any XC4000 Series CLB.
`port and two read ports. Simultaneous read and write
`operations to the same or different addresses are
`Advantages of On-Chip and Edge-Triggered RAM
`supported.
`Theon-chipRAMisextremelyfast.Thereadaccesstimeis
`RAMconfigurationoptionsareselectedbyplacingthe
`thesameasthelogicdelay.
`Thewriteaccesstimeis
`appropriate library symbol.
`slightlyslower. Bothaccesstimesaremuchfasterthan
`any off-chip solution, because they avoid I/O delays.
`Choosing a RAM Configuration Mode
`Edge-triggeredRAM,alsocalledsynchronousRAM,isa
`TheappropriatechoiceofRAMmodeforagivendesign
`featureneverbeforeavailableinaFieldProgrammable
`shouldbebasedontimingandresourcerequirements,
`GateArray.Thesimplicityofdesigningwithedge-triggered
`desiredfunctionality,andthesimplicityofthedesignpro-
`RAM,andthemarkedlyhigherachievableperformance,
`cess. Recommended usage is shown inTable4.
`adduptoasignificantimprovementoverexistingdevices
`The difference between level-sensitive, edge-triggered,
`with on-chip RAM.
`anddual-portRAMisonlyinthewriteoperation.Read
`ThreeapplicationnotesareavailablefromXilinxthatdis-
`operation and timing is identical for all modes of operation.
`cussedge-triggeredRAM:“XC4000EEdge-Triggeredand
`Dual-PortRAMCapability,”
`“ImplementingFIFOsin
`Table 4: RAM Mode Selection
`XC4000ERAM,”and“SynchronousandAsynchronous
`FIFODesigns.”Allthreeapplicationnotesapplytoboth
`Dual-Port
`XC4000E and XC4000X RAM.
`Level-Sens
`Edge-Trigg
`Edge-Trigg
`itive
`ered
`ered
`Table 3: Supported RAM Modes
`Use for New
`No
`Yes
`Yes
`Designs?
`Edge-
`Level-
`16x1
`16x2
`32x1
`Size (16x1,
`Triggered
`Sensitive
`1/2 CLB
`1/2 CLB
`1 CLB
`Registered)
`Timing
`Timing
`Simultaneous
`Single-Port
`No
`No
`Yes
`Read/Write
`Dual-Port
`2X (4X
`Relative
`X
`2X
`Performance
`effective)
`RAM Configuration Options
`ThefunctiongeneratorsinanyCLBcanbeconfiguredas
`RAM Inputs and Outputs
`RAM arrays in the following sizes:
`TheF1-F4andG1-G4inputstothefunctiongeneratorsact
`• Two 16x1 RAMs: two data inputs and two data outputs
`asaddresslines,selectingaparticularmemorycellineach
`with identical or, if preferred, different addressing for
`look-up table.
`each RAM
`ThefunctionalityoftheCLBcontrolsignalschangeswhen
`• One 32x1 RAM: one data input and one data output.
`the function generators are configured as RAM. The
`OneForGfunctiongeneratorcanbeconfiguredasa16x1
`DIN/H2,H1,andSR/H0linesbecomethetwodatainputs
`RAMwhiletheotherfunctiongeneratorsareusedtoimple-
`(D0,D1)andtheWriteEnable(WE)inputforthe16x2
`ment any function of up to 5 inputs.
`memory.Whenthe32x1configurationisselected,D1acts
`as the fifth address bit and D0 is the data input.
`Additionally,theXC4000SeriesRAMmayhaveeitherof
`two timing modes:
`Thecontentsofthememorycell(s)beingaddressedare
`availableattheF’andG’function-generatoroutputs.They
`• Edge-Triggered (Synchronous): data written by the
`canexittheCLBthroughitsXandYoutputs,orcanbecap-
`designated edge of the CLB clock. WE acts as a true
`tured in the CLB flip-flop(s).
`clock enable.
`• Level-Sensitive(Asynchronous):anexternalWEsignal
`ConfiguringtheCLBfunctiongeneratorsasRead/Write
`acts as the write strobe.
`memorydoesnotaffectthefunctionalityoftheotherpor-
`6-12
`May 14, 1999 (Version 1.6)
`Petitioner Microsoft Corporation - Ex. 1035, p. 12
`
`√
`√
`
`√
`
`√
`
`√
`√
`
`

`

`R
`
`Product Obsolete or Under Obsolescence
`XC4000E and XC4000X Series Field Programmable Gate Arrays
`nals.Aninternalwritepulseisgeneratedthatperformsthe
`tionsoftheCLB,withtheexceptionoftheredefinitionofthe
`write.SeeFigure4andFigure5forblockdiagramsofa
`controlsignals.In16x2and16x1modes,theH’function
`generatorcanbeusedtoimplementBooleanfunctionsof
`CLBconfiguredas16x2and32x1edge-triggered,sin-
`F’,G’,andD1,andtheDflip-flopscanlatchtheF’,G’,H’,or
`gle-port RAM.
`D0 signals.
`TherelationshipsbetweenCLBpinsandRAMinputsand
`outputsforsingle-port,edge-triggeredmodeareshownin
`Single-Port Edge-Triggered Mode
`Table5.
`Edge-triggered (synchronous) RAM simplifies timing
`requirements.XC4000Seriesedge-triggeredRAMtiming
`TheWriteClockinput(WCLK)canbeconfiguredasactive
`operateslikewritingtoadataregister.Dataandaddress
`oneithertherisingedge(default)orthefallingedge.Ituses
`arepresented.Theregisterisenabledforwritingbyalogic
`thesameCLBpin(K)usedtoclocktheCLBflip-flops,butit
`Highonthewriteenableinput,WE.Thenarisingorfalling
`canbeindependentlyinverted.Consequently,theRAM
`clockedgeloadsthedataintotheregister,asshownin
`outputcanoptionallyberegisteredwithinthesameCLB
`Figure3.
`eitherbythesameclockedgeastheRAM,orbytheoppo-
`siteedgeofthisclock.ThesenseofWCLKappliestoboth
`functiongeneratorsintheCLBwhenbothareconfigured
`as RAM.
`TWPS
`WCLK (K)
`TheWEpinisactive-Highandisnotinvertiblewithinthe
`CLB.Note:ThepulsefollowingtheactiveedgeofWCLK(TWPS
`TWHS
`TWSS
`WE
`inFigure3)mustbelessthanonemillisecondwide.For
`mostapplications,thisrequirementisnotoverlyrestrictive;
`TDHS
`TDSS
`however,itmustnotbeforgotten.StoppingWCLKatthis
`pointinthewritecyclecouldresultinexcessivecurrentand
`DATA IN
`evendamagetothelargerdevicesifmanyCLBsarecon-
`TASS
`TAHS
`figured as edge-triggered RAM.
`Table 5: Single-Port Edge-Triggered RAM Signals
`ADDRESS
`RAM Signal
`CLB Pin
`Function
`TILO
`TILO
`D
`D0 or D1 (16x2,
`Data In
`TWOS
`16x1), D0 (32x1)
`DATA OUT
`OLD
`NEW
`A[3:0]
`F1-F4 or G1-G4
`Address
`A[4]
`D1 (32x1)
`Address
`Figure 3: Edge-Triggered RAM Write Timing
`WE
`WE
`Write Enable
`X6461
`Complextimingrelationshipsbetweenaddress,data,and
`WCLK
`Clock
`K
`writeenablesignalsarenotrequired,andtheexternalwrite
`SPO(Data Out)
`F’ or G’
`Single Port Out
`enablepulsebecomesasimpleclockenable.Theactive
`(Data Out)
`edgeofWCLKlatchestheaddress,inputdata,andWEsig-
`
`6
`
`May 14, 1999 (Version 1.6)
`
`6-13
`Petitioner Microsoft Corporation - Ex. 1035, p. 13
`
`

`

`Product Obsolete or Under Obsolescence
`XC4000E and XC4000X Series Field Programmable Gate Arrays
`D1
`D0
`
`C1 • • • C4
`
`4
`
`WE
`
`EC
`
`R
`
`WRITE
`DECODER
`1 of 16
`
`WRITE
`DECODER
`1 of 16
`
`DIN
`16-LATCH
`ARRAY
`WRITE PULSE
`DIN
`16-LATCH
`ARRAY
`WRITE PULSE
`
`MUX
`READ
`ADDRESS
`
`MUX
`READ
`ADDRESS
`
`G'
`
`F'
`
`X6752
`
`G1 • • • G4
`
`4
`
`4
`LATCH
`ENABLE
`
`4
`4
`F1 • • • F4
`LATCH
`ENABLE
`K
`(CLOCK)
`Figure 4: 16x2 (or 16x1) Edge-Triggered Single-Port RAM
`4
`C1 • • • C4
`ECEC
`D1/A4
`D0
`
`WE
`
`G1 • • • G4
`F1 • • • F4
`
`4
`
`WRITE
`DECODER
`1 of 16
`
`4
`LATCH
`ENABLE
`
`MUX
`READ
`ADDRESS
`
`G'
`
`F'
`
`H'
`
`DIN
`16-LATCH
`ARRAY
`WRITE PULSE
`DIN
`WRITE
`16-LATCH
`MUX
`DECODER
`ARRAY
`4
`4
`1 of 16
`LATCH
`ENABLE
`K
`READ
`(CLOCK)
`WRITE PULSE
`ADDRESS
`Figure 5: 32x1 Edge-Triggered Single-Port RAM (F and G addresses are identical)
`X6754
`6-14
`May 14, 1999 (Version 1.6)
`Petitioner Microsoft Corporation - Ex. 1035, p. 14
`
`

`

`R
`
`6
`
`Product Obsolete or Under Obsolescence
`XC4000E and XC4000X Series Field Programmable Gate Arrays
`Table 6: Dual-Port Edge-Triggered RAM Signals
`Dual-Port Edge-Triggered Mode
`Indual-portmode,boththeFandGfunctiongenerators
`RAM Signal
`CLB Pin
`Function
`areusedtocreateasingle16x1RAMarraywithonewrite
`D
`D0
`Data In
`portandtworeadports.TheresultingRAMarraycanbe
`A[3:0]
`