(12) United States Patent
`ROever
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 8,543,746 B2
`Sep. 24, 2013
`
`USOO8543746B2
`
`(54) SELF-SYNCHRONIZING DATA STREAMING
`BETWEEN ADDRESS-BASED PRODUCER
`AND CONSUMERCIRCUITS
`
`(75)
`(73)
`(*)
`
`Inventor:
`Assignee:
`Notice:
`
`Jens Roever, Los Gatos, CA (US)
`NXP B.V., Eindhoven (NL)
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 748 days.
`
`(21)
`(22)
`(86)
`
`(87)
`
`(65)
`
`(60)
`
`(51)
`
`(52)
`
`Appl. No.:
`PCT Fled:
`
`11/917,624
`Jun. 23, 2006
`PCT/B2O06/052O68
`
`PCT NO.:
`S371 (c)(1),
`Jul. 7, 2009
`(2), (4) Date:
`PCT Pub. No.: WO2OO6/137044
`PCT Pub. Date: Dec. 28, 2006
`Prior Publication Data
`US 2009/O3OO256A1
`Dec. 3, 2009
`
`Related U.S. Application Data
`Provisional application No. 60/694,113, filed on Jun.
`24, 2005.
`Int. C.
`G06F I3/00
`G06F 3/00
`G06F5/00
`G06F I3/36
`G06F L/04
`G06F L/2
`G06F 15/16
`G06F 3/42
`H04L 5/00
`H04L 700
`U.S. C.
`USPC ................. 710/100; 710/29: 710/58; 710/60;
`710/61; 710/306; 710/308; 7.10/310; 713/375;
`713/400; 713/401
`
`(2006.01)
`(2006.01)
`(2006.01)
`(2006.01)
`(2006.01)
`(2006.01)
`(2006.01)
`(2006.01)
`(2006.01)
`(2006.01)
`
`(58) Field of Classification Search
`USPC ................. 710/29, 58, 60, 61, 100, 306, 308,
`710/310; 713/375,400, 401
`See application file for complete search history.
`
`(56)
`
`References Cited
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`U.S. PATENT DOCUMENTS
`3,810,114. A * 5/1974 Yamada et al. ............... T10,306
`4,232,294. A * 1 1/1980 Burke et al. .................. 370,444
`(Continued)
`FOREIGN PATENT DOCUMENTS
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`(Continued)
`OTHER PUBLICATIONS
`“NA901158: Address Compare Synchronization”, Nov. 1, 1990,
`IBM, IBM Technical Disclosure Bulletin, vol. 33, Iss. 6A, pp.
`58-60.
`
`JP
`JP
`
`(Continued)
`Primary Examiner — Faisal M Zaman
`(57)
`ABSTRACT
`A circuit arrangement and method facilitate the direct stream
`ing of data between producer and consumer circuits (12P.
`12C) that are otherwise configured to communicate over an
`address-based network (18). Sync signals (46,56) are gener
`ated for each of producer and consumer circuits (12P, 12C)
`from the address information encoded into requests that com
`municate the data streams output by the producer circuit
`(12P) and expected by the consumer circuit (12C). The sync
`signals (46,56) for the producer and consumer circuits (12C)
`are then used to selectively modify the data stream output by
`the producer circuit (12P) to a format expected by the con
`Sumer circuit (12C). Typically, such modification takes the
`form of inserting data into the data stream when the consumer
`circuit (12C) expects more data than output by the producer
`circuit (12P), and discarding data communicated by the pro
`ducer circuit (12P) when the consumer expects less data than
`that output by the producer circuit (12P).
`33 Claims, 7 Drawing Sheets
`
`
`
`SATUS, RO
`
`PATENT OWNER DIRECTSTREAM, LLC
`EX. 2173, p. 1
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`

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`US 8,543,746 B2
`Page 2
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`(56)
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`6,134,155. A * 10/2000 Wen ......................... 365,189,04
`6,240,458 B1* 5/2001 Gilbertson .................... 709,232
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`6,275,878 B1* 8/2001 Yashima et al. ...
`... 710,61
`“NN771 12382: Programmable Storage Address Compare”, Nov. 1,
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`“NN77091562: Address Controlled Clocking of Recirculating
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`vol. 20, Iss. 4, pp. 1562-1564.*
`7,197.581 B2 * 3/2007 Kohashi .......................... T10/28
`7585 R: S388. free al"
`785 “NN71122172: Memory Address Sync and Stop Controller”, Dec. 1,
`7,694,061 B2 * 4/2010 Franchuk et al. ..
`710,310
`1971, IBM, IBM Technical Disclosure Bulletin, vol. 14, Iss. 7, pp.
`2002/0026599 A1
`2/2002 Kanazashi et al. .
`713/400
`2172-2173.
`2003. O156220 A1* 8, 2003 Narita ............
`348,571
`2003.0185325 A1 * 10, 2003 Wahl ............................. 375.362
`
`2003/0233513 A1* 12/2003 EZoe ............................. T11 103
`2004/OOO6666 A1* 1 2004 MOSS ....
`T11 5
`2005/0280650 A1* 12/2005 Komagata
`345,531
`2007/0130395 A1
`6/2007 Hsu ................................. T10.61
`2007/0162168 A1* 7/2007 Thompson ...................... TOO.94
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`348,530
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`... 713/400
`2011/0167292 A1* 7, 2011 Bohino .......................... T13/400
`
`
`
`FOREIGN PATENT DOCUMENTS
`ck
`8.6 A ck
`2.
`O8149121 A * 6, 1996
`11016346 A * 1, 1999
`2012O58973 A * 3, 2012
`2004O63836 A2
`T 2004
`2004O9.9995 A2 11/2004
`2005O10759 A1
`2, 2005
`
`E.
`JP
`JP
`JP
`WO
`WO
`WO
`
`* cited by examiner
`
`PATENT OWNER DIRECTSTREAM, LLC
`EX. 2173, p. 2
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`

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`U.S. Patent
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`Sep. 24, 2013
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`Sheet 1 of 7
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`US 8,543,746 B2
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`|PBLOCK
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`MEMORY F.
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`2.
`2P
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`PBLOCK
`(PRODUCER)
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`-22
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`-
`20
`sistan
`CRCU
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`AS k-SE
`NEWORK
`MEMORY
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`PATENT OWNER DIRECTSTREAM, LLC
`EX. 2173, p. 3
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`Sheet 2 of 7
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`|º»,|JENIHON | HVIS
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`PATENT OWNER DIRECTSTREAM, LLC
`EX. 2173, p. 4
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`U.S. Patent
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`Sep. 24, 2013
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`Sheet 3 of 7
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`US 8,543,746 B2
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`
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`7 FILLY
`AONGOING)
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`(SYNCN==SYNCOUT)
`FIG. 4
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`PATENT OWNER DIRECTSTREAM, LLC
`EX. 2173, p. 5
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`U.S. Patent
`US. Patent
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`Sep. 24, 2013
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`EX. 2173, p. 6
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`PATENT OWNER DIRECTSTREAM, LLC
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`EX. 2173, p. 7
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`U.S. Patent
`US. Patent
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`Sep. 24, 2013
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`PATENT OWNER DIRECTSTREAM, LLC
`EX. 2173, p. 8
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`PATENT OWNER DIRECTSTREAM, LLC
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`U.S. Patent
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`Sep. 24, 2013
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`Sheet 7 Of 7
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`US 8,543,746 B2
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`(0N 0ONDÝ \ TIH A
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`(100H º NIH)í
`(100) ºg NN
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`PATENT OWNER DIRECTSTREAM, LLC
`EX. 2173, p. 9
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`

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`US 8,543,746 B2
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`1.
`SELF-SYNCHRONIZING DATA STREAMING
`BETWEEN ADDRESS-BASED PRODUCER
`AND CONSUMER CIRCUITS
`
`2
`throughput. With a dedicated connection, however, address
`information is not used, and strict synchronization is required
`to ensure that the data being communicated by a producer is
`properly received by the consumer, typically by ensuring that
`the amount of data produced is the same as the amount of data
`consumed. In the case of video data, for example, strict Syn
`chronization is often required to ensure that each frame of
`Video data sent by a producer is recognized as a complete
`frame of video data by a consumer. If, for example, a producer
`transmitted more or less data in a frame than was expected by
`a consumer, data intended for one frame of video data may be
`interpreted by the consumer as being incorporated into an
`adjacent frame of video data. Once frames become unaligned,
`spurious artifacts, or even a moving picture may result in the
`displayed video picture.
`IP blocks with dedicated connections tend to have more
`limited applicability in a narrower set of end use applications.
`Moreover, producer and consumer IP blocks that communi
`cate over a dedicated connection typically must be specifi
`cally configured to ensure that the proper alignment of pro
`duced and consumed data streams is ensured. On the other
`hand, it would be desirable in many circumstances to simply
`be able to adapt existing IP blocks configured for address
`based communications to communicate overa dedicated con
`nection. Prior attempts to adapt such IP blocks to use dedi
`cated connections have simply discarded address
`information, and have required strict control over the amount
`of data communicated to ensure continued alignment and
`synchronization of the producer and consumer data streams.
`Often, once data streams lose synchronization and become
`unaligned, a reset is required to restore synchronization of the
`data streams. Therefore, a need continues to exist in the art for
`a manner of enabling IP blocks that support address-based
`communications to communicate over dedicated connec
`tions.
`The invention addresses these and other problems associ
`ated with the prior art by providing a circuit arrangement and
`method that facilitate the direct streaming of data between
`producer and consumer circuits that are otherwise configured
`to communicate overan address-based network. In particular,
`embodiments consistent with the invention generate sync
`signals for each of producer and consumer circuits from the
`address information encoded into requests that communicate
`the data streams output by the producer circuit and expected
`by the consumercircuit. The sync signals for the producer and
`consumer circuits are then used to selectively modify the data
`stream output by the producer circuit to a format expected by
`the consumer circuit. Typically, Such modification takes the
`form of inserting data into the data stream when the consumer
`circuit expects more data than output by the producer circuit,
`and discarding data communicated by the producer circuit
`when the consumer expects less data than that output by the
`producer circuit.
`These and other advantages and features, which character
`ize the invention, are set forth in the claims annexed hereto
`and forming a further parthereof. However, for a better under
`standing of the invention, and of the advantages and objec
`tives attained through its use, reference should be made to the
`Drawings, and to the accompanying descriptive matter, in
`which there is described exemplary embodiments of the
`invention.
`FIG. 1 illustrates an example block diagram of an inte
`grated circuit incorporating multiple circuits coupled to one
`another over an address-based network, and incorporating
`self-synchronizing data streaming consistent with the inven
`tion.
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`This invention relates to the field of electronic design, and
`in particular to a memory access system and method for
`streaming data between circuits in an electronic design.
`The communication of data between circuits in an elec
`tronic design is often a significant factor in the overall per
`formance of the electronic design. Particularly in complex,
`high performance integrated circuits such as System On Chip
`(SOC) designs, the communication of data between circuits
`Such as IP blocks often plays a significant role in the process
`ing capability of Such designs.
`In many instances, IP blocks rely on address-based net
`works to communicate data to and from other IP blocks. In an
`address-based network, data packets are associated with spe
`cific addresses in a memory address space, which effectively
`serve to identify each data packet in a manner that is recog
`nizable both to producer circuits that transmit data and con
`Sumer circuits that receive data. In some instances, push-type
`communications can be used, where a producer of data acts as
`a master, and pushes data to a consumer of data acting as a
`slave. In other instances, pull-type communications can be
`used, where a consumer of data acts as a master, and polls data
`from a producer acting as a slave.
`In still other instances, a shared memory may be used
`facilitate the communication of data between IP blocks. To
`communicate data between IP blocks coupled to a shared
`memory, one IP block, serving as a producer of the data,
`writes the data to the shared memory over an address-based
`network using address-based communications. Then, another
`IP block, serving as a consumer of the data, reads the now
`stored data from the shared memory over the same address
`based network, again using address-based communications.
`35
`Shared memory-based communications offer a number of
`benefits in terms of design flexibility and reuse. Since each
`data packet is associated with a specific address, the data
`packet is easier to correlate between the producer and con
`Sumer IP blocks. Furthermore, specific IP blocks can be
`40
`designed to utilize a standardized interface, which reduces the
`amount of customization required to utilize an IP block in a
`specific design.
`In addition, the operations of producer and consumer IP
`blocks in a shared memory architecture typically need not be
`tightly coordinated or synchronized. Due to this flexibility,
`shared memory architectures are particularly useful in con
`nection with processing data streams such as video data
`streams. Often, a producer IP block will write a frame of
`video data to a shared memory, while a consumer IP block
`50
`will read the frame of video data and perform additional
`processing on the data. Furthermore, in some instances the
`consumer IP block may not even be required to read all of a
`video frame stored by a producer IP block, e.g., when it is
`desirable to display only a portion of a video frame.
`One drawback with the use of a shared memory architec
`ture, however, is that bandwidth to and from a shared memory
`is a limited resource. Producer and consumer IP blocks, as
`well as potentially other IP blocks in a circuit design, are
`required to share access to the memory. Should too many IP
`blocks attempt to access the shared memory at the same time,
`the throughput of each block can suffer.
`Due to these limitations, therefore, it may be desirable or
`even necessary in Some designs to utilize dedicated, negoti
`ated connections between some IP blocks. By doing so, con
`tention over access to a shared memory is reduced, thus
`enabling higher communication rates and greater data
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`US 8,543,746 B2
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`FIG. 2 illustrates an example block diagram of an exem
`plary implementation of the stream interface circuit of FIG.1.
`FIG.3 illustrates an example state diagram of the operation
`of the producer and consumer sync circuits of FIG. 2.
`FIG. 4 illustrates an example state diagram of the operation
`of the state machine in the stream control circuit of FIG. 2.
`FIG. 5 illustrates an example block diagram of an exem
`plary implementation of the memory interface circuits of
`FIG 1.
`FIG. 6 illustrates an example block diagram of an alternate
`exemplary implementation of the memory interface circuits
`of FIG. 1.
`FIG. 7 illustrates an example block diagram of another
`exemplary implementation of the stream interface circuit of
`FIG. 1, suitable for use with horizontal and vertical syncing.
`FIG. 8 illustrates an example state diagram of the operation
`of the producer and consumer sync circuits of FIG. 7.
`FIG. 9 illustrates an example state diagram of the operation
`of the state machine in the stream control circuit of FIG. 7.
`The embodiments discussed hereinafter utilize self-syn
`chronization to facilitate the direct streaming of data between
`producer and consumer circuits in an electronic design. In
`particular, the address information encoded into memory
`access requests generated by producer and consumer circuits
`in connection with respectively outputting and receiving data
`streams is used to generate producer and consumer Sync
`signals. These signals are used, in turn, to self-synchronize
`the data stream output by the producer circuit with that
`expected by the consumer circuit.
`Such self-synchronization incorporates selectively modi
`fying the data stream output by the producer circuit to a
`format expected by the consumer circuit. Typically, Such
`modification takes the form of inserting data into the data
`stream when the consumer circuit expects more data than
`35
`output by the producer circuit, and discarding data commu
`nicated by the producer circuit when the consumer expects
`less data than that output by the producer circuit.
`Often, the generation of sync signals is based upon detec
`tion of boundaries between blocks of data incorporated into a
`data stream. As such, a sync signal may be asserted, for
`example, in response to detecting the first address in a
`memory block being output by a producer circuit or received
`by a consumer circuit. As will be discussed in greater detail
`below, for example, it may be assumed in some environments
`that a memory block is a contiguous range of memory
`addresses, such that a sync signal may be asserted whenever
`an address for a current request is found to be less than or
`equal to (i.e., not greater than), that of the previous request.
`Moreover, in video streaming applications, it may be desir
`able to detect the end of a line of video data, as well as the end
`of a frame of video data, and provide two dimensional (i.e.,
`horizontal and vertical) self-synchronization. Other manners
`of deriving a sync signal from address information will be
`appreciated by one of ordinary skill in the art having the
`benefit of the instant disclosure.
`A producer circuit consistent with the invention may be any
`circuit capable of outputting a data stream, while a consumer
`circuit consistent with the invention may be any circuit
`capable of receiving a data stream. It will be appreciated that
`producer circuits may also function as consumer circuits, and
`Vice versa. In the illustrated embodiments, producer and con
`Sumer circuits are implemented as IP blocks suitable for
`incorporation into the same integrated circuit design such as
`a SOC design. However, it will be appreciated that such
`circuits need not be implemented as modular blocks, nor do
`Such circuits need to be disposed on the same integrated
`
`4
`circuit device. The invention is therefore not limited to the
`particular embodiments discussed herein.
`As noted above, each producer and consumer circuit is
`configured to communicate over an address-based network,
`typically through the issuance of read or write requests that
`incorporate address information associated with the data that
`is to be read or written as a result of the requests. It will be
`appreciated that address information may be provided on
`dedicated interconnect wires, or may be communicated over
`the same interconnect wires as the request and/or data to be
`communicated. Moreover, a producer or consumer circuit
`may still be able to communicate over an address-based net
`work concurrently with communicating with another circuit
`via a self-synchronized dedicated connection as described
`herein.
`Now turning to the drawings, wherein like numbers denote
`like parts throughout the several views, FIG. 1 illustrates an
`integrated circuit 10 incorporating a plurality of circuits 12,
`e.g., IP blocks, each having a dedicated address-based
`memory interface 14 that is used to couple the associated
`circuit 12 to a shared memory 16 via an address-based net
`work 18. Address-based network 18 may be implemented, for
`example, as a Pipelined Memory Access Network (PMAN)
`such as is disclosed in PCT Publication No. WO20040.99995,
`the disclosure of which is incorporated by reference herein. In
`the alternative, other types of address-based networks, e.g.,
`pull-type architectures, push-type architectures, multi-drop
`bus architectures, etc., may be used in the alternative.
`As noted above, each circuit, or IP block, 12 is typically
`configured to communicate over an address-based network.
`In general, it will be appreciated that any circuit that generates
`requests to transmit and/or receive data, where the data is
`associated with and identified by address information, may be
`considered to be configured to communicate over an address
`based network. To this extent, each memory interface 14 is
`configured to output memory access requests including com
`mand and address information (and for write requests, write
`data) over network 18. Furthermore, in the case of read
`requests, each memory interface 14 is configured to receive
`read data from network 18 responsive to requests issued
`thereby.
`As also noted above, it may be desirable to provide self
`synchronized direct data streaming between IP blocks, and
`thus bypass the need to utilize a shared memory to commu
`nicate data between the IP blocks, e.g., a producer IP block
`identified at 12P and a consumer IP block identified at 12C.
`To implement such functionality, a stream interface circuit
`20, coupled intermediate IP blocks 12P, 12C, provides a
`direct communication link configured in a manner described
`in greater detail below. When so configured, IP blocks 12P
`and 12C are capable of communicating a data stream from IP
`block 12P to IP block 12C by respectively issuing series of
`write memory access requests and read memory access
`requests to stream interface circuit 20.
`In the illustrated embodiment, stream interface circuit 20 is
`coupled to additional ports defined in the memory interface
`circuits 14 for IP blocks 12P, 12C. Such ports may be pro
`vided along with ports for coupling to address-based network
`18, thus enable both address-based communication and direct
`data streaming to be utilized by each such IP block. In other
`embodiments, however, an IP block configured for commu
`nication over an address-based network may not actually be
`coupled to any address-based network in integrated circuit
`design. Thus, it will be appreciated that an IP block config
`ured for communication over an address-based network need
`not necessarily actively communicate over Such a network
`when incorporated into a working design.
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`PATENT OWNER DIRECTSTREAM, LLC
`EX. 2173, p. 11
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`5
`Now turning to FIG. 2, an exemplary implementation of
`stream interface circuit 20 is illustrated in greater detail. Cir
`cuit 20 incorporates a pair of sync generation circuits, a
`producer sync generation circuit 24 and a consumer Sync
`generation circuit 26, coupled to a stream control circuit 28.
`Producer Sync generation circuit 24 is coupled to a producer
`IP block 12P and is configured to receive a data stream over a
`data interconnect 30, with packets of data in the data stream
`correlated via associated address information received over
`an address interconnect32. Likewise, consumer Sync genera
`tion circuit 26 is coupled to a consumer IP block 12C and is
`configured to output a data stream over a data interconnect 34
`responsive to address information received over an address
`interconnect 36. It will be appreciated that additional request
`information, e.g., command information, read/write informa
`tion, priority information, etc. may also be received, con
`veyed and/or utilized by circuit 20 consistent with the inven
`tion.
`Producer Sync generation circuit 24 is configured to selec
`tively assert a sync signal that indicates the beginning of a
`memory block of data in a data stream. In this embodiment, it
`is assumed that a memory block communicated by IP block
`12P includes a set of requests addressed to a contiguous range
`of memory addresses in a memory address space. As such, the
`beginning of a memory block of data can be detected by
`comparing the address associated with each request output by
`IP block 12P with the address associated with the prior
`request output by the IP block.
`As a result, for each request received from IP block 12P.
`circuit 24 passes the data for Such request unchanged over
`interconnect 38 and to stream control circuit 28 via a data
`interconnect 40. However, for the address associated with
`each request, the address is passed to a last address register 42
`and a comparator 44. Register 42 stores the address associ
`ated with a previous request for use by comparator 44 in
`comparing the previous, or last address, with that of the
`current request. By passing the address of the current request
`to register 42, the address will be stored in the register for use
`in comparing with the next request received by circuit 24.
`Comparator 44 selectively asserts a producer Sync signal 46
`responsive to the address associated with the current request
`being less than or equal to that of the last request, and thus
`indicates when the current request is directed to a first address
`in a new memory block.
`Consumer sync generation circuit 26 is likewise config
`ured to selectively assert a sync signal that indicates the
`beginning of a memory block of data in a data stream
`expected by the consumer IP block 12C. For each request
`received from IP block 12C, circuit 26 passes the data for such
`request from stream control circuit 28 over interconnects 48.
`50 and along to IP block 12C. However, for the address
`associated with each request, the address is passed to a last
`address register 52 and a comparator 54, which operate in a
`similar manner to register 42 and comparator 44 to selectively
`assert a consumer sync signal 56 responsive to the address
`associated with the current request being less than or equal to
`that of the last request, and thus indicates when the current
`request is directed to a first address in a new memory block.
`The manner in which each sync circuit 24, 26 operates is
`further explained in connection with the state diagram 70 of
`FIG. 3. State diagram 70 includes a reset state 72 to which
`each circuit 24, 26 is initially set. Reset state 72 transitions to
`a sync state 74 during which the respective sync signal 46,56
`is asserted. A transition to a data state 76, where the sync
`signal 46, 56 is not asserted, occurs once a request is received
`having an address (AT) that represents the next sequential
`address relative to that of the previous request (stored in
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`register 42, 52, and represented as AT-1). Then, once a request
`is received having an address that is less than or equal to that
`of the previous request, a transition occurs to state 74 to
`reassert the sync signal 46, 56, indicating the start of a new
`memory block. In addition, upon a reset, each of states 74,76
`transitions to state 72.
`Returning to FIG. 2, the configuration of stream control
`circuit 28, which receives data from a producer data stream
`over interconnect 40 and outputs data to a consumer data
`stream over interconnect 50, is further illustrated. Circuit 28
`includes a state machine 58 that is responsive to sync signals
`46, 56 to control a drain/fill circuit 60 that selectively modifies
`the consumer data stream output to consumer IP block 12C
`relative to the producer data stream received from producer IP
`block 12P. Specifically, drain/fill circuit 60 may be configured
`to selectively drain, or discard, data from the producer data
`stream and/or fill or insert data into the producer data stream
`to align the producer and consumer data streams. In addition,
`state machine 58 may optionally be configured to output a
`status or interrupt signal 62 whenever a misalignment occurs,
`to notify other circuitry in the design (e.g., an interrupt con
`troller 22 as shown in FIG. 1).
`With reference to FIG.4, the operation of state machine 58
`is further illustrated by state diagram 80. Initially, state
`machine 58 begins in a reset state 82, and then transitions to
`a pass data on state 84. Based upon whether the producer Sync
`signal 46 (SYNCIN) and the consumer sync signal 56 (SYN
`COUT) are asserted during each communication cycle, the
`state machine either remains in state 84 or transitions to one of
`a drainincoming state 86 and a fill outgoing state 88. Specifi
`cally, if sync signals 46.56 are in the same state, state machine
`58 remains in state 84, whereby data forwarded from the
`producer data stream is passed unchanged to the consumer
`data stream.
`However, if consumer sync signal 56 is asserted before
`producer sync signal 46, a transition occurs to state 86, which
`results in state machine 58 controlling drain/fill circuit 60 to
`discard data from the producer IP block 12P, and thus prevent
`such data from being passed on to the consumer IP block 12C.
`In addition, it may be desirable at this time to stall the con
`Sumer IP block 12C from issuing any further requests, using
`any number of manners known in the art (e.g., via handshak
`ing). State machine 58 remains in this state until sync signals
`46, 56 are once again equal, which results in a transition back
`to state 84.
`If producer Sync signal 46 is asserted before consumer Sync
`signal 56, a transition occurs to state 88, which results in state
`machine 58 controlling drain/fill circuit 60 to insert padding
`data into the consumer data stream. In addition, it may be
`desirable at this time to stall the producer IP block 12P from
`issuing any further requests. State machine 58 remains in this
`state until sync signals 46, 56 are once again equal, which
`results in a transition back to state 84. In addition, upon a
`reset, each of states 84, 86, 88 transitions to state 82.
`The padding data to be inserted into a data stream by circuit
`60 may vary in different embodiments. For example, a con
`stant value may be used for the padding data, or in the alter
`native, the last data value passed from the producer IP block
`may simply be repeated. In addition, it may be desirable in
`Some embodiments to allow the padding data to be program
`mable. For example, in a video processing application, it may
`be desirable to enable padding data representative of a black
`or grey pixel to be used.
`Therefore, it may be seen that through the operation of state
`machine 58 responsive to sync signals 46,56, the amount of
`data communicated in a data stream by producer IP block 12P
`is selectively modified if necessary to match the amount of
`
`PATENT OWNER DIRECTSTREAM, LLC
`EX. 2173, p. 12
`
`

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`data expected by consumer IP block 12C. Furthermore,
`through this self-synchronization, the respective producer
`and consumer data streams are effectively aligned at each
`memory block boundary. Of note, the address information
`associated with each request from the producer and consumer
`IP blocks is never passed to the other block. Rather, other than
`being used to generate the respective sync signals, the address
`information is effectively discarded, thus enabling address
`based protocols to effectively be used to communicate a data
`stream over a direct connection between IP blocks.
`Now turning to FIGS. 5 & 6, as noted above, the manner in
`which an IP block may be configured to utilize self-synchro
`nized data streaming, while still being configured to commu
`nicate over an address-based network, may differ in various
`embodiments. FIG. 5, for example, illustrates one exemplary
`implementation of the memory interface circuit 14 of an IP
`block 12, wherein a request communication link 90, which
`communicates command and address information, as well as
`data, associated with access requests, is coupled to a pair of
`communication links 92, 94 through a multiplexer/demulti
`plexer96. In the illustrated embodiment, for example, com
`munication link 92 may be used to communicate over an
`address-based network, while communication link94 may be
`used to communicate via self-synchronized data streaming
`through coupling with a stream interface circuit 20. It will
`also be appreciated that memory interface 14 may also incor
`porate functionality for providing handshaking as well as
`ensuring that requests and data transmissions comply with
`any necessary communication protocols.
`In the embodiment of FIG. 5, it is assumed that multi
`plexer/demultiplexer 96 is responsive to a mode signal 98
`generated by IP block 12, which is used to effectively select
`one of the two communication links 92.94 for use by IP block
`12. It will be appr