UNITED STATES PATENT AND TRADEMARK OFFICE
`
`______________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`______________________
`
`MICROSOFT CORPORATION,
`
`Petitioner,
`
`v.
`
`DIRECTSTREAM, LLC,
`Patent Owner.
`_______________________
`
`IPR2018-01594 (Patent 6,434,687 B1)
`IPR2018-01599 (Patent 6,076,152)
`IPR2018-01600 (Patent 6,247,110 B1)
`IPR2018-01601 (Patent 7,225,324 B2)
`IPR2018-01602 (Patent 7,225,324 B2)
`IPR2018-01603 (Patent 7,225,324 B2)
`IPR2018-01604 (Patent 7,421,524 B2)
`IPR2018-01605 (Patent 7,620,800 B2)
`IPR2018-01606 (Patent 7,620,800 B2)
`IPR2018-01607 (Patent 7,620,800 B2)
`__________________________
`
`DECLARATION OF DR. TAREK EL-GHAZAWI
`
`PATENT OWNER DIRECTSTREAM, LLC
`EX. 2166, p. 1
`
`

`

`1. I have been retained by counsel for Patent Owner as an expert witness in the
`
`I. ENGAGEMENT
`
`above-captioned proceedings.
`
`2. It is my understanding that Microsoft has filed and the Board has instituted 10 IPR
`
`Petitions (IPR2018-01594, -1599, -1600, -1601, -1602, -1603, -1604, -1605, -1606, -
`
`1607) (I understand that the -1601, -1602, and -1603 have been consolidated into one
`
`IPR and that the -1605, -1606, and -1607 have been consolidated into one IPR).
`
`3. It is my understanding that the various mentioned IPRs cover U.S. Patent Nos.:
`
`6,434,687 (“’687”); 6,076,152 (“’152”); 6,247,110 (“’110”) 7,225,324 (“’324”);
`
`7,421,524 (“’524”); and 7,620,800 (“’800”) (collectively, “the Patents-in-Suit”).
`
`4. All of the opinions stated in this report are based on my personal knowledge and/or
`
`professional judgment. If called as a witness during the trial in this matter, I am prepared
`
`to testify competently about them. I am over the age of eighteen.
`
`II. QUALIFICATIONS
`
`5. My curriculum vitae is attached as Exhibit A. A summary of my qualifications
`
`relevant to this case is provided below.
`
`6. I am a Professor of Electrical and Computer Engineering at The George
`
`Washington University (GWU), where I lead the university-wide Strategic Academic
`
`Program in High-Performance Computing. My research interests include, among other
`
`PATENT OWNER DIRECTSTREAM, LLC
`EX. 2166, p. 2
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`

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`areas, high-performance computing, computing architectures, and reconfigurable and
`
`embedded computing.
`
`7. I was the founding director of the GW Institute for Massively Parallel Applications
`
`and Computing Technologies (IMPACT) and was a founding Co-Director of the NSF
`
`Industry/University Center for High-Performance Reconfigurable Computing at GWU
`
`and directed it for about ten years. I have led many industry and federally funded
`
`research projects in reconfigurable computing and published close to three hundred
`
`research publications. I received many honors in my field, a few examples follow. I
`
`was elected an IEEE Fellow for my contributions to reconfigurable computing and
`
`parallel programming (only one in a thousand members get that honor). Professor El-
`
`Ghazawi is a Fellow of the IEEE and was selected as a Research Faculty Fellow of the
`
`IBM Center for Advanced Studies, Toronto. I was also awarded the Alexander von
`
`Humboldt Research Award, from the Humboldt Foundation in Germany (given yearly to
`
`100 scientists across all areas from around the world), and the GW SEAS Distinguished
`
`Researcher Award. El-Ghazawi has served as a senior U.S. Fulbright Scholar. I was
`
`selected an IEEE Computer Society Distinguished Visitors Program Speaker and a
`
`Distinguished Visiting Fellow by the U.K. Royal Academy of Engineering.
`
`8. As an expert in the High-Performance Computing Domain, I have been
`
`interviewed by major public and technical media when important relevant events occur,
`
`including IEEE Spectrum and the Washington Post. Further, I participated in more than
`
`PATENT OWNER DIRECTSTREAM, LLC
`EX. 2166, p. 3
`
`

`

`one task force trying to define future research directions in High-Performance
`
`Computing and Reconfigurable Computing.
`
`9. My research was funded extensively by such government organizations like
`
`NSA, DARPA, NSF, AFOSR, NASA, ONR, and industrial organizations such as
`
`Intel, AMD, HP, SGI.
`
`10. I have served in many editorial roles including an Associate Editor for the IEEE
`
`Transactions Parallel and Distributed Computing and the IEEE Transaction on
`
`Computers. I also chaired and co-chaired many IEEEE international conferences and
`
`symposia including IEEE PGAS 2015, IEEE/ACM CCGrid2018, IEEE
`
`HPCC/SmartCity/DSS 2017 to name a few.
`
`
`
`III. COMPENSATION AND PRIOR TESTIMONY
`
`11. I am being compensated $495 per hour for my work in this matter but my
`
`compensation does not depend on the opinions I render or the outcome of these
`
`proceedings. I do not have a personal interest in the outcome of this proceeding.
`
`12. I have only previously testified in the co-pending district cases against
`
`Microsoft and Amazon and that was by deposition and declaration. Those cases are
`
`listed below:
`
`(a) SRC Labs, LLC et al v. Microsoft Corporation, No. 2:18-cv-00321-
`
`JLR (W.D. Wash.).
`
`PATENT OWNER DIRECTSTREAM, LLC
`EX. 2166, p. 4
`
`

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`(b) SRC Labs, LLC et al v. Amazon Web Services, Inc et al, No. 2:18-cv-
`
`00317-JLR (W.D. Wash.).
`
`13. The opinions expressed in this declaration are not exhaustive of my opinions
`
`on the patentability of any of the claims in the Patents-in-Suit. Therefore, the fact that I
`
`do not address a particular point should not be understood to indicate any agreement on
`
`my part that any claim otherwise complies with any patentability requirements.
`
`14. I am not an employee of the Patent Owner or any affiliate or subsidiary thereof
`
`or any prior owner of the Patents-in-Suit. I also have no direct or indirect financial or
`
`other interest of any kind in the underlying litigation, dispute, or outcome thereof,
`
`between the Patent Owner and Microsoft, including, without limitation, no financial
`
`interest in any of the Patent Owner’s patents.
`
`
`
`IV. INFORMATION CONSIDERED
`
`15. My opinions are based on my years of education, research, prior publications,
`
`and experience, as well as my review of several prior art references I was asked to
`
`review as described in greater detail below.
`
`16. Any material I independently searched for and found and/or reviewed and
`
`used to support my opinions will be specifically mentioned in my opinions below and a
`
`copy attached to this declaration as Exhibit B, if possible.
`
`PATENT OWNER DIRECTSTREAM, LLC
`EX. 2166, p. 5
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`

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`V. SUMMARY OF PERSONAL EXPERIENCES IN HPRC AND STATE OF
`THE ART
`
`A. Background of High Performance Computing and Reconfigurable
`Computing
`
`17. State of the Art HPC Systems: While historically other challengers came and
`
`went, the gold standard for high-performance computing until 1990s was vector
`
`machines. Vector machines were entrusted with solving a wide range of large
`
`scientific and engineering problems that required high floating-point precision and
`
`especially those that performed vector computations which is common in those fields,
`
`although they were very expensive. The reason for the high cost was the use of
`
`custom built processors that are small in numbers using expensive technologies such
`
`as gallium arsenide and static memories. Such systems were also dissipating quite a
`
`bit of heat and required expensive provisions for cooling. The world leader in Vector
`
`Supercomputers was undisputedly Cray, a company created by Seymour Cray,
`
`recognized as a main pioneer of supercomputing and the foremost leader in vector
`
`supercomputers. Note that Supercomputing and High-Performance Computing are
`
`used interchangeably to mean the same thing.
`
`18. Under vector machines, many software code and hardware optimizations were
`
`introduced including loop execution and avoiding unnecessary memory transfers
`
`between operations, to name some. Key to all that were the Cray pioneering ideas in
`
`building advanced vector processors with flexible pipelining arrangements,
`
`PATENT OWNER DIRECTSTREAM, LLC
`EX. 2166, p. 6
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`

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`interconnected together and to a large number of interleaved shared memory modules
`
`using large and fast switches from the hardware side, with a set of software
`
`optimizations that leverages such capabilities.
`
`19. In late 1991, then, senator Al Gore introduced the High-Performance
`
`Computing Act. As a result of this act, the High-Performance Computing and
`
`Communications (HPCC) Program was released in 1993. Among the objectives of
`
`the program were to move from Vector Machines to massively parallel systems that
`
`can leverage massive numbers of commercial off the shelf processors to achieve speed
`
`instead of the custom built processors.
`
`20. While performance was the main goal of the field of supercomputing, usability
`
`started to surface as a barrier in the face of developing well-performing
`
`supercomputing applications in a reasonable amount of time as the systems exposed
`
`their inner sophistication and made it hard for domain scientists who did not formally
`
`study computer science and engineering. As an eventual result, DARPA launched in
`
`2002 the High-Productivity Computing Systems initiative, which in simple terms had
`
`the goal of reducing the “Time-to-Solution”, which means both the development time
`
`and the program execution time. Such computers can be then referred to as
`
`“Productive”.
`
`21. The Introduction of FPGAs: When two computer circuits/modules are to be
`
`interconnected and where each follows a different protocol/logic of doing things, an
`
`PATENT OWNER DIRECTSTREAM, LLC
`EX. 2166, p. 7
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`

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`interfacing circuit (also known as a glue logic) is placed in between to perform the
`
`translation. Interfacing circuits used to be implemented with fixed hardwired circuits.
`
`Eventually, some devices with limited flexibility/programmability were introduced
`
`such as Programmable Logic Arrays (PLAs), Programmable Array Logic (PAL) and
`
`Complex Programmable Logic Devices (CPLDs). These devices were limiting. For
`
`example, programming a PLA amounts to burning fuses to leave some connections in
`
`place and remove other to establish the desired circuit. Therefore it was not possible
`
`for these chips to be reprogrammed.
`
`22. Field Programmable Gate Arrays (FPGAs) were originally introduced with the
`
`vision of serving as a new type of glue logic that can be configured in the field and
`
`reconfigured as needed to accommodate upgrades and changes. Their malleability
`
`allowed users to customize these interfaces to translate between both pieces of
`
`hardware and optimize how they work together. At this point, in the early 1990s, the
`
`small size of the FPGAs and the lack of proper software interface, to name a couple of
`
`challenges, made running real applications on them impracticable.
`
`23. As larger FPGAs developed, it became possible to fit applications into them.
`
`The prevailing architecture to run applications on FPGAs involved interfacing the
`
`FPGA card as an accelerator to the microprocessor through Peripheral Component
`
`Interconnect (PCI). This architecture had severe limitations, such as the slow rate of
`
`data transfer between the FPGAs and microprocessor. FPGAs were still too small to
`
`PATENT OWNER DIRECTSTREAM, LLC
`EX. 2166, p. 8
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`

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`run floating point operations though, so applications were also limited to integer
`
`applications such as image processing.
`
`24. I co-authored various papers on the topic and I am attaching to this declaration
`
`two that I co-authored with Dr. Buell (USC, and Project Manager of the Splash 2), Dr.
`
`Gaj (GMU) and Dr. Kindratenko (UIUC). The first of those two papers [BUEL2007] is
`
`an introduction to the guest editors where the IEEE Computer Magazine. This simply
`
`establishes that even in 2007 this was a very hot topic and all contributions were valued.
`
`The article highlights the scalable SRC crossbar switch and indicates that when it comes
`
`to application development using the available commercial systems at the time, SRC
`
`provided a semi-integrated microprocessor-FPGA solution and where the hardware was
`
`side was developed still in C or FORTRAN dialect , while the rest of the vendors did
`
`not have an integrated system level solution and only addressed the FPGA side using
`
`third party FPGA only tools. The second paper, introduced a year later also by the four
`
`co-authors [El-GH2008] attempts to survey state of the art and assess where the
`
`industry and research stood at that time.
`
`25. The amount of data movement required for single image processing was too
`
`large for use in an FPGA architecture that interfaced the FPGA through the PCI bus,
`
`especially for applications that do not require data reuse to amortize the cost of the
`
`transfers.
`
`PATENT OWNER DIRECTSTREAM, LLC
`EX. 2166, p. 9
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`

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`26. One of the breakthroughs that made supporting applications on FPGAs more
`
`feasible was SRC Computers’ (SRC) development of interfacing the FPGA with the
`
`memory bus in the SRC 6E and later the Crossbar switch in the SRC 6. This allowed
`
`for faster data movement between the FPGA and the microprocessor.
`
`27. State of the Art HPC Systems Using FPGAs: In the 1990s, there was a
`
`number of DARPA broad agency announcements stemming from recognizing the
`
`potential and the challenges for FPGA based computing systems. These
`
`announcements came under a DARPA program called the adaptive computing
`
`systems (ACS).
`
`28. By the early to mid-2000s, a few parallel computing systems with FPGAs
`
`supported by HPC vendors started to emerge, with the first ones being SRC and
`
`Starbridge. In 2002, and under a contract from the NSA LUCITE program, I led a
`
`team of multiple universities to study this emerging High-Performance Computing
`
`Technology (HPRC) with focus on SRC and Starbridge. The team included GW
`
`(Myself), GMU (Dr. Gaj) and USC (Dr. Buell). While the team had difficulties with
`
`the Starbridge product, the team was very satisfied with the initial tested machine
`
`from SRC, the SRC 6E. Eventually, Starbridge went out of business while SRC
`
`introduced its SRC 6 follow up. With the good experience from the SRC 6E in total
`
`productivity (performance plus user experience), the NSA and the team made the
`
`decision to purchase and continue further research investigations with the SRC 6. The
`
`PATENT OWNER DIRECTSTREAM, LLC
`EX. 2166, p. 10
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`

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`momentum in the High-Performance Reconfigurable Computing has risen then and
`
`traditional HPC companies like Silicon Graphics and Cray decided to join in the
`
`movement. The Cray solution was to buy an existing FPGA company and leverage
`
`their products, while the SGI Strategy was to build an FPGA board and integrated it
`
`their Altix product line. SRC commercial systems were ahead of the crowd for two
`
`reasons. First, for SRC, this was a core strategic product and nearly defining all what
`
`the company was focused on, and SRC as a commercial product for a high-
`
`performance reconfigurable computer was the first well integrated such system.
`
`Secondly, having come from a Vector Processing background (namely the Cray
`
`culture), SRC was very well positioned to bring to the table many ideas inspired by
`
`vector processing both on the side of code and architecture optimization. Examples of
`
`these are the development of the crossbar switch. The crossbar switch did not only
`
`connect the FPGA boards in a peer-to-peer fashion, but also provided connections to
`
`the modules of an interleaved shared memory subsystem much like a Cray vector
`
`architecture, and also added the microprocessor boards providing a great deal of
`
`flexibility. The support of such a large interleaved shared memory enables tackling
`
`much larger problems that go beyond embarrassingly parallel ones where all data can
`
`be kept local to the processor most of the time. The other high-performance
`
`computing companies on the other hand shortly abandoned their FPGA accelerated
`
`products and SRC continued down this path.
`
`PATENT OWNER DIRECTSTREAM, LLC
`EX. 2166, p. 11
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`

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`29. While by that time it was well understood that the FPGA technology can be
`
`rewarding and has a great potential, it was still seen as very hard to use by the domain
`
`scientist. As such, DARPA instituted a task force around 2006 to understand the main
`
`challenges for reconfigurable and high-performance reconfigurable computing. I
`
`searched for a report for such task force, but I unfortunately could not find one to
`
`include. In most of these gatherings however, the issues are typically that more progress
`
`is needed on supporting floating point operations and improving user productivity
`
`through improved tools for developments, debugging and compilation.
`
`30. Further, in 2007, DARPA funded a 4-university team [GWU, UF, VT, and
`
`BYU] to study the reconfigurable computing and high-performance reconfigurable
`
`computing productivity and tools and provide insights. To sum up, it was very well
`
`understood that while there are many efforts, there was no universal solution to the
`
`problem of working with reconfigurable computing and high-performance
`
`reconfigurable computing productively and each effort still brings something to the
`
`table and more still need to be done.
`
`VI. SUMMARY OF PRIOR ART REFERENCES
`
`31. As part of this declaration, I was also asked to provide my opinions on the
`
`teachings (or lack of teaching) of two prior art references, which I understand are being
`
`used by Microsoft in these IPRs. Specifically, [1005] Halverson, “The Functional
`
`Memory Approach to the Design of Custom Computing Machines,” Dissertation
`
`PATENT OWNER DIRECTSTREAM, LLC
`EX. 2166, p. 12
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`

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`University of Hawaii, August 1994 and [1007] Buell, Arnold, and Kleinfelder, Splash 2
`
`FPGAs In A Custom Computing Machine, IEEE Computer Society Press, 1996.
`
`B. The Functional Memory Computer [1005]
`
`32. Among the historical research efforts is that of Exhibit 1005 , which is a thesis
`
`dated August 1994, written by Richard Peyton Halverson, Jr. for his Ph.D. degree. The
`
`title of the thesis is THE FUNCTIONAL MEMORY APPROACH TO THE DESING
`
`OF CUSTOM COMPUTING MACHINES. The author describes the precise
`
`motivation for this work as: Coming up with a compiler that can take high-level
`
`definition of an application (a function/expression) and convert it to a description of how
`
`the hardware on an FPGA can be configured to perform this application.
`
`33. The author describes the thesis/project was to:
`
`⎯ Define and create a FMC, namely to construct, parallel to conventional
`
`memory (RAM), FPGAs that can implement predetermined functions
`
`where the program is expressed as a Decision Table
`
`⎯ Prototype of 4 FPGA for the FM plus a 5th for a minimal Processor
`
`⎯ Programming Language based on Decision Table (DT) variation of Pascal,
`
`an early structure programming tool that was strictly of interest to teaching
`
`structured programming for computer scientists
`
`⎯ Develop a compiler which reduces DT apps down to FGPA circuits and
`
`where FPGA performs the functions, and the processor performs
`
`load/stores/moves control flow
`
`34. The author showed three applications: Shortest-Path plus two sorting algorithms.
`
`He demonstrated Comparable number of load/stores both FMC and the traditional von
`
`PATENT OWNER DIRECTSTREAM, LLC
`EX. 2166, p. 13
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`

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`Neumann computers but with 35% less parallel steps in computations (due to
`
`parallelism)
`
`35. FMC Author Conclusion: Demonstrates the potential for FPGAs as a custom
`
`computing system for improving speed in computations, establishes that compiling from
`
`applications to FGPAs circuitry is much harder than compiling from applications to
`
`object code in von Neumann architectures. Program must be represented as a DT, upper
`
`left is for conditional stubs (conditions can be evaluated simultaneously), bottom right
`
`are action stubs and linked by rules. Decisions are evaluated in constant time,
`
`corresponding functions are executed in that same time. Length of execution depend on
`
`the number of iterations of executing the rule and the number of assignments.
`
`36. FPGAs extend the RAM and house the functions for execution from which the
`
`term Function Computer. Figure 1.13 shows clearly the Functional Memory containing
`
`both the FPGA and the RAM. Figure 1.4 shows a shared memory that overlaps the
`
`FPGAs and the same bus goes from the processor to RAM blocks and the FPGA.
`
`Figure 2.2 shows the FPGA and the memory using the same address and data buses.
`
`These were likely just to read/write the individual registers. The address decoding
`
`scheme was described in chapter 2. Figure 2.15 provides more implementation details
`
`including a minimal microprocessor built out of an FPGA and in addition to its role in a
`
`FMC it provides the ORing between the main memory and the FPGA outputs. There is
`
`no separate onboard memory and no DMA. However, even if this does have a memory
`
`PATENT OWNER DIRECTSTREAM, LLC
`EX. 2166, p. 14
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`

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`resident functional memory, this was specifically designed to fit with the FMC and the
`
`DT programming/execution model.
`
`37. The author distinguishes his work (FMC) from a number of related efforts based
`
`on whether the others are specialized or they can handle general purpose
`
`programs/functions, and whether data processed with the FPGA and can be read and
`
`written back to memory, and whether the programming model
`
`38. My impression is that most of these are:
`
` ⎯
`
` Single board accelerator, not a multiprocessor
`
`⎯ Single program and single user
`
`⎯ FMC is also restricted to DT programming model.
`
`⎯ The Splash 2 however is the more sophisticated development among all of
`
`those.
`
`⎯ The developments are hard to support legacy applications since the starting
`
`point is not necessarily high-level programming such as those used in real-life
`
`applications
`
`⎯ Remains an interesting academic exercise that was not followed by subsequent
`
`efforts, neither from the original developer nor from anyone else
`
`
`
`39. While FMC supports loops, developments covered do not embody loop
`
`optimization techniques of loop execution such as pipelining of nested loops and
`
`overlapped iterations or provide improved memory accesses via matching data layout
`
`and prefetching. Further the author indicated that potentially many optimizations at
`
`PATENT OWNER DIRECTSTREAM, LLC
`EX. 2166, p. 15
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`

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`functional level (beyond expressions) can take place however those were greatly limited
`
`by the size and capabilities of FPGAs at the time, which did not allow implementing
`
`them in logic.
`
`C. Splash 2 [1007]
`
`40. Splash 2 has a much more ambitious goal citing from the beginning the need to
`
`address real problems that conventional computers can solve, but just more efficiently.
`
`41. Splash 2 is made out of 16 array boards, each with 17 FPGAs. Splash 2 is an
`
`attached computer connected via an interface board to a Sun workstation serving as a
`
`front end/host for each of use and management. The interface board has optional direct
`
`data in and out connections. The array board is therefore interacting with the Sun
`
`workstation through an Sbus connector. The data path is extending in a linear manner
`
`with the SIMD bus bringing in data from the interface board to the first array, which can
`
`then transfer the data to the second board and so on, where each board connects to the
`
`one before and one after with dedicated buses in a daisy chain manner. Data from the
`
`last board returns to the interface board through the Rbus. Loading and unloading
`
`Splash 2 using DMA over the Sbus was an order of magnitude faster than the VMEbus
`
`in its predecessor Splash 1. However the actual observed speed was about 50% of the
`
`maximum limit due to limitations of the buffering design.
`
`42. Programming Splash 2 appears to be problematic. The early on design decision
`
`was to make VHDL the primary programming tool with other tools perhaps developing
`
`PATENT OWNER DIRECTSTREAM, LLC
`EX. 2166, p. 16
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`

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`later. VHDL simply put requires digital hardware engineering design skills.
`
`Programming only skills would not be sufficient since programs describe circuitry and a
`
`typical domain scientist (like a biologist or even a computational biologist) would never
`
`be able to develop his application. Second, VHDL programs only address the FPGA
`
`side of the system, completely reducing the duty of the host CPU-based system to user
`
`interfacing. The CPU as such does not play any role in the computations even when it is
`
`available. Finally, VHDL programs do not have any specific built in optimization with
`
`respect to loop and prefetching optimizations for example. All these would have to be
`
`done in a brute force manner by the programmer. Eventually the dbC language to
`
`program Splash 2 has emerged. dbC is a superset of the C language which for the
`
`FPGAs emphasizes single instruction multiple data (SIMD). SIMD refers to
`
`performing one operation over many data items simultaneously. The compiler translates
`
`dbC programs into a C language portion for a front-end Sun workstation and VHDL for
`
`SIMD operation on the FPGAs. dbC however was not fully developed and among its
`
`major drawbacks was its inability to leverage the on-board memories, which is essential
`
`for many applications.
`
`43. Splash had limited support for loops and optimized loop execution to my
`
`understanding. According to [1005], in Splash 2 looping was handled by the Sun
`
`workstation front-end rather than in the FPGA, which is a great deficiency. In addition,
`
`in the crossbar used by Splash 2, only FPGAs connect to the crossbar while memories
`
`PATENT OWNER DIRECTSTREAM, LLC
`EX. 2166, p. 17
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`attach directly to the FPGA. Those memories are therefore are not all seen by each
`
`FPGA as a shared memory, thereby limiting the range and size of applications that can
`
`be used in a productive manner. Optimizing access to a large strided array would be
`
`hard and optimizing nested loops for multidimensional arrays would be very hard. In
`
`fact, in page 179, the program manager indicates that the system suffered user
`
`productivity issues as creating a double loop was very difficult even for sophisticated
`
`users who are aware of the project inside issues.
`
`
`
`PATENT OWNER DIRECTSTREAM, LLC
`EX. 2166, p. 18
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`

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`I, Tarek El-Ghazawi, I declare that all statements made herein are true and that
`
`these statements were made with knowledge that willful false statements are
`
`punishable by fine or imprisonment, or both, under Section 1001 of Title 18 of the
`
`United States Code. If called as a witness during the trial in this matter, I am
`
`prepared to testify competently about them. I am over the age of eighteen.
`
`
`
`Dated: July 23, 2019
`
`
`
`
`
`
`
`
`
`
`
`
`Tarek El-Ghazawi
`
`
`
`
`
`
`
`
`
`PATENT OWNER DIRECTSTREAM, LLC
`EX. 2166, p. 19
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`

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`Exhibit A
`
`
`
`DR. TAREK EL-GHAZAWI
`curriculum vitae
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`PATENT OWNER DIRECTSTREAM, LLC
`EX. 2166, p. 20
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`Curriculum Vita
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`Tarek El-Ghazawi
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`Professor of ECE and IEEE Fellow
`Director, GW Institute for Massively Parallel Applications and Computing Technologies
`(IMPACT)
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`The George Washington University
`Science and Engineering Hall
`800 22nd Street, N.W.
`Washington, D.C. 20052
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`(202)246-5783 [Cell]
`tarek@gwu.edu [Email]
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`http://tarek.seas.gwu.edu
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`PATENT OWNER DIRECTSTREAM, LLC
`EX. 2166, p. 21
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`PRESENT OCCUPATION:
`Professor, Department of Electrical and Computer Engineering, The George Washington
`University, Washington D.C.
`[8/2003-present]
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`Director, Institute for Massively Parallel Applications and Computing Technology (IMPACT),
`and the GWU High-Performance Computing Academic Signature Program.
`[4/2007-present]
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`Director, GW Strategic Academic Excellence Program in High-Performance Computing
`[7/2006-present]
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`EDUCATION:
`Doctor of Philosophy in Electrical and Computer Engineering, New Mexico State University,
`May 1988
`Dissertation Topic: Theory and Design of a Real-Time Motion Detection Computer System
`Major Field: Computer Engineering
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`Minor Field: Computer Science
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`Master of Science in Electrical and Computer Engineering, New Mexico State University,
`May 1984
`Major Field: Computer Control Systems
`Thesis Title: Analytical Design of Digital Controllers with Minimum Settling Time
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`Master of Science in Control Systems Engineering [completed courses in Linear Control,
`Stochastic Control, Optimal Control, Nonlinear Control], Cairo University, May 2002. Cairo
`University. (Transferred to U.S. after completing above course work)
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`Bachelor of Science in Electronics and Communications Engineering, Helwan University,
`Cairo, Egypt, May 1980
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`AREAS OF RESEARCH INTEREST:
`• High-Performance Computing
`• Heterogeneous and Extreme Computing Systems
`• Convergence of HPC, Big Data, Cloud, AI and IoT
`• Computer Architectures
`• Nano-photonic enabled computing
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`Image Processing and Remote Sensing Applications
`• Parallel Programming Models
`• Performance Evaluations and Workload Characterization
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`HONORS AND PROFESSIONAL MEMBERSHIPS:
`• Fellow, Institute of Electrical and Electronics Engineers (IEEE)
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`PATENT OWNER DIRECTSTREAM, LLC
`EX. 2166, p. 22
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`• Alexander von Humboldt Research Award, Humboldt Foundation, Germany( Given to 100
`scientist per year from across the world and across all disciplines)
`• 2012 Alexander Schwarzkopf Prize for Technological Innovation
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`IEEE Outstanding Leadership Award, IEEE Technical Committee on Scalable Computing
`•
`IEEE Computer Society Distinguished Visitors Program (DVP) Speaker.
`• U.K. Royal Academy of Engineering Distinguished Visiting Fellow
`• GWU SEAS Distinguished Researcher Award, 2015
`• Senior Fulbright Scholar, 2011-2012.
`•
`IBM Faculty Fellow, IBM Center for Advanced Studies, Toronto.
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`IBM Faculty Partnership Award, 2004
`• Member, ACM SigHPC
`• FIP WG10.3 (elected)
`• Phi Kappa Phi National Honor Society
`• Member, IEEE Computer Society Fellows Selection Committee, 2012-present.
`• Member, SigmaXi, The Scientific Research Honor Society
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`SPONSORED RESEARCH AWARDS:
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`1. RAISE: The Reconfigurable Optical Computer (ROC), National Science Foundation, $900K.
`Tarek El-Ghazawi (PI) and Volker Sorger (coPI). NSF (8/17-7/21).
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`2. Collaborative Research: Nanophotonic Neuromorphic Computing, $1.33M. NSF/SRC Pruncal
`(PI, Princeton), Sorger (coPI), and El-Ghazawi (coPI). (10/17-9/20).
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`3. Intel Parallel Computing Center, Intel Corporation, $250K in cash in addition to software,
`hardware and training. Tarek El-Ghazawi (P.I.). (6/16-12/18).
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`4. High-Performance Computing for Big Data, National Institute of Standards and Technology
`(NIST)/ Department of Commerce, $100K. Tarek El-Ghazawi (PI). 3/1/16-11/30/16.
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`5. Dynamically Adaptive Hybrid Nanoplasmonic Networks on Chip (NoCs). Airforce Office of
`Scientific Research, $752K. Tarek El-Ghazawi (P.I.) with Volker Sorger (CoPI) and Vikram
`Narayana (CoPI). (9/15-9/18).
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`6. Architecture Support for Advancing PGAS (ASAP). National Science Foundation, $230K.
`Tarek El-Ghazawi (P.I.). (8/15-7/17).
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`7. Sustainable co-synthesis of cement and fuels, NSF $1.5M, co-PI Tarek El-Ghazawi, with PI
`Stuart Licht, co-PIs Peter LaPuma, Henry Teng, Sabrina McCormick. (08/01/12 - 07/31/16)
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`8. The NSF Industry/University Center for Reconfigurable High-Perfromance Computing
`(CHREC). Collaborative National Center with Sites at UF, VT, and BYU. GWU Site jointly
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`PATENT OWNER DIRECTSTREAM, LLC
`EX. 2166, p. 23
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`funded by NSF, Intel, AMD, HP, SGI, NSA, ONR, NRO, Arctic Region Supercomputing
`Center. GWU site funding (3/06-8/15, $2M). Tarek El-Ghazawi (GWU P.I.).
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`9. A Scalable Heterogeneous Architecture for Big Data, National Institute for Standards and
`Technology (NIST)/ Department of Commerce, $125K. Tarek El-Ghazawi (PI). 9/1/14-
`8/31/15.
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`10. MRI: Acquisition of a High-Performance Instrument for Interdisciplinary Computational
`Science and Engineering. NSF, $1.1M. Tarek El-Ghazawi (P.I.) with Mittal, Lang, Lee and
`Briscoe. (10/09-09/14).
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`11. Collaborative Research: FRP: Productive Scientific Computing on Heterogeneous Systems.
`NSF, $200K. Tarek El-Ghazawi (GW P.I.) with Alan George (UF). 08/01/12 - 01/31/14
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`12. Clinical and Translational Science Institute at Children’s National (CTSI-CN), NIH. PIs (Jill
`Joseph, MD; and Peter Hotez, MD). Tarek El-Ghazawi (Associate Director, Biomedical
`Informatics) (6/10-5/15)
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`13. Collaborative Research: Development of efficient p